Module Definition
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Module Instance : tb.dut.u_to_prog_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.54 93.44 65.77 69.23 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.52 82.67 63.51 66.67 81.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 67.62 76.92 68.57 25.00 100.00
u_reqfifo 87.85 95.00 73.08 83.33 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 68.01 91.43 51.85 68.75 60.00
u_sram_byte 100.00 100.00
u_sramreqfifo 64.11 86.11 47.83 62.50 60.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_to_rd_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.49 95.38 77.39 85.19 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.53 85.78 76.15 100.00 80.72 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 66.91 76.92 65.71 25.00 100.00
u_reqfifo 87.85 95.00 73.08 83.33 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 97.84 100.00 89.19 100.00 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 86.89 95.00 69.23 83.33 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_tl_adapter_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.93 96.92 81.90 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.98 89.60 80.17 100.00 90.11 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cmd_intg_check.u_cmd_intg_chk 100.00 100.00 100.00 100.00
u_err 67.62 76.92 68.57 25.00 100.00
u_reqfifo 95.19 100.00 80.77 100.00 100.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 96.32 100.00 85.29 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 95.19 100.00 80.77 100.00 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
78.54 93.44
tb.dut.u_to_prog_fifo

Line No.TotalCoveredPercent
TOTAL615793.44
ALWAYS9333100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298675.00
ALWAYS2496583.33
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40600
CONT_ASSIGN40800
CONT_ASSIGN41500
ALWAYS4213266.67
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 unreachable
MISSING_ELSE
102 1 1
107 1 1
114 1 1
125 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 0 1
235 1 1
236 0 1
239 1 1
242 1 1
249 1 1
251 1 1
252 1 1
253 0 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 unreachable
408 unreachable
415 unreachable
421 1 1
425 1 1
427 0 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
89.49 95.38
tb.dut.u_to_rd_fifo

Line No.TotalCoveredPercent
TOTAL656295.38
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298675.00
ALWAYS2496583.33
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 0 1
235 1 1
236 1 1
239 0 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 0 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
91.93 96.92
tb.dut.u_tl_adapter_eflash

Line No.TotalCoveredPercent
TOTAL656396.92
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298787.50
ALWAYS2496583.33
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
239 0 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 0 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
78.54 65.77
tb.dut.u_to_prog_fifo

TotalCoveredPercent
Conditions1117365.77
Logical1117365.77
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       125
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT3,T4,T5
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT32,T33,T9
11CoveredT3,T4,T5

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT3,T4,T5
1Not Covered

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT3,T4,T5
1Not Covered

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T5
11Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT32,T33,T9
101CoveredT3,T4,T5
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT3,T4,T17
01CoveredT1,T2,T3
10CoveredT3,T4,T5

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T4,T5
110Not Covered
111CoveredT3,T4,T5

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT3,T4,T5

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT3,T4,T5

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11Not Covered

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT3,T4,T5
10Unreachable
11Unreachable

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
89.49 77.39
tb.dut.u_to_rd_fifo

TotalCoveredPercent
Conditions1158977.39
Logical1158977.39
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T13,T14
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT6,T13,T14
010CoveredT6,T13,T14
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T3,T6
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T6
11CoveredT1,T3,T6

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT1,T3,T6

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T3,T6
10CoveredT4,T20,T34
11CoveredT1,T3,T6

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T3,T6

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T3,T6

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T3,T4
01Not Covered
10CoveredT6,T35,T36

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT1,T3,T6

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T35,T36
11CoveredT1,T3,T4

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T6
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T6
11Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT6,T35,T36

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT4,T20,T34
101CoveredT5,T37,T32
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT6,T4,T20
01CoveredT1,T2,T3
10CoveredT1,T3,T6

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T6
110Not Covered
111CoveredT1,T3,T6

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T6
11Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T3,T6
1Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T6
11Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T6

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT5,T37,T32
10Not Covered
11CoveredT1,T3,T6

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T6

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
91.93 81.90
tb.dut.u_tl_adapter_eflash

TotalCoveredPercent
Conditions1169581.90
Logical1169581.90
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT38,T31,T39

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT38,T31,T39
010Unreachable
100CoveredT38,T31,T39

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T6,T4
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T6,T4
01CoveredT1,T6,T40
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T6,T40

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT6,T40,T8
01CoveredT1,T6,T40
10CoveredT1,T6,T17

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T6,T40
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T6,T17
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T4,T19
000001CoveredT38,T31,T39
000010CoveredT1,T6,T40
000100CoveredT41,T42,T43
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T18,T7
11CoveredT1,T4,T19

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T20,T21
11CoveredT1,T4,T19

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT4,T18,T7
11CoveredT1,T4,T19

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T19

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T19

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T4,T19
01CoveredT41,T42,T38
10CoveredT4,T44,T20

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT41,T42,T38
1110Not Covered
1111CoveredT1,T4,T19

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T44,T20
11CoveredT1,T4,T19

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT41,T42,T38
10CoveredT1,T4,T19
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T19
11Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T19
11CoveredT4,T44,T20

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT4,T18,T7
101CoveredT42,T45
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT4,T18,T7
01CoveredT1,T2,T3
10CoveredT1,T4,T19

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T7,T8
110CoveredT41,T42,T38
111CoveredT1,T4,T19

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T19
11Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T4,T19
1Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T19
11Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T6,T4
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T19

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T4,T19
10Not Covered
11CoveredT1,T4,T19

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT41,T42,T38
11CoveredT1,T4,T19

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 27 26 96.30
TERNARY 107 2 2 100.00
TERNARY 291 2 2 100.00
TERNARY 297 3 2 66.67
TERNARY 324 2 2 100.00
TERNARY 447 2 2 100.00
IF 93 3 3 100.00
IF 231 4 4 100.00
IF 251 3 3 100.00
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T3,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T6,T38,T13
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T41,T42,T38
1 0 1 Covered T1,T3,T6
1 0 0 Covered T3,T4,T5
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T3,T6
1 0 Covered T3,T4,T5
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 981250704 979106175 0 0
DataIntgOptions_A 2628 2628 0 0
ReqOutKnown_A 981250704 979106175 0 0
SramDwHasByteGranularity_A 2628 2628 0 0
SramDwIsMultipleOfTlulWidth_A 2628 2628 0 0
TlOutKnown_A 981250704 979106175 0 0
TlOutPayloadKnown_A 981250704 9974097 0 0
TlOutPayloadKnown_AKnownEnable 981250704 979106175 0 0
WdataOutKnown_A 981250704 979106175 0 0
WeOutKnown_A 981250704 979106175 0 0
WmaskOutKnown_A 981250704 979106175 0 0
adapterNoReadOrWrite 2628 2628 0 0
rvalidHighReqFifoEmpty 981250704 5954544 0 0
rvalidHighWhenRspFifoFull 980816715 5949278 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 981250704 979106175 0 0
T1 27585 27114 0 0
T2 11526 9576 0 0
T3 491220 490986 0 0
T4 951054 950841 0 0
T5 525054 524862 0 0
T6 394107 318525 0 0
T11 12153 10047 0 0
T15 13413 13128 0 0
T16 2988 2736 0 0
T17 136581 136068 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2628 2628 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T11 3 3 0 0
T15 3 3 0 0
T16 3 3 0 0
T17 3 3 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 981250704 979106175 0 0
T1 27585 27114 0 0
T2 11526 9576 0 0
T3 491220 490986 0 0
T4 951054 950841 0 0
T5 525054 524862 0 0
T6 394107 318525 0 0
T11 12153 10047 0 0
T15 13413 13128 0 0
T16 2988 2736 0 0
T17 136581 136068 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2628 2628 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T11 3 3 0 0
T15 3 3 0 0
T16 3 3 0 0
T17 3 3 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2628 2628 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T11 3 3 0 0
T15 3 3 0 0
T16 3 3 0 0
T17 3 3 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 981250704 979106175 0 0
T1 27585 27114 0 0
T2 11526 9576 0 0
T3 491220 490986 0 0
T4 951054 950841 0 0
T5 525054 524862 0 0
T6 394107 318525 0 0
T11 12153 10047 0 0
T15 13413 13128 0 0
T16 2988 2736 0 0
T17 136581 136068 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 981250704 9974097 0 0
T1 18390 263 0 0
T2 7684 0 0 0
T3 491220 3648 0 0
T4 951054 56125 0 0
T5 525054 41211 0 0
T6 394107 1376 0 0
T7 0 32805 0 0
T8 0 31101 0 0
T11 12153 0 0 0
T15 13413 0 0 0
T16 2988 0 0 0
T17 136581 1626 0 0
T18 0 8 0 0
T19 4161 119 0 0
T40 0 7384 0 0
T44 0 8 0 0
T46 1505 1 0 0
T47 0 3 0 0
T48 0 4128 0 0
T49 0 4 0 0
T50 0 8 0 0
T51 0 4 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 981250704 979106175 0 0
T1 27585 27114 0 0
T2 11526 9576 0 0
T3 491220 490986 0 0
T4 951054 950841 0 0
T5 525054 524862 0 0
T6 394107 318525 0 0
T11 12153 10047 0 0
T15 13413 13128 0 0
T16 2988 2736 0 0
T17 136581 136068 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 981250704 979106175 0 0
T1 27585 27114 0 0
T2 11526 9576 0 0
T3 491220 490986 0 0
T4 951054 950841 0 0
T5 525054 524862 0 0
T6 394107 318525 0 0
T11 12153 10047 0 0
T15 13413 13128 0 0
T16 2988 2736 0 0
T17 136581 136068 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 981250704 979106175 0 0
T1 27585 27114 0 0
T2 11526 9576 0 0
T3 491220 490986 0 0
T4 951054 950841 0 0
T5 525054 524862 0 0
T6 394107 318525 0 0
T11 12153 10047 0 0
T15 13413 13128 0 0
T16 2988 2736 0 0
T17 136581 136068 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 981250704 979106175 0 0
T1 27585 27114 0 0
T2 11526 9576 0 0
T3 491220 490986 0 0
T4 951054 950841 0 0
T5 525054 524862 0 0
T6 394107 318525 0 0
T11 12153 10047 0 0
T15 13413 13128 0 0
T16 2988 2736 0 0
T17 136581 136068 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 2628 2628 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T11 3 3 0 0
T15 3 3 0 0
T16 3 3 0 0
T17 3 3 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 981250704 5954544 0 0
T1 18390 263 0 0
T2 7684 0 0 0
T3 327480 2432 0 0
T4 634036 48813 0 0
T5 350036 6144 0 0
T6 262738 1376 0 0
T7 0 32805 0 0
T8 0 31101 0 0
T11 8102 0 0 0
T15 8942 0 0 0
T16 1992 0 0 0
T17 91054 0 0 0
T18 0 1 0 0
T19 0 78 0 0
T40 0 4928 0 0
T44 0 8 0 0
T48 0 2712 0 0
T49 0 4 0 0
T50 0 8 0 0
T51 0 4 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 980816715 5949278 0 0
T1 18390 263 0 0
T2 7684 0 0 0
T3 327480 2432 0 0
T4 634036 48813 0 0
T5 350036 6144 0 0
T6 131564 0 0 0
T7 0 32805 0 0
T8 0 31101 0 0
T11 8102 0 0 0
T15 8942 0 0 0
T16 1992 0 0 0
T17 91054 0 0 0
T18 0 1 0 0
T19 0 78 0 0
T40 0 4928 0 0
T44 0 8 0 0
T48 0 2712 0 0
T49 0 106 0 0
T50 0 8 0 0
T51 0 4 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
TOTAL615793.44
ALWAYS9333100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298675.00
ALWAYS2496583.33
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40600
CONT_ASSIGN40800
CONT_ASSIGN41500
ALWAYS4213266.67
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 unreachable
MISSING_ELSE
102 1 1
107 1 1
114 1 1
125 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 0 1
235 1 1
236 0 1
239 1 1
242 1 1
249 1 1
251 1 1
252 1 1
253 0 1
255 1 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 unreachable
408 unreachable
415 unreachable
421 1 1
425 1 1
427 0 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Instance : tb.dut.u_to_prog_fifo
TotalCoveredPercent
Conditions1117365.77
Logical1117365.77
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       125
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT3,T4,T5
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT32,T33,T9
11CoveredT3,T4,T5

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT3,T4,T5
1Not Covered

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT3,T4,T5
1Not Covered

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T5
11Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT32,T33,T9
101CoveredT3,T4,T5
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT3,T4,T17
01CoveredT1,T2,T3
10CoveredT3,T4,T5

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T4,T5
110Not Covered
111CoveredT3,T4,T5

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T5

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT3,T4,T5

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT3,T4,T5

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11Not Covered

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT3,T4,T5
10Unreachable
11Unreachable

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
Branches 26 18 69.23
TERNARY 107 2 2 100.00
TERNARY 291 2 1 50.00
TERNARY 297 3 1 33.33
TERNARY 324 2 2 100.00
TERNARY 447 2 1 50.00
IF 93 2 2 100.00
IF 231 4 2 50.00
IF 251 3 2 66.67
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Not Covered
1 0 1 Not Covered
1 0 0 Covered T3,T4,T5
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Covered T3,T4,T5
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T3,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 12 85.71
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 12 85.71




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 327083568 326368725 0 0
DataIntgOptions_A 876 876 0 0
ReqOutKnown_A 327083568 326368725 0 0
SramDwHasByteGranularity_A 876 876 0 0
SramDwIsMultipleOfTlulWidth_A 876 876 0 0
TlOutKnown_A 327083568 326368725 0 0
TlOutPayloadKnown_A 327083568 2241196 0 0
TlOutPayloadKnown_AKnownEnable 327083568 326368725 0 0
WdataOutKnown_A 327083568 326368725 0 0
WeOutKnown_A 327083568 326368725 0 0
WmaskOutKnown_A 327083568 326368725 0 0
adapterNoReadOrWrite 876 876 0 0
rvalidHighReqFifoEmpty 327083568 0 0 0
rvalidHighWhenRspFifoFull 327083568 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 2241196 0 0
T3 163740 1216 0 0
T4 317018 7312 0 0
T5 175018 13789 0 0
T6 131369 0 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 1626 0 0
T18 0 7 0 0
T19 4161 41 0 0
T40 0 2456 0 0
T46 1505 1 0 0
T47 0 3 0 0
T48 0 1416 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 0 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
TOTAL656295.38
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298675.00
ALWAYS2496583.33
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 0 1
235 1 1
236 1 1
239 0 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 0 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Instance : tb.dut.u_to_rd_fifo
TotalCoveredPercent
Conditions1158977.39
Logical1158977.39
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T13,T14
10Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT6,T13,T14
010CoveredT6,T13,T14
100Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T3,T6
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T6
11CoveredT1,T3,T6

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT1,T3,T6

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T3,T6
10CoveredT4,T20,T34
11CoveredT1,T3,T6

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T3,T6

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T3,T6

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T3,T4
01Not Covered
10CoveredT6,T35,T36

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT1,T3,T6

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T35,T36
11CoveredT1,T3,T4

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T6
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T6
11Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT6,T35,T36

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT4,T20,T34
101CoveredT5,T37,T32
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT6,T4,T20
01CoveredT1,T2,T3
10CoveredT1,T3,T6

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T6
110Not Covered
111CoveredT1,T3,T6

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T6
11Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T3,T6
1Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T6
11Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T6

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT5,T37,T32
10Not Covered
11CoveredT1,T3,T6

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T6

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

Branch Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
Branches 27 23 85.19
TERNARY 107 2 2 100.00
TERNARY 291 2 2 100.00
TERNARY 297 3 2 66.67
TERNARY 324 2 2 100.00
TERNARY 447 2 2 100.00
IF 93 3 3 100.00
IF 231 4 2 50.00
IF 251 3 2 66.67
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T3,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T6,T13,T14
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Not Covered
1 0 1 Covered T1,T3,T6
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T3,T6
1 0 Not Covered
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 327083568 326368725 0 0
DataIntgOptions_A 876 876 0 0
ReqOutKnown_A 327083568 326368725 0 0
SramDwHasByteGranularity_A 876 876 0 0
SramDwIsMultipleOfTlulWidth_A 876 876 0 0
TlOutKnown_A 327083568 326368725 0 0
TlOutPayloadKnown_A 327083568 3435972 0 0
TlOutPayloadKnown_AKnownEnable 327083568 326368725 0 0
WdataOutKnown_A 327083568 326368725 0 0
WeOutKnown_A 327083568 326368725 0 0
WmaskOutKnown_A 327083568 326368725 0 0
adapterNoReadOrWrite 876 876 0 0
rvalidHighReqFifoEmpty 327083568 2446076 0 0
rvalidHighWhenRspFifoFull 326649579 2440810 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 3435972 0 0
T1 9195 254 0 0
T2 3842 0 0 0
T3 163740 2432 0 0
T4 317018 7522 0 0
T5 175018 27422 0 0
T6 131369 1376 0 0
T7 0 16096 0 0
T8 0 14352 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T19 0 72 0 0
T40 0 4928 0 0
T48 0 2712 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 2446076 0 0
T1 9195 254 0 0
T2 3842 0 0 0
T3 163740 2432 0 0
T4 317018 7522 0 0
T5 175018 6144 0 0
T6 131369 1376 0 0
T7 0 16096 0 0
T8 0 14352 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T19 0 72 0 0
T40 0 4928 0 0
T48 0 2712 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 326649579 2440810 0 0
T1 9195 254 0 0
T2 3842 0 0 0
T3 163740 2432 0 0
T4 317018 7522 0 0
T5 175018 6144 0 0
T6 195 0 0 0
T7 0 16096 0 0
T8 0 14352 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T19 0 72 0 0
T40 0 4928 0 0
T48 0 2712 0 0
T49 0 102 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
TOTAL656396.92
ALWAYS9344100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22411100.00
ALWAYS2298787.50
ALWAYS2496583.33
CONT_ASSIGN26311100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
ALWAYS35466100.00
ALWAYS36655100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41511100.00
ALWAYS42133100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
94 1 1
95 1 1
96 1 1
MISSING_ELSE
102 1 1
107 1 1
114 1 1
119 1 1
139 1 1
151 1 1
222 1 1
223 1 1
224 1 1
229 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
239 0 1
242 1 1
249 1 1
251 1 1
252 1 1
253 1 1
255 0 1
258 1 1
263 1 1
267 1 1
286 1 1
291 1 1
297 1 1
301 1 1
321 1 1
322 1 1
323 1 1
324 1 1
354 1 1
355 1 1
357 1 1
358 1 1
359 1 1
360 1 1
MISSING_ELSE
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
377 1 1
378 1 1
387 1 1
388 1 1
390 1 1
391 1 1
398 1 1
401 1 1
405 1 1
406 1 1
408 1 1
415 1 1
421 1 1
425 1 1
427 1 1
MISSING_ELSE
442 1 1
447 1 1
452 unreachable


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalCoveredPercent
Conditions1169581.90
Logical1169581.90
Non-Logical00
Event00

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT38,T31,T39

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT38,T31,T39
010Unreachable
100CoveredT38,T31,T39

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T6,T4
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T6,T4
01CoveredT1,T6,T40
10CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T6,T40

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT6,T40,T8
01CoveredT1,T6,T40
10CoveredT1,T6,T17

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T6,T40
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T6,T17
1CoveredT1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T4,T19
000001CoveredT38,T31,T39
000010CoveredT1,T6,T40
000100CoveredT41,T42,T43
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T18,T7
11CoveredT1,T4,T19

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T20,T21
11CoveredT1,T4,T19

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT4,T18,T7
11CoveredT1,T4,T19

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T19

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T4,T19

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T4,T19
01CoveredT41,T42,T38
10CoveredT4,T44,T20

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT41,T42,T38
1110Not Covered
1111CoveredT1,T4,T19

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T44,T20
11CoveredT1,T4,T19

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT41,T42,T38
10CoveredT1,T4,T19
11Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T19
11Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T19
11CoveredT4,T44,T20

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT4,T18,T7
101CoveredT42,T45
110Not Covered
111CoveredT1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT4,T18,T7
01CoveredT1,T2,T3
10CoveredT1,T4,T19

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T7,T8
110CoveredT41,T42,T38
111CoveredT1,T4,T19

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T19
11Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T4,T19
1Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T19
11Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T6,T4
1CoveredT1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T19

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T4,T19
10Not Covered
11CoveredT1,T4,T19

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT41,T42,T38
11CoveredT1,T4,T19

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T19

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
Branches 27 24 88.89
TERNARY 107 2 2 100.00
TERNARY 291 2 2 100.00
TERNARY 297 3 2 66.67
TERNARY 324 2 2 100.00
TERNARY 447 2 2 100.00
IF 93 3 3 100.00
IF 231 4 3 75.00
IF 251 3 2 66.67
IF 357 2 2 100.00
IF 369 2 2 100.00
IF 425 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T6,T4


LineNo. Expression -1-: 291 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 297 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 297 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T4,T19
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 447 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if ((!rst_ni)) -2-: 95 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T38,T31,T39
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if (reqfifo_rvalid) -2-: 232 if (reqfifo_rdata.error) -3-: 235 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T41,T42,T38
1 0 1 Covered T1,T4,T19
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 251 if (reqfifo_rvalid) -2-: 252 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T4,T19
1 0 Not Covered
0 - Covered T1,T2,T3


LineNo. Expression -1-: 357 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 425 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T4,T19
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 327083568 326368725 0 0
DataIntgOptions_A 876 876 0 0
ReqOutKnown_A 327083568 326368725 0 0
SramDwHasByteGranularity_A 876 876 0 0
SramDwIsMultipleOfTlulWidth_A 876 876 0 0
TlOutKnown_A 327083568 326368725 0 0
TlOutPayloadKnown_A 327083568 4296929 0 0
TlOutPayloadKnown_AKnownEnable 327083568 326368725 0 0
WdataOutKnown_A 327083568 326368725 0 0
WeOutKnown_A 327083568 326368725 0 0
WmaskOutKnown_A 327083568 326368725 0 0
adapterNoReadOrWrite 876 876 0 0
rvalidHighReqFifoEmpty 327083568 3508468 0 0
rvalidHighWhenRspFifoFull 327083568 3508468 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 4296929 0 0
T1 9195 9 0 0
T2 3842 0 0 0
T3 163740 0 0 0
T4 317018 41291 0 0
T5 175018 0 0 0
T6 131369 0 0 0
T7 0 16709 0 0
T8 0 16749 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T18 0 1 0 0
T19 0 6 0 0
T44 0 8 0 0
T49 0 4 0 0
T50 0 8 0 0
T51 0 4 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 326368725 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 876 876 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 3508468 0 0
T1 9195 9 0 0
T2 3842 0 0 0
T3 163740 0 0 0
T4 317018 41291 0 0
T5 175018 0 0 0
T6 131369 0 0 0
T7 0 16709 0 0
T8 0 16749 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T18 0 1 0 0
T19 0 6 0 0
T44 0 8 0 0
T49 0 4 0 0
T50 0 8 0 0
T51 0 4 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083568 3508468 0 0
T1 9195 9 0 0
T2 3842 0 0 0
T3 163740 0 0 0
T4 317018 41291 0 0
T5 175018 0 0 0
T6 131369 0 0 0
T7 0 16709 0 0
T8 0 16749 0 0
T11 4051 0 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T18 0 1 0 0
T19 0 6 0 0
T44 0 8 0 0
T49 0 4 0 0
T50 0 8 0 0
T51 0 4 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%