Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl_lcmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.58 99.17 94.79 92.11 96.81 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_hw_if 96.58 99.17 94.79 92.11 96.81 100.00



Module Instance : tb.dut.u_flash_hw_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.58 99.17 94.79 92.11 96.81 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.19 98.53 95.37 95.83 92.11 95.27 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_addr_cnt 100.00 100.00
u_addr_sync_reqack 96.46 95.83 100.00 90.00 100.00
u_bus_intg 100.00 100.00
u_data_intg_chk 100.00 100.00 100.00
u_data_sync_reqack 96.46 95.83 100.00 90.00 100.00
u_page_cnt 78.79 78.79
u_prim_flop_err_sts 100.00 100.00 100.00
u_rma_state_regs 100.00 100.00 100.00 100.00
u_seed_cnt 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_sync_flash_init 100.00 100.00 100.00
u_sync_rma_req 100.00 100.00 100.00 100.00
u_wipe_idx_cnt 100.00 100.00
u_word_cnt 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_lcmgr
Line No.TotalCoveredPercent
TOTAL24224099.17
CONT_ASSIGN14911100.00
ALWAYS15233100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17111100.00
ALWAYS17477100.00
CONT_ASSIGN18511100.00
ALWAYS22555100.00
CONT_ASSIGN24111100.00
CONT_ASSIGN24511100.00
ALWAYS24933100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
ALWAYS26266100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN27811100.00
ALWAYS35799100.00
CONT_ASSIGN37811100.00
ALWAYS384858498.82
CONT_ASSIGN60511100.00
ALWAYS61133100.00
ALWAYS66877100.00
ALWAYS6831010100.00
ALWAYS70022100.00
CONT_ASSIGN70911100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN73211100.00
CONT_ASSIGN73611100.00
CONT_ASSIGN73711100.00
CONT_ASSIGN74911100.00
ALWAYS756666598.48
CONT_ASSIGN88611100.00
CONT_ASSIGN88711100.00
CONT_ASSIGN88811100.00
CONT_ASSIGN88900
CONT_ASSIGN89000
CONT_ASSIGN89111100.00
CONT_ASSIGN89211100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89511100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN90011100.00
CONT_ASSIGN90111100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN90411100.00
CONT_ASSIGN90611100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN91311100.00
CONT_ASSIGN91611100.00
ALWAYS92700
CONT_ASSIGN93411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
149 1 1
152 3 3
170 1 1
171 1 1
174 1 1
175 1 1
176 1 1
177 1 1
179 1 1
180 1 1
181 1 1
185 1 1
225 1 1
226 1 1
227 1 1
229 1 1
230 1 1
241 1 1
245 1 1
249 1 1
250 1 1
252 1 1
259 1 1
260 1 1
262 1 1
263 1 1
264 1 1
266 1 1
268 1 1
269 1 1
MISSING_ELSE
276 1 1
277 1 1
278 1 1
357 1 1
358 1 1
359 1 1
361 1 1
362 1 1
363 1 1
MISSING_ELSE
366 1 1
367 1 1
368 1 1
MISSING_ELSE
378 1 1
384 1 1
387 1 1
388 1 1
389 1 1
390 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
400 1 1
402 1 1
403 1 1
404 1 1
407 1 1
409 1 1
410 1 1
413 1 1
414 1 1
417 1 1
418 1 1
421 1 1
423 1 1
425 1 1
431 1 1
432 1 1
433 1 1
434 1 1
MISSING_ELSE
439 1 1
440 1 1
441 1 1
442 1 1
443 1 1
444 1 1
MISSING_ELSE
449 1 1
450 1 1
451 1 1
452 1 1
453 1 1
455 1 1
MISSING_ELSE
462 1 1
465 1 1
466 1 1
467 1 1
470 1 1
471 1 1
472 1 1
473 1 1
474 1 1
475 1 1
476 1 1
MISSING_ELSE
481 1 1
482 1 1
483 1 1
485 1 1
486 1 1
487 1 1
489 1 1
495 1 1
496 1 1
497 1 1
MISSING_ELSE
503 1 1
504 1 1
505 1 1
==> MISSING_ELSE
510 1 1
511 1 1
512 1 1
514 1 1
518 1 1
519 1 1
520 1 1
MISSING_ELSE
529 1 1
530 1 1
531 1 1
532 0 1
534 1 1
541 1 1
542 1 1
543 1 1
547 1 1
548 1 1
549 1 1
550 1 1
567 1 1
570 1 1
MISSING_ELSE
605 1 1
611 3 3
668 1 1
669 1 1
670 1 1
671 1 1
673 1 1
674 1 1
675 1 1
683 1 1
684 1 1
685 1 1
686 1 1
687 1 1
688 1 1
689 1 1
MISSING_ELSE
691 1 1
692 1 1
693 1 1
MISSING_ELSE
MISSING_ELSE
700 1 1
701 1 1
MISSING_ELSE
709 1 1
710 1 1
732 1 1
736 1 1
737 1 1
749 1 1
756 1 1
757 1 1
758 1 1
759 1 1
760 1 1
761 1 1
762 1 1
763 1 1
764 1 1
765 1 1
766 1 1
767 1 1
768 1 1
769 1 1
770 1 1
772 1 1
779 1 1
780 1 1
781 1 1
782 1 1
783 1 1
MISSING_ELSE
788 1 1
789 0 1
790 1 1
791 1 1
793 1 1
794 1 1
795 1 1
800 1 1
801 1 1
802 1 1
803 1 1
804 1 1
MISSING_ELSE
809 1 1
810 1 1
814 1 1
815 1 1
816 1 1
817 1 1
819 1 1
820 1 1
821 1 1
826 1 1
827 1 1
828 1 1
830 1 1
831 1 1
MISSING_ELSE
836 1 1
837 1 1
839 1 1
840 1 1
841 1 1
842 1 1
MISSING_ELSE
847 1 1
848 1 1
849 1 1
851 1 1
852 1 1
853 1 1
854 1 1
MISSING_ELSE
857 1 1
858 1 1
MISSING_ELSE
863 1 1
867 1 1
868 1 1
869 1 1
886 1 1
887 1 1
888 1 1
889 unreachable
890 unreachable
891 1 1
892 1 1
893 1 1
895 1 1
897 1 1
900 1 1
901 1 1
903 1 1
904 1 1
906 1 1
909 1 1
913 1 1
916 1 1
927 unreachable
928 unreachable
==> MISSING_ELSE
934 1 1


Cond Coverage for Module : flash_ctrl_lcmgr
TotalCoveredPercent
Conditions969194.79
Logical969194.79
Non-Logical00
Event00

 LINE       170
 EXPRESSION (phase == PhaseSeed)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       171
 EXPRESSION (phase == PhaseRma)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T11,T154

 LINE       185
 EXPRESSION (seed_err_q | seed_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T164,T165
10Not Covered

 LINE       229
 EXPRESSION (addr_cnt_err_q | addr_cnt_err_d)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T13,T14
10CoveredT6,T13,T14

 LINE       230
 EXPRESSION (seed_cnt_err_q | seed_cnt_err_d)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T13,T14
10CoveredT6,T13,T14

 LINE       245
 EXPRESSION (data_invalid_q | (rvalid_i & ((~data_intg_ok))))
             -------1------   ---------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT166,T167,T168
10CoveredT166,T167,T168

 LINE       245
 SUB-EXPRESSION (rvalid_i & ((~data_intg_ok)))
                 ----1---   --------2--------
-1--2-StatusTests
01CoveredT166,T167,T168
10CoveredT1,T2,T3
11CoveredT166,T167,T168

 LINE       264
 EXPRESSION (seed_phase && validate_q && rvalid_i)
             -----1----    -----2----    ----3---
-1--2--3-StatusTests
011CoveredT169
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       268
 EXPRESSION (seed_phase && rvalid_i)
             -----1----    ----2---
-1--2-StatusTests
01CoveredT6,T59,T155
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       361
 EXPRESSION (addr_key_req_d && addr_key_ack_q)
             -------1------    -------2------
-1--2-StatusTests
01CoveredT95,T96,T97
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       366
 EXPRESSION (data_key_req_d && data_key_ack_q)
             -------1------    -------2------
-1--2-StatusTests
01CoveredT2,T93,T94
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       455
 EXPRESSION (provision_en_i ? StReadSeeds : StWait)
             -------1------
-1-StatusTests
0CoveredT170,T171,T172
1CoveredT1,T2,T3

 LINE       471
 EXPRESSION (seed_cnt_q == flash_ctrl_pkg::NumSeeds)
            --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       514
 EXPRESSION ((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)
             --------------------------1-------------------------    ------2------
-1--2-StatusTests
01CoveredT59,T152,T153
10CoveredT59,T152,T173
11CoveredT59,T152,T173

 LINE       514
 SUB-EXPRESSION (rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0])
                --------------------------1-------------------------
-1-StatusTests
0CoveredT2,T11,T154
1CoveredT59,T152,T173

 LINE       673
 EXPRESSION (page_err_q | page_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T13,T14
10CoveredT6,T13,T14

 LINE       674
 EXPRESSION (word_err_q | word_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T13,T14
10CoveredT6,T13,T14

 LINE       675
 EXPRESSION (rma_idx_err_q | rma_idx_err_d)
             ------1------   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T13,T14
10CoveredT6,T13,T14

 LINE       688
 EXPRESSION (wvalid_o && wready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT174,T175,T176
11CoveredT177,T59,T155

 LINE       692
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT59,T155,T152
10Unreachable
11CoveredT59,T155,T152

 LINE       700
 EXPRESSION (prog_cnt_en && wvalid_o && wready_i)
             -----1-----    ----2---    ----3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT174,T175,T176
111CoveredT177,T59,T155

 LINE       830
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)
             -----------------------1----------------------    ----2---
-1--2-StatusTests
01CoveredT177,T59,T155
10CoveredT176
11CoveredT177,T59,T155

 LINE       830
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------
-1-StatusTests
0CoveredT177,T59,T155
1CoveredT177,T59,T155

 LINE       851
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)
             -----------------------1----------------------    ---2--
-1--2-StatusTests
01Not Covered
10CoveredT59,T155,T152
11CoveredT59,T155,T152

 LINE       851
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------
-1-StatusTests
0CoveredT59,T155,T152
1CoveredT59,T155,T152

 LINE       857
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT59,T155,T152
10Unreachable
11CoveredT59,T155,T152

 LINE       858
 EXPRESSION (prog_data[beat_cnt] != rdata_i[(flash_ctrl_pkg::BusWidth - 1):0])
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT59,T155,T152
1CoveredT153,T178,T100

 LINE       887
 EXPRESSION (seed_phase ? start : rma_start)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       888
 EXPRESSION (seed_phase ? op : rma_op)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       891
 EXPRESSION (seed_phase ? part_sel : rma_part_sel)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       892
 EXPRESSION (seed_phase ? info_sel : rma_info_sel)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       893
 EXPRESSION (seed_phase ? num_words : rma_num_words)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       895
 EXPRESSION (seed_phase ? ({addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}) : ({rma_addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       901
 EXPRESSION (seed_phase | rma_phase)
             -----1----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T11,T154
10CoveredT1,T2,T3

 LINE       909
 EXPRESSION (page_err_q | word_err_q | fsm_err | state_err | rma_idx_err_q | addr_cnt_err_q | seed_cnt_err_q)
             -----1----   -----2----   ---3---   ----4----   ------5------   -------6------   -------7------
-1--2--3--4--5--6--7-StatusTests
0000000CoveredT1,T2,T3
0000001CoveredT6,T13,T14
0000010CoveredT6,T13,T14
0000100CoveredT6,T13,T14
0001000CoveredT6,T100,T13
0010000CoveredT6,T13,T14
0100000CoveredT6,T13,T14
1000000CoveredT6,T13,T14

FSM Coverage for Module : flash_ctrl_lcmgr
Summary for FSM :: state_q
TotalCoveredPercent
States 11 11 100.00 (Not included in score)
Transitions 25 23 92.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StDisabled 543 Covered T12
StEntropyReseed 497 Covered T12
StIdle 430 Covered T12
StInvalid 518 Covered T12
StReadEval 476 Covered T12
StReadSeeds 455 Covered T12
StReqAddrKey 434 Covered T12
StReqDataKey 444 Covered T12
StRmaRsp 518 Covered T12
StRmaWipe 432 Covered T12
StWait 455 Covered T12


transitionsLine No.CoveredTests
StEntropyReseed->StDisabled 570 Covered T12
StEntropyReseed->StRmaWipe 505 Covered T12
StIdle->StDisabled 570 Covered T12
StIdle->StReqAddrKey 434 Covered T12
StIdle->StRmaWipe 432 Covered T12
StInvalid->StDisabled 570 Not Covered
StReadEval->StDisabled 570 Covered T12
StReadEval->StReadSeeds 483 Covered T12
StReadSeeds->StDisabled 570 Covered T12
StReadSeeds->StReadEval 476 Covered T12
StReadSeeds->StWait 473 Covered T12
StReqAddrKey->StDisabled 570 Covered T12
StReqAddrKey->StReqDataKey 444 Covered T12
StReqAddrKey->StRmaWipe 442 Covered T12
StReqDataKey->StDisabled 570 Covered T12
StReqDataKey->StReadSeeds 455 Covered T12
StReqDataKey->StRmaWipe 452 Covered T12
StReqDataKey->StWait 455 Covered T12
StRmaRsp->StDisabled 570 Covered T12
StRmaRsp->StInvalid 532 Not Covered
StRmaWipe->StDisabled 570 Covered T12
StRmaWipe->StInvalid 518 Covered T12
StRmaWipe->StRmaRsp 518 Covered T12
StWait->StDisabled 570 Covered T12
StWait->StEntropyReseed 497 Covered T12


Summary for FSM :: rma_state_q
TotalCoveredPercent
States 10 10 100.00 (Not included in score)
Transitions 13 12 92.31
Sequences 0 0

State, Transition and Sequence Details for FSM :: rma_state_q
statesLine No.CoveredTests
StRmaDisabled 780 Covered T12
StRmaErase 791 Covered T12
StRmaEraseWait 804 Covered T12
StRmaIdle 795 Covered T12
StRmaInvalid 867 Covered T12
StRmaPageSel 782 Covered T12
StRmaProgram 817 Covered T12
StRmaProgramWait 831 Covered T12
StRmaRdVerify 842 Covered T12
StRmaWordSel 810 Covered T12


transitionsLine No.CoveredTests
StRmaErase->StRmaEraseWait 804 Covered T12
StRmaEraseWait->StRmaWordSel 810 Covered T12
StRmaIdle->StRmaDisabled 780 Covered T12
StRmaIdle->StRmaPageSel 782 Covered T12
StRmaPageSel->StRmaDisabled 789 Not Covered
StRmaPageSel->StRmaErase 791 Covered T12
StRmaPageSel->StRmaIdle 795 Covered T12
StRmaProgram->StRmaProgramWait 831 Covered T12
StRmaProgramWait->StRmaRdVerify 842 Covered T12
StRmaRdVerify->StRmaWordSel 854 Covered T12
StRmaWordSel->StRmaDisabled 815 Covered T12
StRmaWordSel->StRmaPageSel 821 Covered T12
StRmaWordSel->StRmaProgram 817 Covered T12



Branch Coverage for Module : flash_ctrl_lcmgr
Line No.TotalCoveredPercent
Branches 94 91 96.81
TERNARY 887 2 2 100.00
TERNARY 888 2 2 100.00
TERNARY 891 2 2 100.00
TERNARY 892 2 2 100.00
TERNARY 893 2 2 100.00
TERNARY 895 2 2 100.00
IF 152 2 2 100.00
IF 174 2 2 100.00
IF 225 2 2 100.00
IF 249 2 2 100.00
IF 262 4 4 100.00
IF 357 5 5 100.00
CASE 425 27 25 92.59
IF 567 2 2 100.00
IF 611 2 2 100.00
IF 668 2 2 100.00
IF 683 7 7 100.00
IF 700 2 2 100.00
CASE 772 23 22 95.65

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 887 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 888 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 891 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 892 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 893 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 895 (seed_phase) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 174 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 225 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 249 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 262 if ((!rst_ni)) -2-: 264 if (((seed_phase && validate_q) && rvalid_i)) -3-: 268 if ((seed_phase && rvalid_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 357 if ((!rst_ni)) -2-: 361 if ((addr_key_req_d && addr_key_ack_q)) -3-: 366 if ((data_key_req_d && data_key_ack_q))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 425 case (state_q) -2-: 431 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqInit])) -3-: 433 if (init_q) -4-: 441 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey])) -5-: 443 if (addr_key_ack_q) -6-: 451 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey])) -7-: 453 if (data_key_ack_q) -8-: 455 (provision_en_i) ? -9-: 471 if ((seed_cnt_q == flash_ctrl_pkg::NumSeeds)) -10-: 474 if (done_i) -11-: 485 if (validate_q) -12-: 496 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqWait])) -13-: 504 if (edn_ack_i) -14-: 514 if (((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)) -15-: 519 if (rma_wipe_done) -16-: 531 if (lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTests
StIdle 1 - - - - - - - - - - - - - - Covered T177,T155,T153
StIdle 0 1 - - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 0 - - - - - - - - - - - - - Covered T1,T2,T3
StReqAddrKey - - 1 - - - - - - - - - - - - Covered T96,T97,T179
StReqAddrKey - - 0 1 - - - - - - - - - - - Covered T1,T2,T3
StReqAddrKey - - 0 0 - - - - - - - - - - - Covered T1,T2,T3
StReqDataKey - - - - 1 - - - - - - - - - - Covered T2,T95,T180
StReqDataKey - - - - 0 1 1 - - - - - - - - Covered T1,T2,T3
StReqDataKey - - - - 0 1 0 - - - - - - - - Covered T170,T171,T172
StReqDataKey - - - - 0 0 - - - - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 1 - - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 0 1 - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 0 0 - - - - - - Covered T1,T2,T3
StReadEval - - - - - - - - - 1 - - - - - Covered T1,T2,T3
StReadEval - - - - - - - - - 0 - - - - - Covered T1,T2,T3
StWait - - - - - - - - - - 1 - - - - Covered T2,T11,T93
StWait - - - - - - - - - - 0 - - - - Covered T1,T2,T3
StEntropyReseed - - - - - - - - - - - 1 - - - Covered T2,T11,T93
StEntropyReseed - - - - - - - - - - - 0 - - - Not Covered
StRmaWipe - - - - - - - - - - - - 1 - - Covered T59,T152,T173
StRmaWipe - - - - - - - - - - - - 0 1 - Covered T59,T152,T153
StRmaWipe - - - - - - - - - - - - 0 0 - Covered T2,T11,T154
StRmaRsp - - - - - - - - - - - - - - 1 Not Covered
StRmaRsp - - - - - - - - - - - - - - 0 Covered T59,T152,T173
StDisabled - - - - - - - - - - - - - - - Covered T2,T6,T11
StInvalid - - - - - - - - - - - - - - - Covered T6,T100,T13
default - - - - - - - - - - - - - - - Covered T6,T13,T14


LineNo. Expression -1-: 567 if (((prim_mubi_pkg::mubi4_test_true_loose(disable_i) && (state_d != StInvalid)) && (!rma_done)))

Branches:
-1-StatusTests
1 Covered T2,T6,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 611 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 668 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 683 if ((!rst_ni)) -2-: 685 if (beat_cnt_clr) -3-: 687 if (prog_cnt_en) -4-: 688 if ((wvalid_o && wready_i)) -5-: 691 if (rd_cnt_en) -6-: 692 if ((rvalid_i && rready_o))

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Covered T59,T155,T152
0 0 1 1 - - Covered T177,T59,T155
0 0 1 0 - - Covered T174,T175,T176
0 0 0 - 1 1 Covered T59,T155,T152
0 0 0 - 1 0 Covered T59,T155,T152
0 0 0 - 0 - Covered T1,T2,T3


LineNo. Expression -1-: 700 if (((prog_cnt_en && wvalid_o) && wready_i))

Branches:
-1-StatusTests
1 Covered T177,T59,T155
0 Covered T1,T2,T3


LineNo. Expression -1-: 772 case (rma_state_q) -2-: 779 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) -3-: 781 if (rma_wipe_req_int) -4-: 788 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) -5-: 790 if ((page_cnt < end_page)) -6-: 802 if (done_i) -7-: 814 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) -8-: 816 if ((word_cnt < flash_ctrl_pkg::BusWordsPerPage)) -9-: 830 if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)) -10-: 839 if (done_i) -11-: 851 if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)) -12-: 857 if ((rvalid_i && rready_o))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12-StatusTests
StRmaIdle 1 - - - - - - - - - - Covered T6,T11,T93
StRmaIdle 0 1 - - - - - - - - - Covered T2,T11,T154
StRmaIdle 0 0 - - - - - - - - - Covered T1,T2,T3
StRmaPageSel - - 1 - - - - - - - - Not Covered
StRmaPageSel - - 0 1 - - - - - - - Covered T2,T11,T154
StRmaPageSel - - 0 0 - - - - - - - Covered T59,T152,T153
StRmaErase - - - - 1 - - - - - - Covered T2,T11,T154
StRmaErase - - - - 0 - - - - - - Covered T2,T11,T154
StRmaEraseWait - - - - - - - - - - - Covered T2,T11,T154
StRmaWordSel - - - - - 1 - - - - - Covered T2,T11,T154
StRmaWordSel - - - - - 0 1 - - - - Covered T177,T59,T155
StRmaWordSel - - - - - 0 0 - - - - Covered T59,T152,T153
StRmaProgram - - - - - - - 1 - - - Covered T177,T59,T155
StRmaProgram - - - - - - - 0 - - - Covered T177,T59,T155
StRmaProgramWait - - - - - - - - 1 - - Covered T59,T155,T152
StRmaProgramWait - - - - - - - - 0 - - Covered T177,T59,T155
StRmaRdVerify - - - - - - - - - 1 - Covered T59,T155,T152
StRmaRdVerify - - - - - - - - - 0 - Covered T59,T155,T152
StRmaRdVerify - - - - - - - - - - 1 Covered T59,T155,T152
StRmaRdVerify - - - - - - - - - - 0 Covered T59,T155,T152
StRmaDisabled - - - - - - - - - - - Covered T2,T6,T11
StRmaInvalid - - - - - - - - - - - Covered T6,T13,T14
default - - - - - - - - - - - Covered T6,T13,T14


Assert Coverage for Module : flash_ctrl_lcmgr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DisableChk_A 314969025 7116221 0 35
ProgRdVerify_A 313177891 1845787 0 0
u_rma_state_regs_A 327083629 326368786 0 0
u_state_regs_A 327083629 326368786 0 0


DisableChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 314969025 7116221 0 35
T2 3842 10 0 0
T3 163740 0 0 0
T4 317018 0 0 0
T5 175018 0 0 0
T6 112145 44185 0 0
T11 4051 11 0 0
T15 4471 0 0 0
T16 996 0 0 0
T17 45527 0 0 0
T19 4161 0 0 0
T24 0 223 0 1
T25 0 0 0 1
T36 0 0 0 1
T38 0 0 0 1
T93 0 12 0 0
T98 0 0 0 1
T99 0 0 0 1
T101 0 0 0 1
T154 0 10 0 0
T166 0 3 0 0
T167 0 3 0 0
T168 0 3 0 0
T177 0 89708 0 0
T181 0 0 0 1
T182 0 0 0 1
T183 0 0 0 1

ProgRdVerify_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 313177891 1845787 0 0
T9 4147 0 0 0
T59 385845 65920 0 0
T94 3957 0 0 0
T102 0 65920 0 0
T116 2220 0 0 0
T117 2099 0 0 0
T118 2270 0 0 0
T152 0 65920 0 0
T155 0 4 0 0
T173 0 65920 0 0
T174 0 65920 0 0
T184 0 4 0 0
T185 0 1 0 0
T186 0 65920 0 0
T187 0 65920 0 0
T188 1524 0 0 0
T189 15658 0 0 0
T190 1282 0 0 0
T191 240403 0 0 0

u_rma_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083629 326368786 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 327083629 326368786 0 0
T1 9195 9038 0 0
T2 3842 3192 0 0
T3 163740 163662 0 0
T4 317018 316947 0 0
T5 175018 174954 0 0
T6 131369 106175 0 0
T11 4051 3349 0 0
T15 4471 4376 0 0
T16 996 912 0 0
T17 45527 45356 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%