SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.58 | 99.17 | 94.79 | 92.11 | 96.81 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
72.41 | 88.24 | 83.33 | 57.14 | 83.33 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
72.29 | 86.27 | 88.89 | 57.14 | 79.17 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.26 | 97.67 | 85.11 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 8760 | 8760 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 18342 |
gen_no_flops.OutputDelay_A | 645748648 | 644318962 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 8760 | 8760 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T5 | 10 | 10 | 0 | 0 |
T6 | 10 | 10 | 0 | 0 |
T11 | 10 | 10 | 0 | 0 |
T15 | 10 | 10 | 0 | 0 |
T16 | 10 | 10 | 0 | 0 |
T17 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 91950 | 90380 | 0 | 0 |
T2 | 38420 | 31920 | 0 | 0 |
T3 | 1637400 | 1636620 | 0 | 0 |
T4 | 3170180 | 3169470 | 0 | 0 |
T5 | 3690 | 3050 | 0 | 0 |
T6 | 1313690 | 1061750 | 0 | 0 |
T11 | 40510 | 33490 | 0 | 0 |
T15 | 44710 | 43760 | 0 | 0 |
T16 | 3880 | 3040 | 0 | 0 |
T17 | 455270 | 453560 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 18342 |
T1 | 73560 | 72256 | 0 | 24 |
T2 | 30736 | 25320 | 0 | 24 |
T3 | 1309920 | 1309272 | 0 | 24 |
T4 | 2536144 | 2535552 | 0 | 24 |
T5 | 2952 | 2440 | 0 | 0 |
T6 | 1050952 | 841216 | 0 | 24 |
T11 | 32408 | 26576 | 0 | 24 |
T15 | 35768 | 34984 | 0 | 24 |
T16 | 3104 | 2432 | 0 | 0 |
T17 | 364216 | 362800 | 0 | 24 |
T19 | 0 | 0 | 0 | 24 |
T46 | 0 | 0 | 0 | 24 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 645748648 | 644318962 | 0 | 0 |
T1 | 18390 | 18076 | 0 | 0 |
T2 | 7684 | 6384 | 0 | 0 |
T3 | 327480 | 327324 | 0 | 0 |
T4 | 634036 | 633894 | 0 | 0 |
T5 | 738 | 610 | 0 | 0 |
T6 | 262738 | 212350 | 0 | 0 |
T11 | 8102 | 6698 | 0 | 0 |
T15 | 8942 | 8752 | 0 | 0 |
T16 | 776 | 608 | 0 | 0 |
T17 | 91054 | 90712 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 876 | 876 | 0 | 0 |
OutputsKnown_A | 322874385 | 322159542 | 0 | 0 |
gen_flops.OutputDelay_A | 322874385 | 322131345 | 0 | 2307 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 876 | 876 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322159542 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322131345 | 0 | 2307 |
T1 | 9195 | 9032 | 0 | 3 |
T2 | 3842 | 3165 | 0 | 3 |
T3 | 163740 | 163659 | 0 | 3 |
T4 | 317018 | 316944 | 0 | 3 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 105152 | 0 | 3 |
T11 | 4051 | 3322 | 0 | 3 |
T15 | 4471 | 4373 | 0 | 3 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45350 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T46 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 876 | 876 | 0 | 0 |
OutputsKnown_A | 322874385 | 322159542 | 0 | 0 |
gen_flops.OutputDelay_A | 322874385 | 322131345 | 0 | 2307 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 876 | 876 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322159542 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322131345 | 0 | 2307 |
T1 | 9195 | 9032 | 0 | 3 |
T2 | 3842 | 3165 | 0 | 3 |
T3 | 163740 | 163659 | 0 | 3 |
T4 | 317018 | 316944 | 0 | 3 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 105152 | 0 | 3 |
T11 | 4051 | 3322 | 0 | 3 |
T15 | 4471 | 4373 | 0 | 3 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45350 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T46 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 876 | 876 | 0 | 0 |
OutputsKnown_A | 322874385 | 322159542 | 0 | 0 |
gen_flops.OutputDelay_A | 322874385 | 322131345 | 0 | 2307 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 876 | 876 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322159542 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322131345 | 0 | 2307 |
T1 | 9195 | 9032 | 0 | 3 |
T2 | 3842 | 3165 | 0 | 3 |
T3 | 163740 | 163659 | 0 | 3 |
T4 | 317018 | 316944 | 0 | 3 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 105152 | 0 | 3 |
T11 | 4051 | 3322 | 0 | 3 |
T15 | 4471 | 4373 | 0 | 3 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45350 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T46 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 876 | 876 | 0 | 0 |
OutputsKnown_A | 322874385 | 322159542 | 0 | 0 |
gen_flops.OutputDelay_A | 322874385 | 322131345 | 0 | 2307 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 876 | 876 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322159542 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322131345 | 0 | 2307 |
T1 | 9195 | 9032 | 0 | 3 |
T2 | 3842 | 3165 | 0 | 3 |
T3 | 163740 | 163659 | 0 | 3 |
T4 | 317018 | 316944 | 0 | 3 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 105152 | 0 | 3 |
T11 | 4051 | 3322 | 0 | 3 |
T15 | 4471 | 4373 | 0 | 3 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45350 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T46 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 876 | 876 | 0 | 0 |
OutputsKnown_A | 322874385 | 322159542 | 0 | 0 |
gen_flops.OutputDelay_A | 322874385 | 322131345 | 0 | 2307 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 876 | 876 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322159542 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322131345 | 0 | 2307 |
T1 | 9195 | 9032 | 0 | 3 |
T2 | 3842 | 3165 | 0 | 3 |
T3 | 163740 | 163659 | 0 | 3 |
T4 | 317018 | 316944 | 0 | 3 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 105152 | 0 | 3 |
T11 | 4051 | 3322 | 0 | 3 |
T15 | 4471 | 4373 | 0 | 3 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45350 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T46 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 876 | 876 | 0 | 0 |
OutputsKnown_A | 322874385 | 322159542 | 0 | 0 |
gen_flops.OutputDelay_A | 322874385 | 322131345 | 0 | 2307 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 876 | 876 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322159542 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874385 | 322131345 | 0 | 2307 |
T1 | 9195 | 9032 | 0 | 3 |
T2 | 3842 | 3165 | 0 | 3 |
T3 | 163740 | 163659 | 0 | 3 |
T4 | 317018 | 316944 | 0 | 3 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 105152 | 0 | 3 |
T11 | 4051 | 3322 | 0 | 3 |
T15 | 4471 | 4373 | 0 | 3 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45350 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T46 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 876 | 876 | 0 | 0 |
OutputsKnown_A | 322874324 | 322159481 | 0 | 0 |
gen_no_flops.OutputDelay_A | 322874324 | 322159481 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 876 | 876 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874324 | 322159481 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874324 | 322159481 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 876 | 876 | 0 | 0 |
OutputsKnown_A | 322857301 | 322142458 | 0 | 0 |
gen_flops.OutputDelay_A | 322857301 | 322114375 | 0 | 2193 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 876 | 876 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322857301 | 322142458 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322857301 | 322114375 | 0 | 2193 |
T1 | 9195 | 9032 | 0 | 3 |
T2 | 3842 | 3165 | 0 | 3 |
T3 | 163740 | 163659 | 0 | 3 |
T4 | 317018 | 316944 | 0 | 3 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 105152 | 0 | 3 |
T11 | 4051 | 3322 | 0 | 3 |
T15 | 4471 | 4373 | 0 | 3 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45350 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T46 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 876 | 876 | 0 | 0 |
OutputsKnown_A | 322874324 | 322159481 | 0 | 0 |
gen_no_flops.OutputDelay_A | 322874324 | 322159481 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 876 | 876 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874324 | 322159481 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874324 | 322159481 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 876 | 876 | 0 | 0 |
OutputsKnown_A | 322874324 | 322159481 | 0 | 0 |
gen_flops.OutputDelay_A | 322874324 | 322131290 | 0 | 2307 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 876 | 876 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874324 | 322159481 | 0 | 0 |
T1 | 9195 | 9038 | 0 | 0 |
T2 | 3842 | 3192 | 0 | 0 |
T3 | 163740 | 163662 | 0 | 0 |
T4 | 317018 | 316947 | 0 | 0 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 106175 | 0 | 0 |
T11 | 4051 | 3349 | 0 | 0 |
T15 | 4471 | 4376 | 0 | 0 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45356 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 322874324 | 322131290 | 0 | 2307 |
T1 | 9195 | 9032 | 0 | 3 |
T2 | 3842 | 3165 | 0 | 3 |
T3 | 163740 | 163659 | 0 | 3 |
T4 | 317018 | 316944 | 0 | 3 |
T5 | 369 | 305 | 0 | 0 |
T6 | 131369 | 105152 | 0 | 3 |
T11 | 4051 | 3322 | 0 | 3 |
T15 | 4471 | 4373 | 0 | 3 |
T16 | 388 | 304 | 0 | 0 |
T17 | 45527 | 45350 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T46 | 0 | 0 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |