Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20214715	1		T12	1236		T45	83		T46	82
full_word	6760825	1		T12	306		T45	59		T46	60

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	26975230	1		T12	1542		T45	142		T46	142
auto[TlIntgErrCmd]	106	1		T48	2		T52	4		T243	3
auto[TlIntgErrData]	109	1		T48	3		T52	2		T243	3
auto[TlIntgErrBoth]	95	1		T48	5		T52	4		T243	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	23122333	1		T12	340		T45	77		T46	77
auto[1]	3853207	1		T12	1202		T45	65		T46	65

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19624741	1		T12	271		T45	66		T46	65
auto[TlIntgErrNone]	partial	auto[1]	589693	1		T12	965		T45	17		T46	17
auto[TlIntgErrNone]	full_word	auto[0]	3497458	1		T12	69		T45	11		T46	12
auto[TlIntgErrNone]	full_word	auto[1]	3263338	1		T12	237		T45	48		T46	48
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T48	2		T52	1		T243	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T52	2		T244	3		T245	7
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T246	1		T339	1		T337	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T52	1		T243	1		T244	1
auto[TlIntgErrData]	partial	auto[0]	48	1		T48	3		T243	3		T244	1
auto[TlIntgErrData]	partial	auto[1]	48	1		T52	1		T244	2		T245	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T244	1		T245	1		T342	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T52	1		T244	2		T339	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T48	2		T52	1		T243	4
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T48	3		T52	2		T244	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T52	1		T343	1		T339	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T343	1		T339	1		T274	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23665	1		T12	914		T50	45		T53	531
full_word	4036094	1		T12	366		T50	17		T53	145

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4059472	1		T12	1280		T50	62		T53	676
auto[TlIntgErrCmd]	92	1		T48	3		T52	7		T243	2
auto[TlIntgErrData]	111	1		T48	5		T243	3		T244	10
auto[TlIntgErrBoth]	84	1		T48	2		T52	2		T243	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4030006	1		T12	53		T50	3		T53	56
auto[1]	29753	1		T12	1227		T50	59		T53	620

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1441	1		T12	47		T50	2		T53	51
auto[TlIntgErrNone]	partial	auto[1]	21961	1		T12	867		T50	43		T53	480
auto[TlIntgErrNone]	full_word	auto[0]	4028461	1		T12	6		T50	1		T53	5
auto[TlIntgErrNone]	full_word	auto[1]	7609	1		T12	360		T50	16		T53	140
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T52	1		T243	2		T244	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T48	1		T52	6		T244	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T338	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T48	2		T245	1		T336	1
auto[TlIntgErrData]	partial	auto[0]	44	1		T48	3		T243	2		T244	7
auto[TlIntgErrData]	partial	auto[1]	57	1		T48	2		T243	1		T244	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T244	1		T271	1		T338	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T245	1		T272	1		T246	1
auto[TlIntgErrBoth]	partial	auto[0]	19	1		T243	1		T245	4		T273	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T48	2		T52	2		T243	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T344	1		T274	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T273	1		T343	1		T339	1