Unified Coverage Report :: Module :: flash_ctrl_prim_reg_top

Module : flash_ctrl_prim_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.94	99.31	95.83	100.00		99.56	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	80.00						gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_chk	100.00	100.00		100.00			100.00
u_csr0_regwen	100.00	100.00	100.00			100.00
u_csr10	100.00	100.00	100.00			100.00
u_csr11	100.00	100.00	100.00			100.00
u_csr12	100.00	100.00	100.00			100.00
u_csr13_field0	100.00	100.00	100.00			100.00
u_csr13_field1	100.00	100.00	100.00			100.00
u_csr14_field0	100.00	100.00	100.00			100.00
u_csr14_field1	100.00	100.00	100.00			100.00
u_csr15_field0	100.00	100.00	100.00			100.00
u_csr15_field1	100.00	100.00	100.00			100.00
u_csr16_field0	100.00	100.00	100.00			100.00
u_csr16_field1	100.00	100.00	100.00			100.00
u_csr17_field0	100.00	100.00	100.00			100.00
u_csr17_field1	100.00	100.00	100.00			100.00
u_csr18	100.00	100.00	100.00			100.00
u_csr19	100.00	100.00	100.00			100.00
u_csr1_field0	100.00	100.00	100.00			100.00
u_csr1_field1	100.00	100.00	100.00			100.00
u_csr20_field0	88.89	100.00	66.67			100.00
u_csr20_field1	88.89	100.00	66.67			100.00
u_csr20_field2	55.19	55.56	50.00			60.00
u_csr2_field0	88.89	100.00	66.67			100.00
u_csr2_field1	88.89	100.00	66.67			100.00
u_csr2_field2	88.89	100.00	66.67			100.00
u_csr2_field3	96.30	100.00	88.89			100.00
u_csr2_field4	88.89	100.00	66.67			100.00
u_csr2_field5	88.89	100.00	66.67			100.00
u_csr2_field6	88.89	100.00	66.67			100.00
u_csr2_field7	96.30	100.00	88.89			100.00
u_csr3_field0	100.00	100.00	100.00			100.00
u_csr3_field1	100.00	100.00	100.00			100.00
u_csr3_field2	100.00	100.00	100.00			100.00
u_csr3_field3	100.00	100.00	100.00			100.00
u_csr3_field4	100.00	100.00	100.00			100.00
u_csr3_field5	100.00	100.00	100.00			100.00
u_csr3_field6	100.00	100.00	100.00			100.00
u_csr3_field7	100.00	100.00	100.00			100.00
u_csr3_field8	100.00	100.00	100.00			100.00
u_csr3_field9	100.00	100.00	100.00			100.00
u_csr4_field0	100.00	100.00	100.00			100.00
u_csr4_field1	100.00	100.00	100.00			100.00
u_csr4_field2	100.00	100.00	100.00			100.00
u_csr4_field3	100.00	100.00	100.00			100.00
u_csr5_field0	100.00	100.00	100.00			100.00
u_csr5_field1	100.00	100.00	100.00			100.00
u_csr5_field2	100.00	100.00	100.00			100.00
u_csr5_field3	100.00	100.00	100.00			100.00
u_csr5_field4	100.00	100.00	100.00			100.00
u_csr6_field0	100.00	100.00	100.00			100.00
u_csr6_field1	100.00	100.00	100.00			100.00
u_csr6_field2	100.00	100.00	100.00			100.00
u_csr6_field3	100.00	100.00	100.00			100.00
u_csr6_field4	100.00	100.00	100.00			100.00
u_csr6_field5	100.00	100.00	100.00			100.00
u_csr6_field6	100.00	100.00	100.00			100.00
u_csr6_field7	100.00	100.00	100.00			100.00
u_csr6_field8	100.00	100.00	100.00			100.00
u_csr7_field0	100.00	100.00	100.00			100.00
u_csr7_field1	100.00	100.00	100.00			100.00
u_csr8	100.00	100.00	100.00			100.00
u_csr9	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_prim_reg_top

	Line No.	Total	Covered	Percent
TOTAL		219	219	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	967	1	1	100.00
CONT_ASSIGN	1107	1	1	100.00
CONT_ASSIGN	1355	1	1	100.00
CONT_ASSIGN	1414	1	1	100.00
CONT_ASSIGN	1445	1	1	100.00
CONT_ASSIGN	1476	1	1	100.00
CONT_ASSIGN	1507	1	1	100.00
CONT_ASSIGN	1538	1	1	100.00
CONT_ASSIGN	1569	1	1	100.00
CONT_ASSIGN	1628	1	1	100.00
CONT_ASSIGN	1687	1	1	100.00
CONT_ASSIGN	1746	1	1	100.00
CONT_ASSIGN	1805	1	1	100.00
CONT_ASSIGN	1864	1	1	100.00
CONT_ASSIGN	1895	1	1	100.00
ALWAYS	2009	22	22	100.00
CONT_ASSIGN	2033	1	1	100.00
ALWAYS	2037	1	1	100.00
CONT_ASSIGN	2062	1	1	100.00
CONT_ASSIGN	2064	1	1	100.00
CONT_ASSIGN	2065	1	1	100.00
CONT_ASSIGN	2067	1	1	100.00
CONT_ASSIGN	2069	1	1	100.00
CONT_ASSIGN	2070	1	1	100.00
CONT_ASSIGN	2072	1	1	100.00
CONT_ASSIGN	2074	1	1	100.00
CONT_ASSIGN	2076	1	1	100.00
CONT_ASSIGN	2078	1	1	100.00
CONT_ASSIGN	2080	1	1	100.00
CONT_ASSIGN	2082	1	1	100.00
CONT_ASSIGN	2084	1	1	100.00
CONT_ASSIGN	2086	1	1	100.00
CONT_ASSIGN	2087	1	1	100.00
CONT_ASSIGN	2089	1	1	100.00
CONT_ASSIGN	2091	1	1	100.00
CONT_ASSIGN	2093	1	1	100.00
CONT_ASSIGN	2095	1	1	100.00
CONT_ASSIGN	2097	1	1	100.00
CONT_ASSIGN	2099	1	1	100.00
CONT_ASSIGN	2101	1	1	100.00
CONT_ASSIGN	2103	1	1	100.00
CONT_ASSIGN	2105	1	1	100.00
CONT_ASSIGN	2107	1	1	100.00
CONT_ASSIGN	2108	1	1	100.00
CONT_ASSIGN	2110	1	1	100.00
CONT_ASSIGN	2112	1	1	100.00
CONT_ASSIGN	2114	1	1	100.00
CONT_ASSIGN	2116	1	1	100.00
CONT_ASSIGN	2117	1	1	100.00
CONT_ASSIGN	2119	1	1	100.00
CONT_ASSIGN	2121	1	1	100.00
CONT_ASSIGN	2123	1	1	100.00
CONT_ASSIGN	2125	1	1	100.00
CONT_ASSIGN	2127	1	1	100.00
CONT_ASSIGN	2128	1	1	100.00
CONT_ASSIGN	2130	1	1	100.00
CONT_ASSIGN	2132	1	1	100.00
CONT_ASSIGN	2134	1	1	100.00
CONT_ASSIGN	2136	1	1	100.00
CONT_ASSIGN	2138	1	1	100.00
CONT_ASSIGN	2140	1	1	100.00
CONT_ASSIGN	2142	1	1	100.00
CONT_ASSIGN	2144	1	1	100.00
CONT_ASSIGN	2146	1	1	100.00
CONT_ASSIGN	2147	1	1	100.00
CONT_ASSIGN	2149	1	1	100.00
CONT_ASSIGN	2151	1	1	100.00
CONT_ASSIGN	2152	1	1	100.00
CONT_ASSIGN	2154	1	1	100.00
CONT_ASSIGN	2155	1	1	100.00
CONT_ASSIGN	2157	1	1	100.00
CONT_ASSIGN	2158	1	1	100.00
CONT_ASSIGN	2160	1	1	100.00
CONT_ASSIGN	2161	1	1	100.00
CONT_ASSIGN	2163	1	1	100.00
CONT_ASSIGN	2164	1	1	100.00
CONT_ASSIGN	2166	1	1	100.00
CONT_ASSIGN	2167	1	1	100.00
CONT_ASSIGN	2169	1	1	100.00
CONT_ASSIGN	2171	1	1	100.00
CONT_ASSIGN	2172	1	1	100.00
CONT_ASSIGN	2174	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2177	1	1	100.00
CONT_ASSIGN	2179	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2182	1	1	100.00
CONT_ASSIGN	2184	1	1	100.00
CONT_ASSIGN	2186	1	1	100.00
CONT_ASSIGN	2187	1	1	100.00
CONT_ASSIGN	2189	1	1	100.00
CONT_ASSIGN	2191	1	1	100.00
CONT_ASSIGN	2192	1	1	100.00
CONT_ASSIGN	2194	1	1	100.00
CONT_ASSIGN	2195	1	1	100.00
CONT_ASSIGN	2197	1	1	100.00
CONT_ASSIGN	2198	1	1	100.00
CONT_ASSIGN	2200	1	1	100.00
CONT_ASSIGN	2202	1	1	100.00
ALWAYS	2206	22	22	100.00
ALWAYS	2232	63	63	100.00
CONT_ASSIGN	2369	0	0
CONT_ASSIGN	2377	1	1	100.00
CONT_ASSIGN	2378	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
302	1	1
579	1	1
854	1	1
967	1	1
1107	1	1
1355	1	1
1414	1	1
1445	1	1
1476	1	1
1507	1	1
1538	1	1
1569	1	1
1628	1	1
1687	1	1
1746	1	1
1805	1	1
1864	1	1
1895	1	1
2009	1	1
2010	1	1
2011	1	1
2012	1	1
2013	1	1
2014	1	1
2015	1	1
2016	1	1
2017	1	1
2018	1	1
2019	1	1
2020	1	1
2021	1	1
2022	1	1
2023	1	1
2024	1	1
2025	1	1
2026	1	1
2027	1	1
2028	1	1
2029	1	1
2030	1	1
2033	1	1
2037	1	1
2062	1	1
2064	1	1
2065	1	1
2067	1	1
2069	1	1
2070	1	1
2072	1	1
2074	1	1
2076	1	1
2078	1	1
2080	1	1
2082	1	1
2084	1	1
2086	1	1
2087	1	1
2089	1	1
2091	1	1
2093	1	1
2095	1	1
2097	1	1
2099	1	1
2101	1	1
2103	1	1
2105	1	1
2107	1	1
2108	1	1
2110	1	1
2112	1	1
2114	1	1
2116	1	1
2117	1	1
2119	1	1
2121	1	1
2123	1	1
2125	1	1
2127	1	1
2128	1	1
2130	1	1
2132	1	1
2134	1	1
2136	1	1
2138	1	1
2140	1	1
2142	1	1
2144	1	1
2146	1	1
2147	1	1
2149	1	1
2151	1	1
2152	1	1
2154	1	1
2155	1	1
2157	1	1
2158	1	1
2160	1	1
2161	1	1
2163	1	1
2164	1	1
2166	1	1
2167	1	1
2169	1	1
2171	1	1
2172	1	1
2174	1	1
2176	1	1
2177	1	1
2179	1	1
2181	1	1
2182	1	1
2184	1	1
2186	1	1
2187	1	1
2189	1	1
2191	1	1
2192	1	1
2194	1	1
2195	1	1
2197	1	1
2198	1	1
2200	1	1
2202	1	1
2206	1	1
2207	1	1
2208	1	1
2209	1	1
2210	1	1
2211	1	1
2212	1	1
2213	1	1
2214	1	1
2215	1	1
2216	1	1
2217	1	1
2218	1	1
2219	1	1
2220	1	1
2221	1	1
2222	1	1
2223	1	1
2224	1	1
2225	1	1
2226	1	1
2227	1	1
2232	1	1
2233	1	1
2235	1	1
2239	1	1
2240	1	1
2244	1	1
2245	1	1
2246	1	1
2247	1	1
2248	1	1
2249	1	1
2250	1	1
2251	1	1
2255	1	1
2256	1	1
2257	1	1
2258	1	1
2259	1	1
2260	1	1
2261	1	1
2262	1	1
2263	1	1
2264	1	1
2268	1	1
2269	1	1
2270	1	1
2271	1	1
2275	1	1
2276	1	1
2277	1	1
2278	1	1
2279	1	1
2283	1	1
2284	1	1
2285	1	1
2286	1	1
2287	1	1
2288	1	1
2289	1	1
2290	1	1
2291	1	1
2295	1	1
2296	1	1
2300	1	1
2304	1	1
2308	1	1
2312	1	1
2316	1	1
2320	1	1
2321	1	1
2325	1	1
2326	1	1
2330	1	1
2331	1	1
2335	1	1
2336	1	1
2340	1	1
2341	1	1
2345	1	1
2349	1	1
2353	1	1
2354	1	1
2355	1	1
2369		unreachable
2377	1	1
2378	1	1

---

Cond Coverage for Module : flash_ctrl_prim_reg_top

	Total	Covered	Percent
Conditions	289	289	100.00
Logical	289	289	100.00
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T12,T53,T48
1	1	Covered	T12,T47,T50

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T12,T45,T46
0	1	Covered	T13,T14,T23
1	0	Covered	T48,T52,T243

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T12,T45,T46
0	0	1	Covered	T13,T14,T23
0	1	0	Covered	T48,T52,T243
1	0	0	Covered	T48,T52,T243

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T12,T45,T46
0	0	1	Covered	T48,T52,T243
0	1	0	Covered	T12,T53,T51
1	0	0	Covered	T12,T50,T53

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T12,T45,T46
1	1	Covered	T12,T50,T53

 LINE       302
 EXPRESSION (csr1_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T49
1	1	Covered	T47,T50,T51

 LINE       579
 EXPRESSION (csr3_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T49
1	1	Covered	T47,T51,T48

 LINE       854
 EXPRESSION (csr4_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T52,T243
1	1	Covered	T47,T51,T48

 LINE       967
 EXPRESSION (csr5_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T49
1	1	Covered	T51,T48,T123

 LINE       1107
 EXPRESSION (csr6_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T49
1	1	Covered	T47,T50,T51

 LINE       1355
 EXPRESSION (csr7_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T49,T52
1	1	Covered	T47,T51,T48

 LINE       1414
 EXPRESSION (csr8_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T52
1	1	Covered	T47,T50,T51

 LINE       1445
 EXPRESSION (csr9_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T49
1	1	Covered	T51,T48,T52

 LINE       1476
 EXPRESSION (csr10_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T49
1	1	Covered	T47,T51,T48

 LINE       1507
 EXPRESSION (csr11_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T52
1	1	Covered	T47,T51,T48

 LINE       1538
 EXPRESSION (csr12_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T49,T52
1	1	Covered	T47,T50,T51

 LINE       1569
 EXPRESSION (csr13_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T52
1	1	Covered	T47,T50,T51

 LINE       1628
 EXPRESSION (csr14_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T49,T52
1	1	Covered	T47,T50,T51

 LINE       1687
 EXPRESSION (csr15_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T49,T52
1	1	Covered	T47,T50,T51

 LINE       1746
 EXPRESSION (csr16_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T52
1	1	Covered	T47,T51,T48

 LINE       1805
 EXPRESSION (csr17_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T49
1	1	Covered	T47,T50,T51

 LINE       1864
 EXPRESSION (csr18_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T49
1	1	Covered	T47,T50,T51

 LINE       1895
 EXPRESSION (csr19_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T45,T46
1	0	Covered	T47,T48,T52
1	1	Covered	T47,T51,T48

 LINE       2010
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR0_REGWEN_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2011
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR1_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2012
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR2_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2013
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR3_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2014
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR4_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T12,T47,T50
1	Covered	T12,T46,T47

 LINE       2015
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR5_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2016
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR6_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2017
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR7_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2018
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR8_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2019
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR9_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2020
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR10_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2021
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR11_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2022
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR12_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2023
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR13_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2024
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR14_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2025
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR15_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2026
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR16_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2027
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR17_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2028
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR18_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2029
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR19_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2030
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR20_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T12,T46,T47
1	Covered	T12,T47,T50

 LINE       2033
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T12,T45,T46
1	Covered	T12,T47,T50

 LINE       2033
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T12,T45,T46
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50

 LINE       2037
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T53,T51

 LINE       2037
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T12,T46,T47
21 (addr_hit[20] & ((|(4'...	Covered	T12,T47,T50
20 (addr_hit[19] & ((|(4'...	Covered	T12,T47,T53
19 (addr_hit[18] & ((|(4'...	Covered	T12,T47,T50
18 (addr_hit[17] & ((|(4'...	Covered	T12,T47,T50
17 (addr_hit[16] & ((|(4'...	Covered	T12,T47,T50
16 (addr_hit[15] & ((|(4'...	Covered	T12,T47,T50
15 (addr_hit[14] & ((|(4'...	Covered	T12,T47,T53
14 (addr_hit[13] & ((|(4'...	Covered	T12,T47,T50
13 (addr_hit[12] & ((|(4'...	Covered	T12,T47,T50
12 (addr_hit[11] & ((|(4'...	Covered	T12,T47,T50
11 (addr_hit[10] & ((|(4'...	Covered	T12,T47,T50
10 (addr_hit[9] & ((|(4'b...	Covered	T12,T47,T50
9 (addr_hit[8] & ((|(4'b...	Covered	T12,T47,T50
8 (addr_hit[7] & ((|(4'b...	Covered	T12,T47,T50
7 (addr_hit[6] & ((|(4'b...	Covered	T12,T47,T50
6 (addr_hit[5] & ((|(4'b...	Covered	T12,T47,T53
5 (addr_hit[4] & ((|(4'b...	Covered	T12,T47,T50
4 (addr_hit[3] & ((|(4'b...	Covered	T12,T47,T50
3 (addr_hit[2] & ((|(4'b...	Covered	T12,T47,T50
2 (addr_hit[1] & ((|(4'b...	Covered	T12,T47,T50
1 (addr_hit[0] & ((|(4'b...	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T46,T47
1	0	Covered	T12,T47,T53
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T46,T47
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T53

 LINE       2037
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T46,T47
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T46,T47
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T46,T47
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T46,T47
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T46,T47
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T53

 LINE       2037
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T53
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2037
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T53

 LINE       2037
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T47,T50
1	0	Covered	T12,T47,T50
1	1	Covered	T12,T47,T50

 LINE       2062
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T53,T123,T127
1	1	1	Covered	T47,T51,T48

 LINE       2065
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T123
1	1	1	Covered	T47,T50,T51

 LINE       2070
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T51
1	1	1	Covered	T47,T51,T48

 LINE       2087
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T51
1	1	1	Covered	T47,T51,T48

 LINE       2108
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T46,T47
1	1	0	Covered	T12,T53,T123
1	1	1	Covered	T47,T51,T48

 LINE       2117
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T53,T123,T124
1	1	1	Covered	T47,T51,T48

 LINE       2128
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T243
1	1	1	Covered	T47,T50,T51

 LINE       2147
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T244
1	1	1	Covered	T47,T51,T48

 LINE       2152
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T51
1	1	1	Covered	T47,T50,T51

 LINE       2155
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T124
1	1	1	Covered	T47,T51,T48

 LINE       2158
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T51
1	1	1	Covered	T47,T51,T48

 LINE       2161
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T53,T124,T128
1	1	1	Covered	T47,T51,T48

 LINE       2164
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T53,T127,T132
1	1	1	Covered	T47,T50,T51

 LINE       2167
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T51
1	1	1	Covered	T47,T50,T51

 LINE       2172
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T123
1	1	1	Covered	T47,T50,T51

 LINE       2177
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T53,T124,T243
1	1	1	Covered	T47,T50,T51

 LINE       2182
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T53,T130,T132
1	1	1	Covered	T47,T51,T48

 LINE       2187
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T53,T123,T124
1	1	1	Covered	T47,T50,T51

 LINE       2192
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T51
1	1	1	Covered	T47,T50,T51

 LINE       2195
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T12,T53,T51
1	1	1	Covered	T47,T51,T48

 LINE       2198
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T47,T50,T51
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T48,T123,T130
1	1	1	Covered	T47,T51,T48

---

Branch Coverage for Module : flash_ctrl_prim_reg_top

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	2033	2	2	100.00
IF	71	3	3	100.00
CASE	2233	22	22	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2033	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T47,T50
0	Covered	T12,T45,T46

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T45,T46
0	1	Covered	T48,T52,T243
0	0	Covered	T12,T45,T46

	LineNo.	Expression
-1-:	2233	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T12,T45,T47
addr_hit[1]	Covered	T12,T45,T47
addr_hit[2]	Covered	T12,T45,T47
addr_hit[3]	Covered	T12,T45,T47
addr_hit[4]	Covered	T12,T45,T46
addr_hit[5]	Covered	T12,T45,T47
addr_hit[6]	Covered	T12,T45,T47
addr_hit[7]	Covered	T12,T45,T47
addr_hit[8]	Covered	T12,T45,T47
addr_hit[9]	Covered	T12,T45,T47
addr_hit[10]	Covered	T12,T45,T47
addr_hit[11]	Covered	T12,T45,T47
addr_hit[12]	Covered	T12,T45,T47
addr_hit[13]	Covered	T12,T45,T47
addr_hit[14]	Covered	T12,T45,T47
addr_hit[15]	Covered	T12,T45,T47
addr_hit[16]	Covered	T12,T45,T47
addr_hit[17]	Covered	T12,T45,T47
addr_hit[18]	Covered	T12,T45,T47
addr_hit[19]	Covered	T12,T45,T47
addr_hit[20]	Covered	T12,T45,T47
default	Covered	T12,T45,T47

---

Assert Coverage for Module : flash_ctrl_prim_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	382029020	62343	0	0
reAfterRv	382029020	62343	0	0
rePulse	382029020	41819	0	0
wePulse	382029020	20524	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	62343	0	0
T12	4149	29	0	0
T45	1524	0	0	0
T46	1248	0	0	0
T47	283370	5376	0	0
T48	16856	635	0	0
T49	0	53	0	0
T50	2903	60	0	0
T51	4318	132	0	0
T52	0	647	0	0
T53	3132	38	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	0	109	0	0
T124	0	22	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	62343	0	0
T12	4149	29	0	0
T45	1524	0	0	0
T46	1248	0	0	0
T47	283370	5376	0	0
T48	16856	635	0	0
T49	0	53	0	0
T50	2903	60	0	0
T51	4318	132	0	0
T52	0	647	0	0
T53	3132	38	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	0	109	0	0
T124	0	22	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	41819	0	0
T12	4149	8	0	0
T45	1524	0	0	0
T46	1248	0	0	0
T47	283370	2688	0	0
T48	16856	421	0	0
T49	0	32	0	0
T50	2903	49	0	0
T51	4318	93	0	0
T52	0	436	0	0
T53	3132	7	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	0	74	0	0
T124	0	8	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	20524	0	0
T12	4149	21	0	0
T45	1524	0	0	0
T46	1248	0	0	0
T47	283370	2688	0	0
T48	16856	214	0	0
T49	0	21	0	0
T50	2903	11	0	0
T51	4318	39	0	0
T52	0	211	0	0
T53	3132	31	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	0	35	0	0
T124	0	14	0	0