Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T16

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1517684188	1514339788	0	0
CheckNGreaterZero_A	4200	4200	0	0
GntImpliesReady_A	1517684188	428612854	0	0
GntImpliesValid_A	1517684188	428612854	0	0
GrantKnown_A	1517684188	1514339788	0	0
IdxKnown_A	1517684188	1514339788	0	0
IndexIsCorrect_A	1517684188	428612854	0	0
NoReadyValidNoGrant_A	1517684188	176931568	0	0
Priority_A	1517684188	452633586	0	0
ReadyAndValidImplyGrant_A	1517684188	428612854	0	0
ReqAndReadyImplyGrant_A	1517684188	428612854	0	0
ReqImpliesValid_A	1517684188	452633586	0	0
ValidKnown_A	1517684188	1514339788	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	1514339788	0	0
T1	6884	6652	0	0
T2	4764	4172	0	0
T3	1452868	1452652	0	0
T4	23916	23536	0	0
T5	837376	789912	0	0
T10	14652	12032	0	0
T11	1604940	1604868	0	0
T15	16616	13872	0	0
T16	13008	12332	0	0
T17	4636	4412	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4200	4200	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	428612854	0	0
T1	6884	130	0	0
T2	4764	282	0	0
T3	1452868	421834	0	0
T4	23916	4164	0	0
T5	837376	264896	0	0
T6	0	125154	0	0
T10	14652	112	0	0
T11	1604940	514650	0	0
T15	16616	488	0	0
T16	13008	850	0	0
T17	4636	64	0	0
T18	0	10256	0	0
T41	0	532	0	0
T42	0	1539270	0	0
T43	0	60074	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	428612854	0	0
T1	6884	130	0	0
T2	4764	282	0	0
T3	1452868	421834	0	0
T4	23916	4164	0	0
T5	837376	264896	0	0
T6	0	125154	0	0
T10	14652	112	0	0
T11	1604940	514650	0	0
T15	16616	488	0	0
T16	13008	850	0	0
T17	4636	64	0	0
T18	0	10256	0	0
T41	0	532	0	0
T42	0	1539270	0	0
T43	0	60074	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	1514339788	0	0
T1	6884	6652	0	0
T2	4764	4172	0	0
T3	1452868	1452652	0	0
T4	23916	23536	0	0
T5	837376	789912	0	0
T10	14652	12032	0	0
T11	1604940	1604868	0	0
T15	16616	13872	0	0
T16	13008	12332	0	0
T17	4636	4412	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	1514339788	0	0
T1	6884	6652	0	0
T2	4764	4172	0	0
T3	1452868	1452652	0	0
T4	23916	23536	0	0
T5	837376	789912	0	0
T10	14652	12032	0	0
T11	1604940	1604868	0	0
T15	16616	13872	0	0
T16	13008	12332	0	0
T17	4636	4412	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	428612854	0	0
T1	6884	130	0	0
T2	4764	282	0	0
T3	1452868	421834	0	0
T4	23916	4164	0	0
T5	837376	264896	0	0
T6	0	125154	0	0
T10	14652	112	0	0
T11	1604940	514650	0	0
T15	16616	488	0	0
T16	13008	850	0	0
T17	4636	64	0	0
T18	0	10256	0	0
T41	0	532	0	0
T42	0	1539270	0	0
T43	0	60074	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	176931568	0	0
T1	6884	360	0	0
T2	4764	528	0	0
T3	1452868	309914	0	0
T4	23916	596	0	0
T5	837376	60088	0	0
T6	0	86660	0	0
T10	14652	448	0	0
T11	1604940	2109952	0	0
T15	16616	1856	0	0
T16	13008	952	0	0
T17	4636	256	0	0
T18	0	682	0	0
T41	0	462	0	0
T42	0	3306	0	0
T43	0	3528	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	452633586	0	0
T1	6884	130	0	0
T2	4764	292	0	0
T3	1452868	501944	0	0
T4	23916	4164	0	0
T5	837376	264896	0	0
T6	0	169572	0	0
T10	14652	112	0	0
T11	1604940	514650	0	0
T15	16616	488	0	0
T16	13008	850	0	0
T17	4636	64	0	0
T18	0	10256	0	0
T41	0	532	0	0
T42	0	1539270	0	0
T43	0	60074	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	428612854	0	0
T1	6884	130	0	0
T2	4764	282	0	0
T3	1452868	421834	0	0
T4	23916	4164	0	0
T5	837376	264896	0	0
T6	0	125154	0	0
T10	14652	112	0	0
T11	1604940	514650	0	0
T15	16616	488	0	0
T16	13008	850	0	0
T17	4636	64	0	0
T18	0	10256	0	0
T41	0	532	0	0
T42	0	1539270	0	0
T43	0	60074	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	428612854	0	0
T1	6884	130	0	0
T2	4764	282	0	0
T3	1452868	421834	0	0
T4	23916	4164	0	0
T5	837376	264896	0	0
T6	0	125154	0	0
T10	14652	112	0	0
T11	1604940	514650	0	0
T15	16616	488	0	0
T16	13008	850	0	0
T17	4636	64	0	0
T18	0	10256	0	0
T41	0	532	0	0
T42	0	1539270	0	0
T43	0	60074	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	452633586	0	0
T1	6884	130	0	0
T2	4764	292	0	0
T3	1452868	501944	0	0
T4	23916	4164	0	0
T5	837376	264896	0	0
T6	0	169572	0	0
T10	14652	112	0	0
T11	1604940	514650	0	0
T15	16616	488	0	0
T16	13008	850	0	0
T17	4636	64	0	0
T18	0	10256	0	0
T41	0	532	0	0
T42	0	1539270	0	0
T43	0	60074	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1517684188	1514339788	0	0
T1	6884	6652	0	0
T2	4764	4172	0	0
T3	1452868	1452652	0	0
T4	23916	23536	0	0
T5	837376	789912	0	0
T10	14652	12032	0	0
T11	1604940	1604868	0	0
T15	16616	13872	0	0
T16	13008	12332	0	0
T17	4636	4412	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T44
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T44
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	379421047	378584947	0	0
CheckNGreaterZero_A	1050	1050	0	0
GntImpliesReady_A	379421047	118846865	0	0
GntImpliesValid_A	379421047	118846865	0	0
GrantKnown_A	379421047	378584947	0	0
IdxKnown_A	379421047	378584947	0	0
IndexIsCorrect_A	379421047	118846865	0	0
NoReadyValidNoGrant_A	379421047	46122871	0	0
Priority_A	379421047	124949327	0	0
ReadyAndValidImplyGrant_A	379421047	118846865	0	0
ReqAndReadyImplyGrant_A	379421047	118846865	0	0
ReqImpliesValid_A	379421047	124949327	0	0
ValidKnown_A	379421047	378584947	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	118846865	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	118453	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	118846865	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	118453	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	118846865	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	118453	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	46122871	0	0
T1	1721	148	0	0
T2	1191	259	0	0
T3	363217	83389	0	0
T4	5979	208	0	0
T5	209344	30044	0	0
T10	3663	224	0	0
T11	401235	530688	0	0
T15	4154	928	0	0
T16	3252	476	0	0
T17	1159	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	124949327	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	148470	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	118846865	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	118453	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	118846865	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	118453	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	124949327	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	148470	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T44
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T44
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	379421047	378584947	0	0
CheckNGreaterZero_A	1050	1050	0	0
GntImpliesReady_A	379421047	118837995	0	0
GntImpliesValid_A	379421047	118837995	0	0
GrantKnown_A	379421047	378584947	0	0
IdxKnown_A	379421047	378584947	0	0
IndexIsCorrect_A	379421047	118837995	0	0
NoReadyValidNoGrant_A	379421047	46122871	0	0
Priority_A	379421047	124940457	0	0
ReadyAndValidImplyGrant_A	379421047	118837995	0	0
ReqAndReadyImplyGrant_A	379421047	118837995	0	0
ReqImpliesValid_A	379421047	124940457	0	0
ValidKnown_A	379421047	378584947	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	118837995	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	118453	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	118837995	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	118453	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	118837995	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	118453	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	46122871	0	0
T1	1721	148	0	0
T2	1191	259	0	0
T3	363217	83389	0	0
T4	5979	208	0	0
T5	209344	30044	0	0
T10	3663	224	0	0
T11	401235	530688	0	0
T15	4154	928	0	0
T16	3252	476	0	0
T17	1159	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	124940457	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	148470	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	118837995	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	118453	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	118837995	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	118453	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	124940457	0	0
T1	1721	45	0	0
T2	1191	133	0	0
T3	363217	148470	0	0
T4	5979	1301	0	0
T5	209344	132448	0	0
T10	3663	56	0	0
T11	401235	129428	0	0
T15	4154	244	0	0
T16	3252	425	0	0
T17	1159	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	379421047	378584947	0	0
CheckNGreaterZero_A	1050	1050	0	0
GntImpliesReady_A	379421047	95463997	0	0
GntImpliesValid_A	379421047	95463997	0	0
GrantKnown_A	379421047	378584947	0	0
IdxKnown_A	379421047	378584947	0	0
IndexIsCorrect_A	379421047	95463997	0	0
NoReadyValidNoGrant_A	379421047	42342913	0	0
Priority_A	379421047	101371901	0	0
ReadyAndValidImplyGrant_A	379421047	95463997	0	0
ReqAndReadyImplyGrant_A	379421047	95463997	0	0
ReqImpliesValid_A	379421047	101371901	0	0
ValidKnown_A	379421047	378584947	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	95463997	0	0
T1	1721	20	0	0
T2	1191	8	0	0
T3	363217	92464	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	62577	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	95463997	0	0
T1	1721	20	0	0
T2	1191	8	0	0
T3	363217	92464	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	62577	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	95463997	0	0
T1	1721	20	0	0
T2	1191	8	0	0
T3	363217	92464	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	62577	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	42342913	0	0
T1	1721	32	0	0
T2	1191	5	0	0
T3	363217	71568	0	0
T4	5979	90	0	0
T5	209344	0	0	0
T6	0	43330	0	0
T10	3663	0	0	0
T11	401235	524288	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	341	0	0
T41	0	231	0	0
T42	0	1653	0	0
T43	0	1764	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	101371901	0	0
T1	1721	20	0	0
T2	1191	13	0	0
T3	363217	102502	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	84786	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	95463997	0	0
T1	1721	20	0	0
T2	1191	8	0	0
T3	363217	92464	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	62577	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	95463997	0	0
T1	1721	20	0	0
T2	1191	8	0	0
T3	363217	92464	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	62577	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	101371901	0	0
T1	1721	20	0	0
T2	1191	13	0	0
T3	363217	102502	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	84786	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	379421047	378584947	0	0
CheckNGreaterZero_A	1050	1050	0	0
GntImpliesReady_A	379421047	95463997	0	0
GntImpliesValid_A	379421047	95463997	0	0
GrantKnown_A	379421047	378584947	0	0
IdxKnown_A	379421047	378584947	0	0
IndexIsCorrect_A	379421047	95463997	0	0
NoReadyValidNoGrant_A	379421047	42342913	0	0
Priority_A	379421047	101371901	0	0
ReadyAndValidImplyGrant_A	379421047	95463997	0	0
ReqAndReadyImplyGrant_A	379421047	95463997	0	0
ReqImpliesValid_A	379421047	101371901	0	0
ValidKnown_A	379421047	378584947	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	95463997	0	0
T1	1721	20	0	0
T2	1191	8	0	0
T3	363217	92464	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	62577	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	95463997	0	0
T1	1721	20	0	0
T2	1191	8	0	0
T3	363217	92464	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	62577	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	95463997	0	0
T1	1721	20	0	0
T2	1191	8	0	0
T3	363217	92464	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	62577	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	42342913	0	0
T1	1721	32	0	0
T2	1191	5	0	0
T3	363217	71568	0	0
T4	5979	90	0	0
T5	209344	0	0	0
T6	0	43330	0	0
T10	3663	0	0	0
T11	401235	524288	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	341	0	0
T41	0	231	0	0
T42	0	1653	0	0
T43	0	1764	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	101371901	0	0
T1	1721	20	0	0
T2	1191	13	0	0
T3	363217	102502	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	84786	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	95463997	0	0
T1	1721	20	0	0
T2	1191	8	0	0
T3	363217	92464	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	62577	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	95463997	0	0
T1	1721	20	0	0
T2	1191	8	0	0
T3	363217	92464	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	62577	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	101371901	0	0
T1	1721	20	0	0
T2	1191	13	0	0
T3	363217	102502	0	0
T4	5979	781	0	0
T5	209344	0	0	0
T6	0	84786	0	0
T10	3663	0	0	0
T11	401235	127897	0	0
T15	4154	0	0	0
T16	3252	0	0	0
T17	1159	0	0	0
T18	0	5128	0	0
T41	0	266	0	0
T42	0	769635	0	0
T43	0	30037	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379421047	378584947	0	0
T1	1721	1663	0	0
T2	1191	1043	0	0
T3	363217	363163	0	0
T4	5979	5884	0	0
T5	209344	197478	0	0
T10	3663	3008	0	0
T11	401235	401217	0	0
T15	4154	3468	0	0
T16	3252	3083	0	0
T17	1159	1103	0	0