Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382029020	30354220	0	0
DepthKnown_A	382029020	381106323	0	0
RvalidKnown_A	382029020	381106323	0	0
WreadyKnown_A	382029020	381106323	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	30354220	0	0
T12	4149	2951	0	0
T45	1524	142	0	0
T46	1248	142	0	0
T47	283370	25974	0	0
T48	16856	8567	0	0
T50	2903	348	0	0
T51	4318	1132	0	0
T53	3132	2050	0	0
T54	1356	124	0	0
T55	1164	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T12	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382029020	32705908	0	0
DepthKnown_A	382029020	381106323	0	0
RvalidKnown_A	382029020	381106323	0	0
WreadyKnown_A	382029020	381106323	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	32705908	0	0
T12	4149	1542	0	0
T45	1524	142	0	0
T46	1248	142	0	0
T47	283370	79575	0	0
T48	16856	5177	0	0
T50	2903	324	0	0
T51	4318	2169	0	0
T53	3132	1077	0	0
T54	1356	124	0	0
T55	1164	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T12	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382029020	3766328	0	0
DepthKnown_A	382029020	381106323	0	0
RvalidKnown_A	382029020	381106323	0	0
WreadyKnown_A	382029020	381106323	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	3766328	0	0
T12	4149	355	0	0
T45	1524	0	0	0
T46	1248	0	0	0
T47	283370	0	0	0
T48	16856	0	0	0
T50	2903	53	0	0
T51	4318	203	0	0
T53	3132	218	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	0	134	0	0
T124	0	152	0	0
T125	0	198	0	0
T126	0	150	0	0
T127	0	209	0	0
T128	0	123	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T12	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382029020	2336994	0	0
DepthKnown_A	382029020	381106323	0	0
RvalidKnown_A	382029020	381106323	0	0
WreadyKnown_A	382029020	381106323	0	0
gen_passthru_fifo.paramCheckPass	1265	1265	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	2336994	0	0
T12	4149	318	0	0
T45	1524	0	0	0
T46	1248	0	0	0
T47	283370	0	0	0
T48	16856	0	0	0
T50	2903	49	0	0
T51	4318	532	0	0
T53	3132	205	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	0	127	0	0
T124	0	122	0	0
T125	0	99	0	0
T126	0	128	0	0
T127	0	138	0	0
T128	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029020	381106323	0	0
T12	4149	4093	0	0
T45	1524	1435	0	0
T46	1248	1197	0	0
T47	283370	283275	0	0
T48	16856	14409	0	0
T50	2903	2803	0	0
T51	4318	4251	0	0
T53	3132	3053	0	0
T54	1356	1265	0	0
T55	1164	1091	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1265	1265	0	0
T12	1	1	0	0
T45	1	1	0	0
T46	1	1	0	0
T47	1	1	0	0
T48	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0