Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.22	97.14	92.20	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	382029047	4534	0	0
addr_rd_A	382029047	2178	0	0
bank0_info0_page_cfg_0_rd_A	382029047	2611	0	0
bank0_info0_page_cfg_1_rd_A	382029047	2203	0	0
bank0_info0_page_cfg_2_rd_A	382029047	3021	0	0
bank0_info0_page_cfg_3_rd_A	382029047	1891	0	0
bank0_info0_page_cfg_4_rd_A	382029047	2918	0	0
bank0_info0_page_cfg_5_rd_A	382029047	3039	0	0
bank0_info0_page_cfg_6_rd_A	382029047	2434	0	0
bank0_info0_page_cfg_7_rd_A	382029047	2607	0	0
bank0_info0_page_cfg_8_rd_A	382029047	2778	0	0
bank0_info0_page_cfg_9_rd_A	382029047	2719	0	0
bank0_info0_regwen_0_rd_A	382029047	2580	0	0
bank0_info0_regwen_1_rd_A	382029047	2640	0	0
bank0_info0_regwen_2_rd_A	382029047	2063	0	0
bank0_info0_regwen_3_rd_A	382029047	2372	0	0
bank0_info0_regwen_4_rd_A	382029047	1973	0	0
bank0_info0_regwen_5_rd_A	382029047	2044	0	0
bank0_info0_regwen_6_rd_A	382029047	1595	0	0
bank0_info0_regwen_7_rd_A	382029047	1567	0	0
bank0_info0_regwen_8_rd_A	382029047	2564	0	0
bank0_info0_regwen_9_rd_A	382029047	2006	0	0
bank0_info1_page_cfg_rd_A	382029047	2841	0	0
bank0_info1_regwen_rd_A	382029047	2551	0	0
bank0_info2_page_cfg_0_rd_A	382029047	1730	0	0
bank0_info2_page_cfg_1_rd_A	382029047	2000	0	0
bank0_info2_regwen_0_rd_A	382029047	2582	0	0
bank0_info2_regwen_1_rd_A	382029047	2188	0	0
bank1_info0_page_cfg_0_rd_A	382029047	3416	0	0
bank1_info0_page_cfg_1_rd_A	382029047	2436	0	0
bank1_info0_page_cfg_2_rd_A	382029047	2450	0	0
bank1_info0_page_cfg_3_rd_A	382029047	2521	0	0
bank1_info0_page_cfg_4_rd_A	382029047	3183	0	0
bank1_info0_page_cfg_5_rd_A	382029047	1900	0	0
bank1_info0_page_cfg_6_rd_A	382029047	2638	0	0
bank1_info0_page_cfg_7_rd_A	382029047	3042	0	0
bank1_info0_page_cfg_8_rd_A	382029047	2202	0	0
bank1_info0_page_cfg_9_rd_A	382029047	2819	0	0
bank1_info0_regwen_0_rd_A	382029047	2320	0	0
bank1_info0_regwen_1_rd_A	382029047	1830	0	0
bank1_info0_regwen_2_rd_A	382029047	2198	0	0
bank1_info0_regwen_3_rd_A	382029047	2534	0	0
bank1_info0_regwen_4_rd_A	382029047	2555	0	0
bank1_info0_regwen_5_rd_A	382029047	1526	0	0
bank1_info0_regwen_6_rd_A	382029047	2317	0	0
bank1_info0_regwen_7_rd_A	382029047	2503	0	0
bank1_info0_regwen_8_rd_A	382029047	2625	0	0
bank1_info0_regwen_9_rd_A	382029047	2676	0	0
bank1_info1_page_cfg_rd_A	382029047	2409	0	0
bank1_info1_regwen_rd_A	382029047	1827	0	0
bank1_info2_page_cfg_0_rd_A	382029047	2949	0	0
bank1_info2_page_cfg_1_rd_A	382029047	2193	0	0
bank1_info2_regwen_0_rd_A	382029047	2085	0	0
bank1_info2_regwen_1_rd_A	382029047	2142	0	0
bank_cfg_regwen_rd_A	382029047	2084	0	0
default_region_rd_A	382029047	2061	0	0
exec_rd_A	382029047	2522	0	0
fifo_lvl_rd_A	382029047	2629	0	0
fifo_rst_rd_A	382029047	2478	0	0
hw_info_cfg_override_rd_A	382029047	2766	0	0
intr_enable_rd_A	382029047	2890	0	0
mp_region_0_rd_A	382029047	2102	0	0
mp_region_1_rd_A	382029047	2285	0	0
mp_region_2_rd_A	382029047	2606	0	0
mp_region_3_rd_A	382029047	2349	0	0
mp_region_4_rd_A	382029047	2800	0	0
mp_region_5_rd_A	382029047	2699	0	0
mp_region_6_rd_A	382029047	2474	0	0
mp_region_7_rd_A	382029047	1801	0	0
mp_region_cfg_0_rd_A	382029047	3050	0	0
mp_region_cfg_1_rd_A	382029047	3070	0	0
mp_region_cfg_2_rd_A	382029047	2945	0	0
mp_region_cfg_3_rd_A	382029047	2873	0	0
mp_region_cfg_4_rd_A	382029047	2427	0	0
mp_region_cfg_5_rd_A	382029047	2462	0	0
mp_region_cfg_6_rd_A	382029047	3234	0	0
mp_region_cfg_7_rd_A	382029047	1995	0	0
phy_alert_cfg_rd_A	382029047	817	0	0
region_cfg_regwen_0_rd_A	382029047	2007	0	0
region_cfg_regwen_1_rd_A	382029047	2624	0	0
region_cfg_regwen_2_rd_A	382029047	2103	0	0
region_cfg_regwen_3_rd_A	382029047	2687	0	0
region_cfg_regwen_4_rd_A	382029047	2570	0	0
region_cfg_regwen_5_rd_A	382029047	1487	0	0
region_cfg_regwen_6_rd_A	382029047	2036	0	0
region_cfg_regwen_7_rd_A	382029047	1867	0	0
scratch_rd_A	382029047	1339	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	4534	0	0
T12	4149	163	0	0
T45	1524	0	0	0
T46	1248	0	0	0
T47	283370	0	0	0
T48	16856	0	0	0
T50	2903	0	0	0
T51	4318	2	0	0
T52	0	1	0	0
T53	3132	394	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	0	2	0	0
T124	0	153	0	0
T126	0	35	0	0
T127	0	22	0	0
T244	0	2	0	0
T245	0	3	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2178	0	0
T47	283370	261	0	0
T48	16856	0	0	0
T49	3585	0	0	0
T50	2903	0	0	0
T51	4318	5	0	0
T52	0	33	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	265	0	0
T294	0	3	0	0
T295	0	9	0	0
T296	0	3	0	0
T297	0	15	0	0
T298	0	17	0	0
T299	0	5	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2611	0	0
T47	283370	286	0	0
T48	16856	0	0	0
T49	3585	8	0	0
T50	2903	0	0	0
T51	4318	13	0	0
T52	0	192	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	547	0	0
T294	0	31	0	0
T295	0	25	0	0
T296	0	36	0	0
T297	0	51	0	0
T298	0	14	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2203	0	0
T47	283370	308	0	0
T48	16856	0	0	0
T49	3585	2	0	0
T50	2903	0	0	0
T51	4318	3	0	0
T52	0	171	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	614	0	0
T294	0	42	0	0
T295	0	22	0	0
T296	0	3	0	0
T297	0	25	0	0
T298	0	35	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	3021	0	0
T47	283370	237	0	0
T48	16856	0	0	0
T49	3585	37	0	0
T50	2903	0	0	0
T51	4318	5	0	0
T52	0	146	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	517	0	0
T294	0	45	0	0
T295	0	6	0	0
T296	0	31	0	0
T297	0	24	0	0
T298	0	19	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1891	0	0
T47	283370	195	0	0
T48	16856	0	0	0
T49	3585	5	0	0
T50	2903	0	0	0
T51	4318	11	0	0
T52	0	188	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	309	0	0
T294	0	33	0	0
T295	0	4	0	0
T296	0	43	0	0
T297	0	20	0	0
T298	0	24	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2918	0	0
T47	283370	239	0	0
T48	16856	0	0	0
T49	3585	26	0	0
T50	2903	0	0	0
T51	4318	6	0	0
T52	0	176	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	443	0	0
T294	0	71	0	0
T295	0	25	0	0
T296	0	5	0	0
T297	0	1	0	0
T298	0	21	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	3039	0	0
T47	283370	310	0	0
T48	16856	0	0	0
T49	3585	4	0	0
T50	2903	0	0	0
T51	4318	11	0	0
T52	0	91	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	556	0	0
T294	0	28	0	0
T295	0	27	0	0
T296	0	29	0	0
T297	0	35	0	0
T298	0	24	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2434	0	0
T47	283370	267	0	0
T48	16856	0	0	0
T49	3585	34	0	0
T50	2903	0	0	0
T51	4318	5	0	0
T52	0	198	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	454	0	0
T294	0	6	0	0
T295	0	4	0	0
T296	0	29	0	0
T297	0	14	0	0
T298	0	1	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2607	0	0
T47	283370	251	0	0
T48	16856	0	0	0
T49	3585	2	0	0
T50	2903	0	0	0
T51	4318	11	0	0
T52	0	166	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	251	0	0
T294	0	39	0	0
T295	0	25	0	0
T296	0	7	0	0
T297	0	43	0	0
T298	0	17	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2778	0	0
T47	283370	280	0	0
T48	16856	0	0	0
T49	3585	2	0	0
T50	2903	0	0	0
T51	4318	10	0	0
T52	0	151	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	273	0	0
T294	0	54	0	0
T295	0	18	0	0
T296	0	7	0	0
T297	0	38	0	0
T298	0	40	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2719	0	0
T47	283370	213	0	0
T48	16856	0	0	0
T49	3585	2	0	0
T50	2903	0	0	0
T51	4318	8	0	0
T52	0	150	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	301	0	0
T294	0	44	0	0
T295	0	22	0	0
T296	0	39	0	0
T297	0	18	0	0
T298	0	48	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2580	0	0
T47	283370	305	0	0
T48	16856	0	0	0
T49	3585	7	0	0
T50	2903	0	0	0
T51	4318	8	0	0
T52	0	38	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	519	0	0
T294	0	18	0	0
T295	0	5	0	0
T296	0	4	0	0
T297	0	25	0	0
T298	0	14	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2640	0	0
T47	283370	348	0	0
T48	16856	0	0	0
T49	3585	4	0	0
T50	2903	0	0	0
T51	4318	10	0	0
T52	0	38	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	542	0	0
T294	0	5	0	0
T296	0	7	0	0
T297	0	8	0	0
T298	0	22	0	0
T299	0	3	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2063	0	0
T47	283370	294	0	0
T48	16856	0	0	0
T49	3585	10	0	0
T50	2903	0	0	0
T51	4318	12	0	0
T52	0	37	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	547	0	0
T294	0	7	0	0
T295	0	1	0	0
T296	0	2	0	0
T297	0	5	0	0
T298	0	19	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2372	0	0
T47	283370	325	0	0
T48	16856	0	0	0
T49	3585	0	0	0
T50	2903	0	0	0
T51	4318	12	0	0
T52	0	30	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	259	0	0
T294	0	1	0	0
T295	0	3	0	0
T296	0	6	0	0
T297	0	18	0	0
T298	0	21	0	0
T299	0	5	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1973	0	0
T47	283370	360	0	0
T48	16856	0	0	0
T49	3585	5	0	0
T50	2903	0	0	0
T51	4318	9	0	0
T52	0	37	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	268	0	0
T294	0	9	0	0
T295	0	7	0	0
T297	0	13	0	0
T298	0	15	0	0
T299	0	6	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2044	0	0
T47	283370	245	0	0
T48	16856	0	0	0
T49	3585	4	0	0
T50	2903	0	0	0
T51	4318	5	0	0
T52	0	44	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	530	0	0
T294	0	1	0	0
T295	0	1	0	0
T296	0	2	0	0
T297	0	24	0	0
T298	0	42	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1595	0	0
T47	283370	264	0	0
T48	16856	0	0	0
T49	3585	4	0	0
T50	2903	0	0	0
T51	4318	17	0	0
T52	0	42	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	569	0	0
T294	0	13	0	0
T295	0	6	0	0
T296	0	8	0	0
T297	0	16	0	0
T298	0	21	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1567	0	0
T47	283370	255	0	0
T48	16856	0	0	0
T49	3585	0	0	0
T50	2903	0	0	0
T51	4318	15	0	0
T52	0	25	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	586	0	0
T294	0	5	0	0
T295	0	7	0	0
T296	0	4	0	0
T297	0	26	0	0
T298	0	25	0	0
T300	0	240	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2564	0	0
T47	283370	242	0	0
T48	16856	0	0	0
T49	3585	3	0	0
T50	2903	0	0	0
T51	4318	11	0	0
T52	0	43	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	547	0	0
T294	0	11	0	0
T295	0	6	0	0
T296	0	7	0	0
T297	0	2	0	0
T298	0	9	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2006	0	0
T47	283370	290	0	0
T48	16856	0	0	0
T49	3585	2	0	0
T50	2903	0	0	0
T51	4318	4	0	0
T52	0	37	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	494	0	0
T294	0	6	0	0
T295	0	3	0	0
T296	0	9	0	0
T297	0	33	0	0
T298	0	34	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2841	0	0
T47	283370	234	0	0
T48	16856	0	0	0
T49	3585	1	0	0
T50	2903	0	0	0
T51	4318	7	0	0
T52	0	224	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	273	0	0
T294	0	66	0	0
T295	0	12	0	0
T296	0	2	0	0
T297	0	8	0	0
T298	0	33	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2551	0	0
T47	283370	242	0	0
T48	16856	0	0	0
T49	3585	1	0	0
T50	2903	0	0	0
T51	4318	8	0	0
T52	0	29	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	557	0	0
T294	0	10	0	0
T295	0	2	0	0
T296	0	9	0	0
T297	0	1	0	0
T298	0	11	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1730	0	0
T47	283370	265	0	0
T48	16856	0	0	0
T49	3585	4	0	0
T50	2903	0	0	0
T51	4318	4	0	0
T52	0	153	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	254	0	0
T294	0	28	0	0
T295	0	11	0	0
T296	0	2	0	0
T297	0	29	0	0
T298	0	40	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2000	0	0
T47	283370	299	0	0
T48	16856	0	0	0
T49	3585	21	0	0
T50	2903	0	0	0
T51	4318	10	0	0
T52	0	184	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	327	0	0
T294	0	16	0	0
T295	0	6	0	0
T296	0	5	0	0
T298	0	41	0	0
T299	0	40	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2582	0	0
T47	283370	259	0	0
T48	16856	0	0	0
T49	3585	0	0	0
T50	2903	0	0	0
T51	4318	15	0	0
T52	0	47	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	552	0	0
T294	0	5	0	0
T295	0	1	0	0
T296	0	4	0	0
T297	0	3	0	0
T298	0	12	0	0
T299	0	7	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2188	0	0
T47	283370	278	0	0
T48	16856	0	0	0
T49	3585	8	0	0
T50	2903	0	0	0
T51	4318	13	0	0
T52	0	43	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	594	0	0
T294	0	3	0	0
T296	0	4	0	0
T297	0	14	0	0
T298	0	17	0	0
T299	0	1	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	3416	0	0
T47	283370	290	0	0
T48	16856	0	0	0
T49	3585	19	0	0
T50	2903	0	0	0
T51	4318	9	0	0
T52	0	278	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	645	0	0
T294	0	10	0	0
T295	0	33	0	0
T296	0	23	0	0
T297	0	10	0	0
T298	0	36	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2436	0	0
T47	283370	285	0	0
T48	16856	0	0	0
T49	3585	6	0	0
T50	2903	0	0	0
T51	4318	8	0	0
T52	0	121	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	310	0	0
T294	0	13	0	0
T295	0	21	0	0
T296	0	22	0	0
T297	0	44	0	0
T298	0	19	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2450	0	0
T47	283370	226	0	0
T48	16856	0	0	0
T49	3585	2	0	0
T50	2903	0	0	0
T51	4318	3	0	0
T52	0	116	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	227	0	0
T294	0	36	0	0
T295	0	4	0	0
T296	0	15	0	0
T297	0	36	0	0
T298	0	41	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2521	0	0
T47	283370	231	0	0
T48	16856	0	0	0
T49	3585	29	0	0
T50	2903	0	0	0
T51	4318	5	0	0
T52	0	161	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	549	0	0
T294	0	36	0	0
T295	0	28	0	0
T296	0	35	0	0
T297	0	14	0	0
T298	0	10	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	3183	0	0
T47	283370	308	0	0
T48	16856	0	0	0
T49	3585	9	0	0
T50	2903	0	0	0
T51	4318	6	0	0
T52	0	192	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	540	0	0
T294	0	33	0	0
T295	0	30	0	0
T296	0	7	0	0
T297	0	14	0	0
T298	0	34	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1900	0	0
T47	283370	260	0	0
T48	16856	0	0	0
T49	3585	2	0	0
T50	2903	0	0	0
T51	4318	12	0	0
T52	0	81	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T294	0	3	0	0
T295	0	22	0	0
T296	0	36	0	0
T297	0	29	0	0
T298	0	33	0	0
T299	0	2	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2638	0	0
T47	283370	230	0	0
T48	16856	0	0	0
T49	3585	20	0	0
T50	2903	0	0	0
T51	4318	8	0	0
T52	0	131	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	266	0	0
T294	0	7	0	0
T295	0	36	0	0
T296	0	37	0	0
T297	0	18	0	0
T298	0	30	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	3042	0	0
T47	283370	305	0	0
T48	16856	0	0	0
T49	3585	2	0	0
T50	2903	0	0	0
T51	4318	8	0	0
T52	0	201	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	494	0	0
T294	0	42	0	0
T295	0	20	0	0
T296	0	35	0	0
T297	0	14	0	0
T298	0	20	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2202	0	0
T47	283370	261	0	0
T48	16856	0	0	0
T49	3585	19	0	0
T50	2903	0	0	0
T51	4318	7	0	0
T52	0	192	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	250	0	0
T294	0	40	0	0
T295	0	28	0	0
T296	0	2	0	0
T297	0	13	0	0
T298	0	24	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2819	0	0
T47	283370	262	0	0
T48	16856	0	0	0
T49	3585	9	0	0
T50	2903	0	0	0
T51	4318	6	0	0
T52	0	155	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	348	0	0
T294	0	35	0	0
T295	0	22	0	0
T296	0	23	0	0
T297	0	13	0	0
T298	0	45	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2320	0	0
T47	283370	252	0	0
T48	16856	0	0	0
T49	3585	4	0	0
T50	2903	0	0	0
T51	4318	8	0	0
T52	0	16	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	263	0	0
T294	0	9	0	0
T295	0	9	0	0
T296	0	1	0	0
T297	0	38	0	0
T298	0	44	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1830	0	0
T47	283370	220	0	0
T48	16856	0	0	0
T49	3585	5	0	0
T50	2903	0	0	0
T51	4318	10	0	0
T52	0	30	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	266	0	0
T294	0	12	0	0
T295	0	5	0	0
T298	0	17	0	0
T299	0	3	0	0
T301	0	10	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2198	0	0
T47	283370	265	0	0
T48	16856	0	0	0
T49	3585	0	0	0
T50	2903	0	0	0
T51	4318	8	0	0
T52	0	35	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	249	0	0
T294	0	8	0	0
T295	0	4	0	0
T296	0	5	0	0
T297	0	15	0	0
T298	0	18	0	0
T299	0	5	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2534	0	0
T47	283370	235	0	0
T48	16856	0	0	0
T49	3585	6	0	0
T50	2903	0	0	0
T51	4318	4	0	0
T52	0	49	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	531	0	0
T294	0	9	0	0
T295	0	4	0	0
T296	0	2	0	0
T297	0	5	0	0
T298	0	45	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2555	0	0
T47	283370	260	0	0
T48	16856	0	0	0
T49	3585	9	0	0
T50	2903	0	0	0
T51	4318	16	0	0
T52	0	47	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	581	0	0
T294	0	14	0	0
T295	0	7	0	0
T296	0	1	0	0
T297	0	9	0	0
T298	0	10	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1526	0	0
T47	283370	262	0	0
T48	16856	0	0	0
T49	3585	1	0	0
T50	2903	0	0	0
T51	4318	10	0	0
T52	0	33	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T294	0	4	0	0
T295	0	1	0	0
T296	0	6	0	0
T297	0	28	0	0
T298	0	39	0	0
T299	0	4	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2317	0	0
T47	283370	225	0	0
T48	16856	0	0	0
T49	3585	2	0	0
T50	2903	0	0	0
T51	4318	6	0	0
T52	0	34	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	302	0	0
T294	0	7	0	0
T295	0	2	0	0
T296	0	2	0	0
T297	0	23	0	0
T298	0	20	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2503	0	0
T47	283370	222	0	0
T48	16856	0	0	0
T49	3585	0	0	0
T50	2903	0	0	0
T51	4318	5	0	0
T52	0	39	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	493	0	0
T294	0	6	0	0
T296	0	5	0	0
T297	0	53	0	0
T298	0	29	0	0
T299	0	5	0	0
T301	0	25	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2625	0	0
T47	283370	310	0	0
T48	16856	0	0	0
T49	3585	6	0	0
T50	2903	0	0	0
T51	4318	8	0	0
T52	0	49	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	540	0	0
T294	0	8	0	0
T296	0	3	0	0
T297	0	23	0	0
T298	0	20	0	0
T299	0	3	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2676	0	0
T47	283370	248	0	0
T48	16856	0	0	0
T49	3585	0	0	0
T50	2903	0	0	0
T51	4318	10	0	0
T52	0	49	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	613	0	0
T294	0	1	0	0
T295	0	6	0	0
T296	0	1	0	0
T297	0	20	0	0
T298	0	58	0	0
T301	0	10	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2409	0	0
T47	283370	291	0	0
T48	16856	0	0	0
T49	3585	3	0	0
T50	2903	0	0	0
T51	4318	6	0	0
T52	0	69	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	492	0	0
T294	0	54	0	0
T295	0	39	0	0
T296	0	3	0	0
T297	0	40	0	0
T298	0	37	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1827	0	0
T47	283370	260	0	0
T48	16856	0	0	0
T49	3585	8	0	0
T50	2903	0	0	0
T51	4318	17	0	0
T52	0	40	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	248	0	0
T294	0	7	0	0
T295	0	4	0	0
T297	0	26	0	0
T298	0	24	0	0
T299	0	2	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2949	0	0
T47	283370	248	0	0
T48	16856	0	0	0
T49	3585	0	0	0
T50	2903	0	0	0
T51	4318	6	0	0
T52	0	142	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	524	0	0
T294	0	4	0	0
T295	0	4	0	0
T296	0	41	0	0
T297	0	30	0	0
T298	0	1	0	0
T299	0	7	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2193	0	0
T47	283370	260	0	0
T48	16856	0	0	0
T49	3585	19	0	0
T50	2903	0	0	0
T51	4318	1	0	0
T52	0	198	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	478	0	0
T294	0	18	0	0
T295	0	6	0	0
T296	0	3	0	0
T297	0	2	0	0
T298	0	7	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2085	0	0
T47	283370	249	0	0
T48	16856	0	0	0
T49	3585	8	0	0
T50	2903	0	0	0
T51	4318	21	0	0
T52	0	38	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T294	0	6	0	0
T295	0	7	0	0
T296	0	6	0	0
T297	0	45	0	0
T298	0	27	0	0
T299	0	5	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2142	0	0
T47	283370	232	0	0
T48	16856	0	0	0
T49	3585	6	0	0
T50	2903	0	0	0
T51	4318	4	0	0
T52	0	38	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	271	0	0
T294	0	7	0	0
T295	0	2	0	0
T296	0	7	0	0
T297	0	33	0	0
T298	0	17	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2084	0	0
T47	283370	311	0	0
T48	16856	0	0	0
T49	3585	5	0	0
T50	2903	0	0	0
T51	4318	4	0	0
T52	0	31	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	515	0	0
T294	0	12	0	0
T295	0	8	0	0
T296	0	7	0	0
T297	0	8	0	0
T298	0	46	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2061	0	0
T47	283370	264	0	0
T48	16856	0	0	0
T49	3585	15	0	0
T50	2903	0	0	0
T51	4318	6	0	0
T52	0	104	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	247	0	0
T294	0	45	0	0
T295	0	4	0	0
T296	0	1	0	0
T297	0	29	0	0
T298	0	13	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2522	0	0
T47	283370	293	0	0
T48	16856	0	0	0
T49	3585	5	0	0
T50	2903	0	0	0
T51	4318	8	0	0
T52	0	19	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	569	0	0
T294	0	9	0	0
T295	0	10	0	0
T296	0	3	0	0
T297	0	16	0	0
T298	0	15	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2629	0	0
T47	283370	243	0	0
T48	16856	0	0	0
T49	3585	9	0	0
T50	2903	0	0	0
T51	4318	9	0	0
T52	0	53	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	578	0	0
T294	0	12	0	0
T295	0	10	0	0
T296	0	8	0	0
T297	0	30	0	0
T298	0	16	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2478	0	0
T47	283370	262	0	0
T48	16856	0	0	0
T49	3585	10	0	0
T50	2903	0	0	0
T51	4318	1	0	0
T52	0	56	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	498	0	0
T294	0	2	0	0
T295	0	8	0	0
T296	0	3	0	0
T297	0	50	0	0
T298	0	20	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2766	0	0
T47	283370	291	0	0
T48	16856	0	0	0
T49	3585	10	0	0
T50	2903	0	0	0
T51	4318	9	0	0
T52	0	57	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	645	0	0
T294	0	11	0	0
T296	0	7	0	0
T297	0	33	0	0
T298	0	58	0	0
T299	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2890	0	0
T47	283370	265	0	0
T48	16856	0	0	0
T49	3585	13	0	0
T50	2903	0	0	0
T51	4318	11	0	0
T52	0	159	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	302	0	0
T294	0	28	0	0
T295	0	24	0	0
T296	0	39	0	0
T297	0	32	0	0
T298	0	33	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2102	0	0
T47	283370	283	0	0
T48	16856	0	0	0
T49	3585	5	0	0
T50	2903	0	0	0
T51	4318	6	0	0
T52	0	59	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	529	0	0
T294	0	14	0	0
T296	0	6	0	0
T297	0	30	0	0
T298	0	11	0	0
T301	0	8	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2285	0	0
T47	283370	227	0	0
T48	16856	0	0	0
T49	3585	0	0	0
T50	2903	0	0	0
T51	4318	12	0	0
T52	0	57	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	241	0	0
T294	0	4	0	0
T295	0	6	0	0
T297	0	6	0	0
T298	0	20	0	0
T299	0	5	0	0
T301	0	3	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2606	0	0
T47	283370	272	0	0
T48	16856	0	0	0
T49	3585	9	0	0
T50	2903	0	0	0
T51	4318	5	0	0
T52	0	68	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	532	0	0
T294	0	7	0	0
T296	0	9	0	0
T297	0	16	0	0
T298	0	14	0	0
T299	0	1	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2349	0	0
T47	283370	249	0	0
T48	16856	0	0	0
T49	3585	2	0	0
T50	2903	0	0	0
T51	4318	4	0	0
T52	0	50	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	293	0	0
T294	0	17	0	0
T295	0	3	0	0
T296	0	1	0	0
T297	0	28	0	0
T298	0	12	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2800	0	0
T47	283370	310	0	0
T48	16856	0	0	0
T49	3585	2	0	0
T50	2903	0	0	0
T51	4318	15	0	0
T52	0	69	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	552	0	0
T294	0	26	0	0
T295	0	5	0	0
T296	0	6	0	0
T297	0	44	0	0
T298	0	17	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2699	0	0
T47	283370	255	0	0
T48	16856	0	0	0
T49	3585	7	0	0
T50	2903	0	0	0
T51	4318	4	0	0
T52	0	68	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	590	0	0
T294	0	15	0	0
T295	0	4	0	0
T296	0	2	0	0
T297	0	26	0	0
T298	0	6	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2474	0	0
T47	283370	295	0	0
T48	16856	0	0	0
T49	3585	4	0	0
T50	2903	0	0	0
T51	4318	6	0	0
T52	0	54	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	276	0	0
T294	0	8	0	0
T295	0	12	0	0
T296	0	10	0	0
T297	0	42	0	0
T298	0	40	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1801	0	0
T47	283370	243	0	0
T48	16856	0	0	0
T49	3585	6	0	0
T50	2903	0	0	0
T51	4318	16	0	0
T52	0	96	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	220	0	0
T294	0	19	0	0
T295	0	1	0	0
T296	0	3	0	0
T297	0	45	0	0
T298	0	13	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	3050	0	0
T47	283370	283	0	0
T48	16856	0	0	0
T49	3585	9	0	0
T50	2903	0	0	0
T51	4318	14	0	0
T52	0	249	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	454	0	0
T294	0	14	0	0
T295	0	1	0	0
T296	0	49	0	0
T297	0	37	0	0
T298	0	19	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	3070	0	0
T47	283370	243	0	0
T48	16856	0	0	0
T49	3585	6	0	0
T50	2903	0	0	0
T51	4318	13	0	0
T52	0	165	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	472	0	0
T294	0	32	0	0
T295	0	25	0	0
T296	0	6	0	0
T297	0	49	0	0
T298	0	30	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2945	0	0
T47	283370	214	0	0
T48	16856	0	0	0
T49	3585	21	0	0
T50	2903	0	0	0
T51	4318	5	0	0
T52	0	191	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	534	0	0
T294	0	1	0	0
T295	0	21	0	0
T296	0	6	0	0
T297	0	41	0	0
T298	0	17	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2873	0	0
T47	283370	268	0	0
T48	16856	0	0	0
T49	3585	18	0	0
T50	2903	0	0	0
T51	4318	11	0	0
T52	0	70	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	484	0	0
T294	0	1	0	0
T295	0	9	0	0
T296	0	31	0	0
T297	0	17	0	0
T298	0	33	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2427	0	0
T47	283370	230	0	0
T48	16856	0	0	0
T49	3585	9	0	0
T50	2903	0	0	0
T51	4318	1	0	0
T52	0	161	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	567	0	0
T294	0	9	0	0
T295	0	4	0	0
T296	0	32	0	0
T297	0	37	0	0
T298	0	13	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2462	0	0
T47	283370	287	0	0
T48	16856	0	0	0
T49	3585	39	0	0
T50	2903	0	0	0
T51	4318	4	0	0
T52	0	163	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	277	0	0
T294	0	5	0	0
T295	0	17	0	0
T296	0	3	0	0
T297	0	66	0	0
T298	0	23	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	3234	0	0
T47	283370	303	0	0
T48	16856	0	0	0
T49	3585	7	0	0
T50	2903	0	0	0
T51	4318	9	0	0
T52	0	181	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	593	0	0
T294	0	45	0	0
T295	0	5	0	0
T296	0	29	0	0
T297	0	30	0	0
T298	0	23	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1995	0	0
T47	283370	297	0	0
T48	16856	0	0	0
T49	3585	29	0	0
T50	2903	0	0	0
T51	4318	5	0	0
T52	0	159	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	524	0	0
T294	0	10	0	0
T295	0	6	0	0
T296	0	24	0	0
T297	0	35	0	0
T298	0	14	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	817	0	0
T48	16856	0	0	0
T49	3585	0	0	0
T51	4318	14	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T124	3492	0	0	0
T185	1189	0	0	0
T256	1816	0	0	0
T257	687	0	0	0
T262	0	219	0	0
T297	0	23	0	0
T298	0	19	0	0
T302	0	10	0	0
T303	0	4	0	0
T304	0	24	0	0
T305	0	4	0	0
T306	0	500	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2007	0	0
T47	283370	252	0	0
T48	16856	0	0	0
T49	3585	5	0	0
T50	2903	0	0	0
T51	4318	2	0	0
T52	0	32	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	493	0	0
T294	0	7	0	0
T295	0	1	0	0
T297	0	16	0	0
T298	0	38	0	0
T300	0	224	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2624	0	0
T47	283370	306	0	0
T48	16856	0	0	0
T49	3585	4	0	0
T50	2903	0	0	0
T51	4318	11	0	0
T52	0	47	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	529	0	0
T294	0	4	0	0
T295	0	3	0	0
T296	0	2	0	0
T297	0	29	0	0
T298	0	23	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2103	0	0
T47	283370	231	0	0
T48	16856	0	0	0
T49	3585	1	0	0
T50	2903	0	0	0
T51	4318	11	0	0
T52	0	32	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	541	0	0
T294	0	9	0	0
T295	0	6	0	0
T296	0	3	0	0
T297	0	17	0	0
T298	0	54	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2687	0	0
T47	283370	315	0	0
T48	16856	0	0	0
T49	3585	4	0	0
T50	2903	0	0	0
T51	4318	9	0	0
T52	0	42	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	546	0	0
T294	0	5	0	0
T295	0	3	0	0
T296	0	3	0	0
T297	0	41	0	0
T298	0	44	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2570	0	0
T47	283370	278	0	0
T48	16856	0	0	0
T49	3585	9	0	0
T50	2903	0	0	0
T51	4318	2	0	0
T52	0	45	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	523	0	0
T294	0	9	0	0
T295	0	9	0	0
T297	0	13	0	0
T298	0	6	0	0
T299	0	8	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1487	0	0
T47	283370	266	0	0
T48	16856	0	0	0
T49	3585	0	0	0
T50	2903	0	0	0
T51	4318	12	0	0
T52	0	43	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T294	0	18	0	0
T295	0	9	0	0
T296	0	5	0	0
T298	0	8	0	0
T299	0	9	0	0
T300	0	283	0	0
T301	0	16	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	2036	0	0
T47	283370	280	0	0
T48	16856	0	0	0
T49	3585	1	0	0
T50	2903	0	0	0
T51	4318	7	0	0
T52	0	42	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	564	0	0
T294	0	16	0	0
T295	0	6	0	0
T296	0	7	0	0
T297	0	2	0	0
T298	0	20	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1867	0	0
T47	283370	316	0	0
T48	16856	0	0	0
T49	3585	6	0	0
T50	2903	0	0	0
T51	4318	11	0	0
T52	0	52	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	229	0	0
T294	0	12	0	0
T296	0	6	0	0
T297	0	24	0	0
T298	0	28	0	0
T299	0	5	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382029047	1339	0	0
T47	283370	313	0	0
T48	16856	0	0	0
T49	3585	8	0	0
T50	2903	0	0	0
T51	4318	3	0	0
T52	0	36	0	0
T53	3132	0	0	0
T54	1356	0	0	0
T55	1164	0	0	0
T123	3744	0	0	0
T185	1189	0	0	0
T262	0	291	0	0
T294	0	6	0	0
T295	0	8	0	0
T296	0	7	0	0
T297	0	21	0	0
T298	0	30	0	0