| | | | | | | |
gen_flash_cores[0].u_core |
98.12 |
98.00 |
93.45 |
100.00 |
100.00 |
99.31 |
97.98 |
gen_prog_data.u_prog |
99.74 |
100.00 |
98.41 |
100.00 |
100.00 |
100.00 |
100.00 |
u_data_intg_chk |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
u_enc |
100.00 |
100.00 |
|
|
|
|
|
u_plain_enc |
100.00 |
100.00 |
|
|
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_disable_buf |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_erase |
97.22 |
100.00 |
88.89 |
|
100.00 |
100.00 |
|
u_host_arb |
93.98 |
75.93 |
100.00 |
|
|
100.00 |
100.00 |
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
gen_input_bufs[0].gen_fixed_arbiter.u_arb |
96.88 |
87.50 |
100.00 |
|
|
100.00 |
100.00 |
gen_input_bufs[0].u_req_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
gen_input_bufs[1].gen_fixed_arbiter.u_arb |
96.88 |
87.50 |
100.00 |
|
|
100.00 |
100.00 |
gen_input_bufs[1].u_req_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_host_outstanding_cnt |
100.00 |
|
|
100.00 |
|
|
|
u_rd |
97.59 |
99.15 |
93.31 |
100.00 |
|
99.25 |
96.23 |
gen_bufs[0].u_rd_buf |
94.64 |
100.00 |
78.57 |
|
|
100.00 |
100.00 |
gen_bufs[1].u_rd_buf |
94.64 |
100.00 |
78.57 |
|
|
100.00 |
100.00 |
gen_bufs[2].u_rd_buf |
94.64 |
100.00 |
78.57 |
|
|
100.00 |
100.00 |
gen_bufs[3].u_rd_buf |
94.64 |
100.00 |
78.57 |
|
|
100.00 |
100.00 |
u_bus_intg |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
u_dec |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intg_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_mask_storage |
92.90 |
100.00 |
78.26 |
|
|
93.33 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_plain_enc |
100.00 |
100.00 |
|
|
|
|
|
u_rd_buf_dep |
96.59 |
100.00 |
86.36 |
|
|
100.00 |
100.00 |
u_rd_storage |
96.55 |
100.00 |
82.76 |
100.00 |
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
100.00 |
|
|
|
gen_secure_ptrs.u_rptr |
100.00 |
|
|
100.00 |
|
|
|
gen_secure_ptrs.u_wptr |
100.00 |
|
|
100.00 |
|
|
|
u_rsp_order_fifo |
96.55 |
100.00 |
82.76 |
100.00 |
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
100.00 |
|
|
|
gen_secure_ptrs.u_rptr |
100.00 |
|
|
100.00 |
|
|
|
gen_secure_ptrs.u_wptr |
100.00 |
|
|
100.00 |
|
|
|
u_valid_random |
94.17 |
92.31 |
97.69 |
|
|
100.00 |
86.67 |
u_scramble |
98.18 |
100.00 |
90.91 |
100.00 |
|
100.00 |
100.00 |
gen_gf_mult.u_mult |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
gen_prince.u_cipher |
100.00 |
|
|
100.00 |
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_flash_cores[0].u_host_rsp_fifo |
97.84 |
100.00 |
89.19 |
100.00 |
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
100.00 |
|
|
|
gen_secure_ptrs.u_rptr |
100.00 |
|
|
100.00 |
|
|
|
gen_secure_ptrs.u_wptr |
100.00 |
|
|
100.00 |
|
|
|
gen_flash_cores[1].u_core |
97.81 |
98.00 |
92.59 |
98.97 |
100.00 |
99.31 |
97.98 |
gen_prog_data.u_prog |
98.64 |
100.00 |
96.83 |
95.00 |
100.00 |
100.00 |
100.00 |
u_data_intg_chk |
97.50 |
100.00 |
|
95.00 |
|
|
|
u_data_chk |
95.00 |
|
|
95.00 |
|
|
|
u_enc |
100.00 |
100.00 |
|
|
|
|
|
u_plain_enc |
100.00 |
100.00 |
|
|
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_disable_buf |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_erase |
97.22 |
100.00 |
88.89 |
|
100.00 |
100.00 |
|
u_host_arb |
91.95 |
75.93 |
91.89 |
|
|
100.00 |
100.00 |
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
gen_input_bufs[0].gen_fixed_arbiter.u_arb |
96.88 |
87.50 |
100.00 |
|
|
100.00 |
100.00 |
gen_input_bufs[0].u_req_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
gen_input_bufs[1].gen_fixed_arbiter.u_arb |
96.88 |
87.50 |
100.00 |
|
|
100.00 |
100.00 |
gen_input_bufs[1].u_req_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_host_outstanding_cnt |
100.00 |
|
|
100.00 |
|
|
|
u_rd |
97.59 |
99.15 |
93.31 |
100.00 |
|
99.25 |
96.23 |
gen_bufs[0].u_rd_buf |
94.64 |
100.00 |
78.57 |
|
|
100.00 |
100.00 |
gen_bufs[1].u_rd_buf |
94.64 |
100.00 |
78.57 |
|
|
100.00 |
100.00 |
gen_bufs[2].u_rd_buf |
94.64 |
100.00 |
78.57 |
|
|
100.00 |
100.00 |
gen_bufs[3].u_rd_buf |
94.64 |
100.00 |
78.57 |
|
|
100.00 |
100.00 |
u_bus_intg |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
u_dec |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intg_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_mask_storage |
92.90 |
100.00 |
78.26 |
|
|
93.33 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_plain_enc |
100.00 |
100.00 |
|
|
|
|
|
u_rd_buf_dep |
96.59 |
100.00 |
86.36 |
|
|
100.00 |
100.00 |
u_rd_storage |
96.55 |
100.00 |
82.76 |
100.00 |
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
100.00 |
|
|
|
gen_secure_ptrs.u_rptr |
100.00 |
|
|
100.00 |
|
|
|
gen_secure_ptrs.u_wptr |
100.00 |
|
|
100.00 |
|
|
|
u_rsp_order_fifo |
96.55 |
100.00 |
82.76 |
100.00 |
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
100.00 |
|
|
|
gen_secure_ptrs.u_rptr |
100.00 |
|
|
100.00 |
|
|
|
gen_secure_ptrs.u_wptr |
100.00 |
|
|
100.00 |
|
|
|
u_valid_random |
94.17 |
92.31 |
97.69 |
|
|
100.00 |
86.67 |
u_scramble |
98.18 |
100.00 |
90.91 |
100.00 |
|
100.00 |
100.00 |
gen_gf_mult.u_mult |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
gen_prince.u_cipher |
100.00 |
|
|
100.00 |
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_flash_cores[1].u_host_rsp_fifo |
96.76 |
100.00 |
83.78 |
100.00 |
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
100.00 |
|
|
|
gen_secure_ptrs.u_rptr |
100.00 |
|
|
100.00 |
|
|
|
gen_secure_ptrs.u_wptr |
100.00 |
|
|
100.00 |
|
|
|
u_bank_sequence_fifo |
95.19 |
100.00 |
80.77 |
|
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_disable_buf |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_flash |
97.83 |
98.77 |
94.77 |
100.00 |
93.75 |
99.67 |
100.00 |
gen_generic.u_impl_generic |
97.83 |
98.77 |
94.77 |
100.00 |
93.75 |
99.67 |
100.00 |
subtree... |
|
|
|
|
|
|
|
u_lc_nvm_debug_en_sync |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_flops.u_prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_region_sel |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|