Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T19

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1688929012	1685781512	0	0
CheckNGreaterZero_A	4244	4244	0	0
GntImpliesReady_A	1688929012	445341232	0	0
GntImpliesValid_A	1688929012	445341232	0	0
GrantKnown_A	1688929012	1685781512	0	0
IdxKnown_A	1688929012	1685781512	0	0
IndexIsCorrect_A	1688929012	445341232	0	0
NoReadyValidNoGrant_A	1688929012	179347765	0	0
Priority_A	1688929012	469850515	0	0
ReadyAndValidImplyGrant_A	1688929012	445341232	0	0
ReqAndReadyImplyGrant_A	1688929012	445341232	0	0
ReqImpliesValid_A	1688929012	469850515	0	0
ValidKnown_A	1688929012	1685781512	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	1685781512	0	0
T1	7504	6884	0	0
T2	6636	6236	0	0
T3	218908	218520	0	0
T4	137288	136936	0	0
T5	5416	5096	0	0
T6	21988	21668	0	0
T8	1272100	1271836	0	0
T19	25620	23240	0	0
T20	5852	5216	0	0
T21	12772	12380	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4244	4244	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T8	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	445341232	0	0
T1	7504	144	0	0
T2	6636	600	0	0
T3	218908	42944	0	0
T4	137288	2128	0	0
T5	5416	84	0	0
T6	21988	6078	0	0
T7	0	6	0	0
T8	1272100	328574	0	0
T19	25620	1384	0	0
T20	5852	148	0	0
T21	12772	64	0	0
T22	0	1514492	0	0
T24	0	34816	0	0
T28	0	426	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	445341232	0	0
T1	7504	144	0	0
T2	6636	600	0	0
T3	218908	42944	0	0
T4	137288	2128	0	0
T5	5416	84	0	0
T6	21988	6078	0	0
T7	0	6	0	0
T8	1272100	328574	0	0
T19	25620	1384	0	0
T20	5852	148	0	0
T21	12772	64	0	0
T22	0	1514492	0	0
T24	0	34816	0	0
T28	0	426	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	1685781512	0	0
T1	7504	6884	0	0
T2	6636	6236	0	0
T3	218908	218520	0	0
T4	137288	136936	0	0
T5	5416	5096	0	0
T6	21988	21668	0	0
T8	1272100	1271836	0	0
T19	25620	23240	0	0
T20	5852	5216	0	0
T21	12772	12380	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	1685781512	0	0
T1	7504	6884	0	0
T2	6636	6236	0	0
T3	218908	218520	0	0
T4	137288	136936	0	0
T5	5416	5096	0	0
T6	21988	21668	0	0
T8	1272100	1271836	0	0
T19	25620	23240	0	0
T20	5852	5216	0	0
T21	12772	12380	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	445341232	0	0
T1	7504	144	0	0
T2	6636	600	0	0
T3	218908	42944	0	0
T4	137288	2128	0	0
T5	5416	84	0	0
T6	21988	6078	0	0
T7	0	6	0	0
T8	1272100	328574	0	0
T19	25620	1384	0	0
T20	5852	148	0	0
T21	12772	64	0	0
T22	0	1514492	0	0
T24	0	34816	0	0
T28	0	426	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	179347765	0	0
T1	3752	512	0	0
T2	6636	282	0	0
T3	218908	60378	0	0
T4	137288	2816	0	0
T5	5416	286	0	0
T6	21988	750	0	0
T7	0	10	0	0
T8	1272100	345510	0	0
T19	25620	3292	0	0
T20	5852	512	0	0
T21	12772	256	0	0
T22	0	4758	0	0
T23	0	16	0	0
T24	0	85302	0	0
T28	17826	674	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	469850515	0	0
T1	7504	144	0	0
T2	6636	600	0	0
T3	218908	53526	0	0
T4	137288	2128	0	0
T5	5416	84	0	0
T6	21988	6094	0	0
T7	0	6	0	0
T8	1272100	397228	0	0
T19	25620	1384	0	0
T20	5852	148	0	0
T21	12772	64	0	0
T22	0	1514492	0	0
T24	0	36192	0	0
T28	0	476	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	445341232	0	0
T1	7504	144	0	0
T2	6636	600	0	0
T3	218908	42944	0	0
T4	137288	2128	0	0
T5	5416	84	0	0
T6	21988	6078	0	0
T7	0	6	0	0
T8	1272100	328574	0	0
T19	25620	1384	0	0
T20	5852	148	0	0
T21	12772	64	0	0
T22	0	1514492	0	0
T24	0	34816	0	0
T28	0	426	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	445341232	0	0
T1	7504	144	0	0
T2	6636	600	0	0
T3	218908	42944	0	0
T4	137288	2128	0	0
T5	5416	84	0	0
T6	21988	6078	0	0
T7	0	6	0	0
T8	1272100	328574	0	0
T19	25620	1384	0	0
T20	5852	148	0	0
T21	12772	64	0	0
T22	0	1514492	0	0
T24	0	34816	0	0
T28	0	426	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	469850515	0	0
T1	7504	144	0	0
T2	6636	600	0	0
T3	218908	53526	0	0
T4	137288	2128	0	0
T5	5416	84	0	0
T6	21988	6094	0	0
T7	0	6	0	0
T8	1272100	397228	0	0
T19	25620	1384	0	0
T20	5852	148	0	0
T21	12772	64	0	0
T22	0	1514492	0	0
T24	0	36192	0	0
T28	0	476	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1688929012	1685781512	0	0
T1	7504	6884	0	0
T2	6636	6236	0	0
T3	218908	218520	0	0
T4	137288	136936	0	0
T5	5416	5096	0	0
T6	21988	21668	0	0
T8	1272100	1271836	0	0
T19	25620	23240	0	0
T20	5852	5216	0	0
T21	12772	12380	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422232253	421445378	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	422232253	122235286	0	0
GntImpliesValid_A	422232253	122235286	0	0
GrantKnown_A	422232253	421445378	0	0
IdxKnown_A	422232253	421445378	0	0
IndexIsCorrect_A	422232253	122235286	0	0
NoReadyValidNoGrant_A	422232253	46756609	0	0
Priority_A	422232253	128476379	0	0
ReadyAndValidImplyGrant_A	422232253	122235286	0	0
ReqAndReadyImplyGrant_A	422232253	122235286	0	0
ReqImpliesValid_A	422232253	128476379	0	0
ValidKnown_A	422232253	421445378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	122235286	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	12463	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1537	0	0
T8	318025	91824	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	122235286	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	12463	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1537	0	0
T8	318025	91824	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	122235286	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	12463	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1537	0	0
T8	318025	91824	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	46756609	0	0
T1	1876	256	0	0
T2	1659	128	0	0
T3	54727	17537	0	0
T4	34322	1408	0	0
T5	1354	143	0	0
T6	5497	251	0	0
T8	318025	78957	0	0
T19	6405	1118	0	0
T20	1463	256	0	0
T21	3193	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	128476379	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	15519	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1540	0	0
T8	318025	102300	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	122235286	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	12463	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1537	0	0
T8	318025	91824	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	122235286	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	12463	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1537	0	0
T8	318025	91824	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	128476379	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	15519	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1540	0	0
T8	318025	102300	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422232253	421445378	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	422232253	122213318	0	0
GntImpliesValid_A	422232253	122213318	0	0
GrantKnown_A	422232253	421445378	0	0
IdxKnown_A	422232253	421445378	0	0
IndexIsCorrect_A	422232253	122213318	0	0
NoReadyValidNoGrant_A	422232253	46756650	0	0
Priority_A	422232253	128454370	0	0
ReadyAndValidImplyGrant_A	422232253	122213318	0	0
ReqAndReadyImplyGrant_A	422232253	122213318	0	0
ReqImpliesValid_A	422232253	128454370	0	0
ValidKnown_A	422232253	421445378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	122213318	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	12463	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1537	0	0
T8	318025	91824	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	122213318	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	12463	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1537	0	0
T8	318025	91824	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	122213318	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	12463	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1537	0	0
T8	318025	91824	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	46756650	0	0
T1	1876	256	0	0
T2	1659	128	0	0
T3	54727	17537	0	0
T4	34322	1408	0	0
T5	1354	143	0	0
T6	5497	251	0	0
T8	318025	78957	0	0
T19	6405	1118	0	0
T20	1463	256	0	0
T21	3193	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	128454370	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	15519	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1540	0	0
T8	318025	102300	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	122213318	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	12463	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1537	0	0
T8	318025	91824	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	122213318	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	12463	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1537	0	0
T8	318025	91824	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	128454370	0	0
T1	1876	64	0	0
T2	1659	292	0	0
T3	54727	15519	0	0
T4	34322	1064	0	0
T5	1354	42	0	0
T6	5497	1540	0	0
T8	318025	102300	0	0
T19	6405	392	0	0
T20	1463	74	0	0
T21	3193	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T19,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T19,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T19,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T19,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T19,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T19,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T19,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422232253	421445378	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	422232253	100446314	0	0
GntImpliesValid_A	422232253	100446314	0	0
GrantKnown_A	422232253	421445378	0	0
IdxKnown_A	422232253	421445378	0	0
IndexIsCorrect_A	422232253	100446314	0	0
NoReadyValidNoGrant_A	422232253	42917253	0	0
Priority_A	422232253	106459883	0	0
ReadyAndValidImplyGrant_A	422232253	100446314	0	0
ReqAndReadyImplyGrant_A	422232253	100446314	0	0
ReqImpliesValid_A	422232253	106459883	0	0
ValidKnown_A	422232253	421445378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	100446314	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	9009	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1502	0	0
T7	0	3	0	0
T8	318025	72463	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	17408	0	0
T28	0	213	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	100446314	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	9009	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1502	0	0
T7	0	3	0	0
T8	318025	72463	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	17408	0	0
T28	0	213	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	100446314	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	9009	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1502	0	0
T7	0	3	0	0
T8	318025	72463	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	17408	0	0
T28	0	213	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	42917253	0	0
T2	1659	13	0	0
T3	54727	12652	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	124	0	0
T7	0	5	0	0
T8	318025	93798	0	0
T19	6405	528	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	2379	0	0
T23	0	8	0	0
T24	0	42651	0	0
T28	8913	337	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	106459883	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	11244	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1507	0	0
T7	0	3	0	0
T8	318025	96314	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	18096	0	0
T28	0	238	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	100446314	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	9009	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1502	0	0
T7	0	3	0	0
T8	318025	72463	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	17408	0	0
T28	0	213	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	100446314	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	9009	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1502	0	0
T7	0	3	0	0
T8	318025	72463	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	17408	0	0
T28	0	213	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	106459883	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	11244	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1507	0	0
T7	0	3	0	0
T8	318025	96314	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	18096	0	0
T28	0	238	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T19,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T19,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T19,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T19,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T19,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T19,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T19,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422232253	421445378	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	422232253	100446314	0	0
GntImpliesValid_A	422232253	100446314	0	0
GrantKnown_A	422232253	421445378	0	0
IdxKnown_A	422232253	421445378	0	0
IndexIsCorrect_A	422232253	100446314	0	0
NoReadyValidNoGrant_A	422232253	42917253	0	0
Priority_A	422232253	106459883	0	0
ReadyAndValidImplyGrant_A	422232253	100446314	0	0
ReqAndReadyImplyGrant_A	422232253	100446314	0	0
ReqImpliesValid_A	422232253	106459883	0	0
ValidKnown_A	422232253	421445378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	100446314	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	9009	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1502	0	0
T7	0	3	0	0
T8	318025	72463	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	17408	0	0
T28	0	213	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	100446314	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	9009	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1502	0	0
T7	0	3	0	0
T8	318025	72463	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	17408	0	0
T28	0	213	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	100446314	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	9009	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1502	0	0
T7	0	3	0	0
T8	318025	72463	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	17408	0	0
T28	0	213	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	42917253	0	0
T2	1659	13	0	0
T3	54727	12652	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	124	0	0
T7	0	5	0	0
T8	318025	93798	0	0
T19	6405	528	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	2379	0	0
T23	0	8	0	0
T24	0	42651	0	0
T28	8913	337	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	106459883	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	11244	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1507	0	0
T7	0	3	0	0
T8	318025	96314	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	18096	0	0
T28	0	238	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	100446314	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	9009	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1502	0	0
T7	0	3	0	0
T8	318025	72463	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	17408	0	0
T28	0	213	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	100446314	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	9009	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1502	0	0
T7	0	3	0	0
T8	318025	72463	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	17408	0	0
T28	0	213	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	106459883	0	0
T1	1876	8	0	0
T2	1659	8	0	0
T3	54727	11244	0	0
T4	34322	0	0	0
T5	1354	0	0	0
T6	5497	1507	0	0
T7	0	3	0	0
T8	318025	96314	0	0
T19	6405	300	0	0
T20	1463	0	0	0
T21	3193	0	0	0
T22	0	757246	0	0
T24	0	18096	0	0
T28	0	238	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422232253	421445378	0	0
T1	1876	1721	0	0
T2	1659	1559	0	0
T3	54727	54630	0	0
T4	34322	34234	0	0
T5	1354	1274	0	0
T6	5497	5417	0	0
T8	318025	317959	0	0
T19	6405	5810	0	0
T20	1463	1304	0	0
T21	3193	3095	0	0