Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.36 100.00 83.96 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.81 98.00 92.59 98.97 100.00 99.31 97.98


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.26 97.67 85.11 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 98.64 100.00 96.83 95.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 97.22 100.00 88.89 100.00 100.00
u_host_arb 91.95 75.93 91.89 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.59 99.15 93.31 100.00 99.25 96.23
u_scramble 98.18 100.00 90.91 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.87 100.00 91.51 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.12 98.00 93.45 100.00 100.00 99.31 97.98


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.26 97.67 85.11 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 99.74 100.00 98.41 100.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 97.22 100.00 88.89 100.00 100.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.59 99.15 93.31 100.00 99.25 96.23
u_scramble 98.18 100.00 90.91 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
TOTAL7979100.00
ALWAYS15466100.00
ALWAYS16733100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20311100.00
ALWAYS20644100.00
ALWAYS21866100.00
ALWAYS23266100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32311100.00
ALWAYS3272929100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN39911100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN41711100.00
CONT_ASSIGN43011100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN57811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN60211100.00
CONT_ASSIGN60311100.00
CONT_ASSIGN60411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
MISSING_ELSE
167 3 3
199 1 1
203 1 1
206 1 1
207 1 1
208 1 1
209 1 1
MISSING_ELSE
218 1 1
219 1 1
220 1 1
221 1 1
222 1 1
223 1 1
MISSING_ELSE
232 1 1
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
MISSING_ELSE
279 1 1
282 1 1
283 1 1
284 1 1
289 1 1
319 1 1
323 1 1
327 1 1
328 1 1
329 1 1
330 1 1
331 1 1
333 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
342 1 1
343 1 1
MISSING_ELSE
349 1 1
350 1 1
351 1 1
MISSING_ELSE
358 1 1
359 1 1
360 1 1
361 1 1
MISSING_ELSE
367 1 1
368 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
376 1 1
377 1 1
390 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
399 1 1
400 1 1
417 1 1
430 1 1
550 1 1
578 1 1
585 1 1
602 1 1
603 1 1
604 1 1


Cond Coverage for Module : flash_phy_core
TotalCoveredPercent
Conditions1069791.51
Logical1069791.51
Non-Logical00
Event00

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T19
11CoveredT23,T90,T9

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T19
11Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT23,T90,T9

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT3,T5,T19
1CoveredT1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT3,T5,T19
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT3,T5,T19
1CoveredT1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T5,T19
110Not Covered
111CoveredT3,T5,T19

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT3,T5,T19
101CoveredT3,T5,T19
110CoveredT7,T108,T132
111CoveredT3,T5,T19

 LINE       283
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT3,T8,T6
11CoveredT3,T5,T19

 LINE       284
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T19
11CoveredT3,T5,T19

 LINE       319
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       319
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT143,T144,T145
10CoveredT1,T2,T3
11CoveredT3,T5,T19

 LINE       323
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT3,T5,T19
10CoveredT1,T2,T3
11CoveredT3,T8,T28

 LINE       338
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       340
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T20,T8
10CoveredT2,T4,T12
11CoveredT1,T20,T8

 LINE       390
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T108,T132
10CoveredT227

 LINE       390
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT227

 LINE       390
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT3,T5,T19
10CoveredT1,T2,T3
11CoveredT7,T108,T132

 LINE       390
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       394
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       395
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       396
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       397
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       398
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       399
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T20,T8
10CoveredT1,T2,T3
11CoveredT1,T20,T8

 LINE       400
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT2,T4,T12
10CoveredT1,T2,T3
11CoveredT2,T4,T12

 LINE       400
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T56,T63
10CoveredT2,T4,T12

 LINE       430
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       430
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT3,T5,T19
10Not Covered
11Not Covered

 LINE       430
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       433
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       433
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T5,T19
10CoveredT1,T2,T3

 LINE       433
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       550
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T20,T8

 LINE       556
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T20,T8

 LINE       556
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T20,T8

 LINE       556
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T20,T8

 LINE       578
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T29
10CoveredT17,T18,T29

FSM Coverage for Module : flash_phy_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 343 Covered T16
StCtrlProg 341 Covered T16
StCtrlRead 339 Covered T16
StDisable 337 Covered T16
StIdle 351 Covered T16


transitionsLine No.CoveredTests
StCtrl->StIdle 371 Covered T16
StCtrlProg->StIdle 361 Covered T16
StCtrlRead->StIdle 351 Covered T16
StIdle->StCtrl 343 Covered T16
StIdle->StCtrlProg 341 Covered T16
StIdle->StCtrlRead 339 Covered T16
StIdle->StDisable 337 Covered T16



Branch Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 319 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 396 2 2 100.00
TERNARY 397 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 433 2 1 50.00
TERNARY 556 2 2 100.00
IF 154 4 4 100.00
IF 167 2 2 100.00
IF 206 3 3 100.00
IF 218 4 4 100.00
IF 232 4 4 100.00
CASE 333 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 319 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T3,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 396 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 397 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T20,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 433 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 556 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T20,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 154 if ((!rst_ni)) -2-: 156 if (ctrl_rsp_vld) -3-: 158 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T3,T8,T28
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 167 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 206 if ((!rst_ni)) -2-: 208 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T23,T90,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 218 if ((!rst_ni)) -2-: 220 if ((host_outstanding == '0)) -3-: 222 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T9,T15
0 0 0 Covered T3,T5,T19


LineNo. Expression -1-: 232 if ((!rst_ni)) -2-: 234 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 236 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T9,T15
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 333 case (state_q) -2-: 336 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 338 if ((ctrl_gnt && rd_i)) -4-: 340 if ((ctrl_gnt && prog_i)) -5-: 342 if (ctrl_gnt) -6-: 349 if (rd_stage_data_valid) -7-: 359 if (prog_ack) -8-: 369 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T12,T13,T14
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T20,T8
StIdle 0 0 0 1 - - - Covered T2,T4,T12
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T20,T8
StCtrlProg - - - - - 0 - Covered T1,T20,T8
StCtrl - - - - - - 1 Covered T2,T4,T12
StCtrl - - - - - - 0 Covered T2,T4,T12
StDisable - - - - - - - Covered T12,T13,T14
default - - - - - - - Covered T17,T18,T9


Assert Coverage for Module : flash_phy_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 844464506 4408765 0 0
CtrlPrio_A 844464506 4408763 0 0
HostTransIdleChk_A 844464506 46031381 0 0
NoRemainder_A 2122 2122 0 0
OneHotReqs_A 844464506 842890756 0 0
Pow2Multiple_A 2122 2122 0 0
RdTxnCheck_A 844037616 842463866 0 0
u_state_regs_A 844464506 842890756 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 844464506 4408765 0 0
T3 109454 2018 0 0
T4 68644 0 0 0
T5 2708 0 0 0
T6 10994 0 0 0
T7 2980 0 0 0
T8 636050 19949 0 0
T19 12810 0 0 0
T20 2926 0 0 0
T21 6386 0 0 0
T24 0 6253 0 0
T28 17826 134 0 0
T33 0 3022 0 0
T51 0 5191 0 0
T57 0 5553 0 0
T58 0 5289 0 0
T62 0 16793 0 0
T135 0 81473 0 0
T228 0 3114 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 844464506 4408763 0 0
T3 109454 2018 0 0
T4 68644 0 0 0
T5 2708 0 0 0
T6 10994 0 0 0
T7 2980 0 0 0
T8 636050 19949 0 0
T19 12810 0 0 0
T20 2926 0 0 0
T21 6386 0 0 0
T24 0 6253 0 0
T28 17826 133 0 0
T33 0 3022 0 0
T51 0 5191 0 0
T57 0 5553 0 0
T58 0 5289 0 0
T62 0 16793 0 0
T135 0 81473 0 0
T228 0 3114 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 844464506 46031381 0 0
T3 109454 32939 0 0
T4 68644 0 0 0
T5 2708 15 0 0
T6 10994 266 0 0
T7 2980 20 0 0
T8 636050 201758 0 0
T19 12810 878 0 0
T20 2926 0 0 0
T21 6386 0 0 0
T23 0 28 0 0
T24 0 53488 0 0
T28 17826 888 0 0
T41 0 32 0 0
T51 0 52665 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2122 2122 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T8 2 2 0 0
T19 2 2 0 0
T20 2 2 0 0
T21 2 2 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 844464506 842890756 0 0
T1 3752 3442 0 0
T2 3318 3118 0 0
T3 109454 109260 0 0
T4 68644 68468 0 0
T5 2708 2548 0 0
T6 10994 10834 0 0
T8 636050 635918 0 0
T19 12810 11620 0 0
T20 2926 2608 0 0
T21 6386 6190 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2122 2122 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T8 2 2 0 0
T19 2 2 0 0
T20 2 2 0 0
T21 2 2 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 844037616 842463866 0 0
T1 3752 3442 0 0
T2 3318 3118 0 0
T3 109454 109260 0 0
T4 68644 68468 0 0
T5 2708 2548 0 0
T6 10994 10834 0 0
T8 636050 635918 0 0
T19 12810 11620 0 0
T20 2926 2608 0 0
T21 6386 6190 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 844464506 842890756 0 0
T1 3752 3442 0 0
T2 3318 3118 0 0
T3 109454 109260 0 0
T4 68644 68468 0 0
T5 2708 2548 0 0
T6 10994 10834 0 0
T8 636050 635918 0 0
T19 12810 11620 0 0
T20 2926 2608 0 0
T21 6386 6190 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
TOTAL7979100.00
ALWAYS15466100.00
ALWAYS16733100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20311100.00
ALWAYS20644100.00
ALWAYS21866100.00
ALWAYS23266100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32311100.00
ALWAYS3272929100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN39911100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN41711100.00
CONT_ASSIGN43011100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN57811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN60211100.00
CONT_ASSIGN60311100.00
CONT_ASSIGN60411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
MISSING_ELSE
167 3 3
199 1 1
203 1 1
206 1 1
207 1 1
208 1 1
209 1 1
MISSING_ELSE
218 1 1
219 1 1
220 1 1
221 1 1
222 1 1
223 1 1
MISSING_ELSE
232 1 1
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
MISSING_ELSE
279 1 1
282 1 1
283 1 1
284 1 1
289 1 1
319 1 1
323 1 1
327 1 1
328 1 1
329 1 1
330 1 1
331 1 1
333 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
342 1 1
343 1 1
MISSING_ELSE
349 1 1
350 1 1
351 1 1
MISSING_ELSE
358 1 1
359 1 1
360 1 1
361 1 1
MISSING_ELSE
367 1 1
368 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
376 1 1
377 1 1
390 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
399 1 1
400 1 1
417 1 1
430 1 1
550 1 1
578 1 1
585 1 1
602 1 1
603 1 1
604 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalCoveredPercent
Conditions1068983.96
Logical1068983.96
Non-Logical00
Event00

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T19,T8
11Not Covered

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T19,T8
11Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT3,T19,T8
1CoveredT1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT3,T19,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT3,T19,T8
1CoveredT1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T19,T8
110Not Covered
111CoveredT3,T19,T8

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT3,T19,T8
101CoveredT3,T19,T8
110Not Covered
111CoveredT3,T19,T8

 LINE       283
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT3,T8,T6
11CoveredT3,T19,T8

 LINE       284
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT2,T3,T8
10CoveredT3,T19,T8
11CoveredT3,T19,T8

 LINE       319
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T19,T8

 LINE       319
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T19,T8

 LINE       323
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT3,T19,T8
10CoveredT1,T2,T3
11CoveredT3,T8,T24

 LINE       338
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T8,T6
11CoveredT2,T3,T8

 LINE       340
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT20,T8,T6
10CoveredT22,T25,T80
11CoveredT1,T8,T6

 LINE       390
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       390
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       390
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT3,T19,T8
10CoveredT1,T2,T3
11Not Covered

 LINE       390
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       394
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T19,T8

 LINE       395
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T19,T8

 LINE       396
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T19,T8

 LINE       397
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T19,T8

 LINE       398
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T8,T6
11CoveredT2,T3,T8

 LINE       399
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T20,T8
10CoveredT2,T3,T8
11CoveredT1,T8,T6

 LINE       400
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT2,T4,T12
10CoveredT1,T2,T3
11CoveredT22,T25,T80

 LINE       400
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T56,T63
10CoveredT2,T4,T12

 LINE       430
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       430
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT3,T19,T8
10Not Covered
11Not Covered

 LINE       430
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T19,T8

 LINE       433
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T8,T6
11CoveredT2,T3,T19

 LINE       433
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T19,T8
10CoveredT1,T2,T3

 LINE       433
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       550
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T8,T41

 LINE       556
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T19,T8
10CoveredT1,T8,T41

 LINE       556
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T19,T8
10CoveredT1,T8,T41

 LINE       556
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T8,T41

 LINE       578
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T29
10CoveredT17,T18,T29

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 343 Covered T16
StCtrlProg 341 Covered T16
StCtrlRead 339 Covered T16
StDisable 337 Covered T16
StIdle 351 Covered T16


transitionsLine No.CoveredTests
StCtrl->StIdle 371 Covered T16
StCtrlProg->StIdle 361 Covered T16
StCtrlRead->StIdle 351 Covered T16
StIdle->StCtrl 343 Covered T16
StIdle->StCtrlProg 341 Covered T16
StIdle->StCtrlRead 339 Covered T16
StIdle->StDisable 337 Covered T16



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 319 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 396 2 2 100.00
TERNARY 397 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 433 2 1 50.00
TERNARY 556 2 2 100.00
IF 154 4 4 100.00
IF 167 2 2 100.00
IF 206 3 3 100.00
IF 218 4 4 100.00
IF 232 4 4 100.00
CASE 333 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 319 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T3,T19,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T19,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T19,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 396 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T19,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 397 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T19,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T8,T41
0 Covered T1,T2,T3


LineNo. Expression -1-: 433 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 556 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T8,T41
0 Covered T1,T2,T3


LineNo. Expression -1-: 154 if ((!rst_ni)) -2-: 156 if (ctrl_rsp_vld) -3-: 158 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T3,T8,T24
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 167 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 206 if ((!rst_ni)) -2-: 208 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T15
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 218 if ((!rst_ni)) -2-: 220 if ((host_outstanding == '0)) -3-: 222 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T9,T15
0 0 0 Covered T3,T19,T8


LineNo. Expression -1-: 232 if ((!rst_ni)) -2-: 234 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 236 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T9,T15
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 333 case (state_q) -2-: 336 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 338 if ((ctrl_gnt && rd_i)) -4-: 340 if ((ctrl_gnt && prog_i)) -5-: 342 if (ctrl_gnt) -6-: 349 if (rd_stage_data_valid) -7-: 359 if (prog_ack) -8-: 369 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T12,T13,T14
StIdle 0 1 - - - - - Covered T2,T3,T8
StIdle 0 0 1 - - - - Covered T1,T8,T6
StIdle 0 0 0 1 - - - Covered T22,T25,T80
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T2,T3,T8
StCtrlRead - - - - 0 - - Covered T2,T3,T8
StCtrlProg - - - - - 1 - Covered T1,T8,T6
StCtrlProg - - - - - 0 - Covered T1,T8,T6
StCtrl - - - - - - 1 Covered T22,T25,T80
StCtrl - - - - - - 0 Covered T22,T25,T80
StDisable - - - - - - - Covered T12,T13,T14
default - - - - - - - Covered T17,T18,T9


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 422232253 2116643 0 0
CtrlPrio_A 422232253 2116643 0 0
HostTransIdleChk_A 422232253 22575597 0 0
NoRemainder_A 1061 1061 0 0
OneHotReqs_A 422232253 421445378 0 0
Pow2Multiple_A 1061 1061 0 0
RdTxnCheck_A 422018808 421231933 0 0
u_state_regs_A 422232253 421445378 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422232253 2116643 0 0
T3 54727 181 0 0
T4 34322 0 0 0
T5 1354 0 0 0
T6 5497 0 0 0
T7 1490 0 0 0
T8 318025 10074 0 0
T19 6405 0 0 0
T20 1463 0 0 0
T21 3193 0 0 0
T24 0 3742 0 0
T28 8913 0 0 0
T33 0 1210 0 0
T51 0 2583 0 0
T57 0 2079 0 0
T58 0 1473 0 0
T62 0 6638 0 0
T135 0 52530 0 0
T228 0 3114 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422232253 2116643 0 0
T3 54727 181 0 0
T4 34322 0 0 0
T5 1354 0 0 0
T6 5497 0 0 0
T7 1490 0 0 0
T8 318025 10074 0 0
T19 6405 0 0 0
T20 1463 0 0 0
T21 3193 0 0 0
T24 0 3742 0 0
T28 8913 0 0 0
T33 0 1210 0 0
T51 0 2583 0 0
T57 0 2079 0 0
T58 0 1473 0 0
T62 0 6638 0 0
T135 0 52530 0 0
T228 0 3114 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422232253 22575597 0 0
T3 54727 16283 0 0
T4 34322 0 0 0
T5 1354 0 0 0
T6 5497 134 0 0
T7 1490 6 0 0
T8 318025 115341 0 0
T19 6405 528 0 0
T20 1463 0 0 0
T21 3193 0 0 0
T23 0 12 0 0
T24 0 28779 0 0
T28 8913 454 0 0
T41 0 32 0 0
T51 0 27314 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422232253 421445378 0 0
T1 1876 1721 0 0
T2 1659 1559 0 0
T3 54727 54630 0 0
T4 34322 34234 0 0
T5 1354 1274 0 0
T6 5497 5417 0 0
T8 318025 317959 0 0
T19 6405 5810 0 0
T20 1463 1304 0 0
T21 3193 3095 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422018808 421231933 0 0
T1 1876 1721 0 0
T2 1659 1559 0 0
T3 54727 54630 0 0
T4 34322 34234 0 0
T5 1354 1274 0 0
T6 5497 5417 0 0
T8 318025 317959 0 0
T19 6405 5810 0 0
T20 1463 1304 0 0
T21 3193 3095 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422232253 421445378 0 0
T1 1876 1721 0 0
T2 1659 1559 0 0
T3 54727 54630 0 0
T4 34322 34234 0 0
T5 1354 1274 0 0
T6 5497 5417 0 0
T8 318025 317959 0 0
T19 6405 5810 0 0
T20 1463 1304 0 0
T21 3193 3095 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
TOTAL7979100.00
ALWAYS15466100.00
ALWAYS16733100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20311100.00
ALWAYS20644100.00
ALWAYS21866100.00
ALWAYS23266100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32311100.00
ALWAYS3272929100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN39911100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN41711100.00
CONT_ASSIGN43011100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN57811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN60211100.00
CONT_ASSIGN60311100.00
CONT_ASSIGN60411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
MISSING_ELSE
167 3 3
199 1 1
203 1 1
206 1 1
207 1 1
208 1 1
209 1 1
MISSING_ELSE
218 1 1
219 1 1
220 1 1
221 1 1
222 1 1
223 1 1
MISSING_ELSE
232 1 1
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
MISSING_ELSE
279 1 1
282 1 1
283 1 1
284 1 1
289 1 1
319 1 1
323 1 1
327 1 1
328 1 1
329 1 1
330 1 1
331 1 1
333 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
342 1 1
343 1 1
MISSING_ELSE
349 1 1
350 1 1
351 1 1
MISSING_ELSE
358 1 1
359 1 1
360 1 1
361 1 1
MISSING_ELSE
367 1 1
368 1 1
369 1 1
370 1 1
371 1 1
MISSING_ELSE
376 1 1
377 1 1
390 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
399 1 1
400 1 1
417 1 1
430 1 1
550 1 1
578 1 1
585 1 1
602 1 1
603 1 1
604 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalCoveredPercent
Conditions1069791.51
Logical1069791.51
Non-Logical00
Event00

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T19
11CoveredT23,T90,T9

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T19
11Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT23,T90,T9

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT3,T5,T19
1CoveredT1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT3,T5,T19
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT3,T5,T19
1CoveredT1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T5,T19
110Not Covered
111CoveredT3,T5,T19

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT3,T5,T19
101CoveredT3,T5,T19
110CoveredT7,T108,T132
111CoveredT3,T5,T19

 LINE       283
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT3,T8,T6
11CoveredT3,T5,T19

 LINE       284
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T19
11CoveredT3,T5,T19

 LINE       319
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       319
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT143,T144,T145
10CoveredT1,T2,T3
11CoveredT3,T5,T19

 LINE       323
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT3,T5,T19
10CoveredT1,T2,T3
11CoveredT3,T8,T28

 LINE       338
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT2,T3,T8
10CoveredT2,T4,T20
11CoveredT1,T2,T3

 LINE       340
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T8,T6
10CoveredT2,T4,T12
11CoveredT20,T8,T6

 LINE       390
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T108,T132
10CoveredT227

 LINE       390
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT227

 LINE       390
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT3,T5,T19
10CoveredT1,T2,T3
11CoveredT7,T108,T132

 LINE       390
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       394
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       395
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       396
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       397
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       398
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T20
11CoveredT1,T2,T3

 LINE       399
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T20,T8
10CoveredT1,T2,T3
11CoveredT20,T8,T6

 LINE       400
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT2,T4,T12
10CoveredT1,T2,T3
11CoveredT2,T4,T12

 LINE       400
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT22,T56,T63
10CoveredT2,T4,T12

 LINE       430
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       430
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT3,T5,T19
10Not Covered
11Not Covered

 LINE       430
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T19

 LINE       433
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T20
11CoveredT1,T2,T3

 LINE       433
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T5,T19
10CoveredT1,T2,T3

 LINE       433
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       550
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T8,T28

 LINE       556
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT20,T8,T28

 LINE       556
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT20,T8,T28

 LINE       556
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T8,T28

 LINE       578
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T29
10CoveredT17,T18,T29

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 343 Covered T16
StCtrlProg 341 Covered T16
StCtrlRead 339 Covered T16
StDisable 337 Covered T16
StIdle 351 Covered T16


transitionsLine No.CoveredTests
StCtrl->StIdle 371 Covered T16
StCtrlProg->StIdle 361 Covered T16
StCtrlRead->StIdle 351 Covered T16
StIdle->StCtrl 343 Covered T16
StIdle->StCtrlProg 341 Covered T16
StIdle->StCtrlRead 339 Covered T16
StIdle->StDisable 337 Covered T16



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 319 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 396 2 2 100.00
TERNARY 397 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 433 2 1 50.00
TERNARY 556 2 2 100.00
IF 154 4 4 100.00
IF 167 2 2 100.00
IF 206 3 3 100.00
IF 218 4 4 100.00
IF 232 4 4 100.00
CASE 333 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 319 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T3,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 396 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 397 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T5,T19
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T20,T8,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 433 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 556 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T20,T8,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 154 if ((!rst_ni)) -2-: 156 if (ctrl_rsp_vld) -3-: 158 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T3,T8,T28
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 167 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 206 if ((!rst_ni)) -2-: 208 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T23,T90,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 218 if ((!rst_ni)) -2-: 220 if ((host_outstanding == '0)) -3-: 222 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T9,T15
0 0 0 Covered T3,T5,T19


LineNo. Expression -1-: 232 if ((!rst_ni)) -2-: 234 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 236 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T9,T15
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 333 case (state_q) -2-: 336 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 338 if ((ctrl_gnt && rd_i)) -4-: 340 if ((ctrl_gnt && prog_i)) -5-: 342 if (ctrl_gnt) -6-: 349 if (rd_stage_data_valid) -7-: 359 if (prog_ack) -8-: 369 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T12,T13,T14
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T20,T8,T6
StIdle 0 0 0 1 - - - Covered T2,T4,T12
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T20,T8,T6
StCtrlProg - - - - - 0 - Covered T20,T8,T6
StCtrl - - - - - - 1 Covered T2,T4,T12
StCtrl - - - - - - 0 Covered T2,T4,T12
StDisable - - - - - - - Covered T12,T13,T14
default - - - - - - - Covered T17,T18,T9


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 422232253 2292122 0 0
CtrlPrio_A 422232253 2292120 0 0
HostTransIdleChk_A 422232253 23455784 0 0
NoRemainder_A 1061 1061 0 0
OneHotReqs_A 422232253 421445378 0 0
Pow2Multiple_A 1061 1061 0 0
RdTxnCheck_A 422018808 421231933 0 0
u_state_regs_A 422232253 421445378 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422232253 2292122 0 0
T3 54727 1837 0 0
T4 34322 0 0 0
T5 1354 0 0 0
T6 5497 0 0 0
T7 1490 0 0 0
T8 318025 9875 0 0
T19 6405 0 0 0
T20 1463 0 0 0
T21 3193 0 0 0
T24 0 2511 0 0
T28 8913 134 0 0
T33 0 1812 0 0
T51 0 2608 0 0
T57 0 3474 0 0
T58 0 3816 0 0
T62 0 10155 0 0
T135 0 28943 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422232253 2292120 0 0
T3 54727 1837 0 0
T4 34322 0 0 0
T5 1354 0 0 0
T6 5497 0 0 0
T7 1490 0 0 0
T8 318025 9875 0 0
T19 6405 0 0 0
T20 1463 0 0 0
T21 3193 0 0 0
T24 0 2511 0 0
T28 8913 133 0 0
T33 0 1812 0 0
T51 0 2608 0 0
T57 0 3474 0 0
T58 0 3816 0 0
T62 0 10155 0 0
T135 0 28943 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422232253 23455784 0 0
T3 54727 16656 0 0
T4 34322 0 0 0
T5 1354 15 0 0
T6 5497 132 0 0
T7 1490 14 0 0
T8 318025 86417 0 0
T19 6405 350 0 0
T20 1463 0 0 0
T21 3193 0 0 0
T23 0 16 0 0
T24 0 24709 0 0
T28 8913 434 0 0
T51 0 25351 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422232253 421445378 0 0
T1 1876 1721 0 0
T2 1659 1559 0 0
T3 54727 54630 0 0
T4 34322 34234 0 0
T5 1354 1274 0 0
T6 5497 5417 0 0
T8 318025 317959 0 0
T19 6405 5810 0 0
T20 1463 1304 0 0
T21 3193 3095 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422018808 421231933 0 0
T1 1876 1721 0 0
T2 1659 1559 0 0
T3 54727 54630 0 0
T4 34322 34234 0 0
T5 1354 1274 0 0
T6 5497 5417 0 0
T8 318025 317959 0 0
T19 6405 5810 0 0
T20 1463 1304 0 0
T21 3193 3095 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 422232253 421445378 0 0
T1 1876 1721 0 0
T2 1659 1559 0 0
T3 54727 54630 0 0
T4 34322 34234 0 0
T5 1354 1274 0 0
T6 5497 5417 0 0
T8 318025 317959 0 0
T19 6405 5810 0 0
T20 1463 1304 0 0
T21 3193 3095 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%