Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23836310	1		T1	110		T2	56967		T3	4388
full_word	7259463	1		T1	70		T2	9112		T3	403

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31095473	1		T1	180		T2	66079		T3	4791
auto[TlIntgErrCmd]	100	1		T55	7		T190	4		T225	7
auto[TlIntgErrData]	89	1		T55	4		T190	4		T225	7
auto[TlIntgErrBoth]	111	1		T55	9		T190	2		T225	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26875941	1		T1	58		T2	59261		T3	4555
auto[1]	4219832	1		T1	122		T2	6818		T3	236

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23220402	1		T1	57		T2	56077		T3	4328
auto[TlIntgErrNone]	partial	auto[1]	615636	1		T1	53		T2	890		T3	60
auto[TlIntgErrNone]	full_word	auto[0]	3655392	1		T1	1		T2	3184		T3	227
auto[TlIntgErrNone]	full_word	auto[1]	3604043	1		T1	69		T2	5928		T3	176
auto[TlIntgErrCmd]	partial	auto[0]	40	1		T55	5		T190	2		T268	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T55	2		T190	2		T225	6
auto[TlIntgErrCmd]	full_word	auto[0]	9	1		T249	1		T266	1		T381	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T225	1		T277	1		T269	3
auto[TlIntgErrData]	partial	auto[0]	47	1		T55	3		T190	2		T225	2
auto[TlIntgErrData]	partial	auto[1]	32	1		T190	2		T225	5		T249	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T55	1		T382	1		T380	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T249	1		T277	1		T265	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1		T55	3		T190	2		T225	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T55	6		T225	4		T249	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T225	1		T277	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T294	1		T379	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23929	1		T55	16		T189	132		T190	8
full_word	4207543	1		T3	16		T4	10		T5	16459

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4231191	1		T3	16		T4	10		T5	16459
auto[TlIntgErrCmd]	90	1		T55	7		T190	3		T225	6
auto[TlIntgErrData]	99	1		T55	9		T190	4		T225	9
auto[TlIntgErrBoth]	92	1		T55	4		T190	2		T225	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4200353	1		T3	16		T4	10		T5	16459
auto[1]	31119	1		T55	12		T189	164		T190	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1478	1		T189	10		T223	5		T224	14
auto[TlIntgErrNone]	partial	auto[1]	22200	1		T189	122		T223	38		T224	323
auto[TlIntgErrNone]	full_word	auto[0]	4198767	1		T3	16		T4	10		T5	16459
auto[TlIntgErrNone]	full_word	auto[1]	8746	1		T189	42		T223	9		T224	199
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T55	3		T190	1		T225	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T55	4		T190	2		T225	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T383	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T273	1		T274	1		T267	1
auto[TlIntgErrData]	partial	auto[0]	37	1		T55	2		T190	1		T225	7
auto[TlIntgErrData]	partial	auto[1]	44	1		T55	4		T190	2		T225	2
auto[TlIntgErrData]	full_word	auto[0]	9	1		T55	2		T265	1		T270	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T55	1		T190	1		T266	1
auto[TlIntgErrBoth]	partial	auto[0]	25	1		T55	1		T190	2		T249	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T55	2		T225	3		T249	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T277	1		T266	1		T274	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T55	1		T265	1		T269	1