Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1447268640	1443985128	0	0
CheckNGreaterZero_A	3940	3940	0	0
GntImpliesReady_A	1447268640	409384705	0	0
GntImpliesValid_A	1447268640	409384705	0	0
GrantKnown_A	1447268640	1443985128	0	0
IdxKnown_A	1447268640	1443985128	0	0
IndexIsCorrect_A	1447268640	409384705	0	0
NoReadyValidNoGrant_A	1447268640	162227974	0	0
Priority_A	1447268640	433531645	0	0
ReadyAndValidImplyGrant_A	1447268640	409384705	0	0
ReqAndReadyImplyGrant_A	1447268640	409384705	0	0
ReqImpliesValid_A	1447268640	433531645	0	0
ValidKnown_A	1447268640	1443985128	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	1443985128	0	0
T1	12904	12624	0	0
T2	593400	558844	0	0
T3	41408	40788	0	0
T4	12044	11568	0	0
T5	404732	404168	0	0
T6	12288	12008	0	0
T7	3367572	3366944	0	0
T18	924760	882424	0	0
T19	2113372	2113340	0	0
T20	5732	5396	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3940	3940	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	409384705	0	0
T1	6452	64	0	0
T2	296700	184080	0	0
T3	41408	15632	0	0
T4	12044	804	0	0
T5	404732	65154	0	0
T6	12288	1090	0	0
T7	3367572	60466	0	0
T8	0	202678	0	0
T18	924760	200764	0	0
T19	2113372	1048534	0	0
T20	5732	64	0	0
T32	0	444	0	0
T36	417266	47418	0	0
T41	0	189504	0	0
T52	2640	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	409384705	0	0
T1	6452	64	0	0
T2	296700	184080	0	0
T3	41408	15632	0	0
T4	12044	804	0	0
T5	404732	65154	0	0
T6	12288	1090	0	0
T7	3367572	60466	0	0
T8	0	202678	0	0
T18	924760	200764	0	0
T19	2113372	1048534	0	0
T20	5732	64	0	0
T32	0	444	0	0
T36	417266	47418	0	0
T41	0	189504	0	0
T52	2640	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	1443985128	0	0
T1	12904	12624	0	0
T2	593400	558844	0	0
T3	41408	40788	0	0
T4	12044	11568	0	0
T5	404732	404168	0	0
T6	12288	12008	0	0
T7	3367572	3366944	0	0
T18	924760	882424	0	0
T19	2113372	2113340	0	0
T20	5732	5396	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	1443985128	0	0
T1	12904	12624	0	0
T2	593400	558844	0	0
T3	41408	40788	0	0
T4	12044	11568	0	0
T5	404732	404168	0	0
T6	12288	12008	0	0
T7	3367572	3366944	0	0
T18	924760	882424	0	0
T19	2113372	2113340	0	0
T20	5732	5396	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	409384705	0	0
T1	6452	64	0	0
T2	296700	184080	0	0
T3	41408	15632	0	0
T4	12044	804	0	0
T5	404732	65154	0	0
T6	12288	1090	0	0
T7	3367572	60466	0	0
T8	0	202678	0	0
T18	924760	200764	0	0
T19	2113372	1048534	0	0
T20	5732	64	0	0
T32	0	444	0	0
T36	417266	47418	0	0
T41	0	189504	0	0
T52	2640	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	162227974	0	0
T1	6452	256	0	0
T2	296700	44360	0	0
T3	41408	1486	0	0
T4	12044	840	0	0
T5	404732	96046	0	0
T6	12288	292	0	0
T7	3367572	1987956	0	0
T8	0	157308	0	0
T18	924760	51096	0	0
T19	2113372	3392	0	0
T20	5732	256	0	0
T36	417266	3768	0	0
T45	0	276	0	0
T52	2640	0	0	0
T59	0	396	0	0
T67	0	3552	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	433531645	0	0
T1	6452	64	0	0
T2	296700	184080	0	0
T3	41408	15632	0	0
T4	12044	804	0	0
T5	404732	76792	0	0
T6	12288	1090	0	0
T7	3367572	525458	0	0
T8	0	244176	0	0
T18	924760	200764	0	0
T19	2113372	1048534	0	0
T20	5732	64	0	0
T32	0	444	0	0
T36	417266	47418	0	0
T41	0	189504	0	0
T52	2640	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	409384705	0	0
T1	6452	64	0	0
T2	296700	184080	0	0
T3	41408	15632	0	0
T4	12044	804	0	0
T5	404732	65154	0	0
T6	12288	1090	0	0
T7	3367572	60466	0	0
T8	0	202678	0	0
T18	924760	200764	0	0
T19	2113372	1048534	0	0
T20	5732	64	0	0
T32	0	444	0	0
T36	417266	47418	0	0
T41	0	189504	0	0
T52	2640	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	409384705	0	0
T1	6452	64	0	0
T2	296700	184080	0	0
T3	41408	15632	0	0
T4	12044	804	0	0
T5	404732	65154	0	0
T6	12288	1090	0	0
T7	3367572	60466	0	0
T8	0	202678	0	0
T18	924760	200764	0	0
T19	2113372	1048534	0	0
T20	5732	64	0	0
T32	0	444	0	0
T36	417266	47418	0	0
T41	0	189504	0	0
T52	2640	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	433531645	0	0
T1	6452	64	0	0
T2	296700	184080	0	0
T3	41408	15632	0	0
T4	12044	804	0	0
T5	404732	76792	0	0
T6	12288	1090	0	0
T7	3367572	525458	0	0
T8	0	244176	0	0
T18	924760	200764	0	0
T19	2113372	1048534	0	0
T20	5732	64	0	0
T32	0	444	0	0
T36	417266	47418	0	0
T41	0	189504	0	0
T52	2640	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447268640	1443985128	0	0
T1	12904	12624	0	0
T2	593400	558844	0	0
T3	41408	40788	0	0
T4	12044	11568	0	0
T5	404732	404168	0	0
T6	12288	12008	0	0
T7	3367572	3366944	0	0
T18	924760	882424	0	0
T19	2113372	2113340	0	0
T20	5732	5396	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361817160	360996282	0	0
CheckNGreaterZero_A	985	985	0	0
GntImpliesReady_A	361817160	110712092	0	0
GntImpliesValid_A	361817160	110712092	0	0
GrantKnown_A	361817160	360996282	0	0
IdxKnown_A	361817160	360996282	0	0
IndexIsCorrect_A	361817160	110712092	0	0
NoReadyValidNoGrant_A	361817160	41814781	0	0
Priority_A	361817160	116687659	0	0
ReadyAndValidImplyGrant_A	361817160	110712092	0	0
ReqAndReadyImplyGrant_A	361817160	110712092	0	0
ReqImpliesValid_A	361817160	116687659	0	0
ValidKnown_A	361817160	360996282	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	985	985	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	110712092	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	16107	0	0
T6	3072	441	0	0
T7	841893	15182	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	110712092	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	16107	0	0
T6	3072	441	0	0
T7	841893	15182	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	110712092	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	16107	0	0
T6	3072	441	0	0
T7	841893	15182	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	41814781	0	0
T1	3226	128	0	0
T2	148350	22180	0	0
T3	10352	256	0	0
T4	3011	256	0	0
T5	101183	25071	0	0
T6	3072	141	0	0
T7	841893	497636	0	0
T18	231190	25548	0	0
T19	528343	1696	0	0
T20	1433	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	116687659	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	19121	0	0
T6	3072	441	0	0
T7	841893	136362	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	110712092	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	16107	0	0
T6	3072	441	0	0
T7	841893	15182	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	110712092	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	16107	0	0
T6	3072	441	0	0
T7	841893	15182	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	116687659	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	19121	0	0
T6	3072	441	0	0
T7	841893	136362	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361817160	360996282	0	0
CheckNGreaterZero_A	985	985	0	0
GntImpliesReady_A	361817160	110694303	0	0
GntImpliesValid_A	361817160	110694303	0	0
GrantKnown_A	361817160	360996282	0	0
IdxKnown_A	361817160	360996282	0	0
IndexIsCorrect_A	361817160	110694303	0	0
NoReadyValidNoGrant_A	361817160	41814781	0	0
Priority_A	361817160	116669870	0	0
ReadyAndValidImplyGrant_A	361817160	110694303	0	0
ReqAndReadyImplyGrant_A	361817160	110694303	0	0
ReqImpliesValid_A	361817160	116669870	0	0
ValidKnown_A	361817160	360996282	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	985	985	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	110694303	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	16107	0	0
T6	3072	441	0	0
T7	841893	15182	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	110694303	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	16107	0	0
T6	3072	441	0	0
T7	841893	15182	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	110694303	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	16107	0	0
T6	3072	441	0	0
T7	841893	15182	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	41814781	0	0
T1	3226	128	0	0
T2	148350	22180	0	0
T3	10352	256	0	0
T4	3011	256	0	0
T5	101183	25071	0	0
T6	3072	141	0	0
T7	841893	497636	0	0
T18	231190	25548	0	0
T19	528343	1696	0	0
T20	1433	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	116669870	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	19121	0	0
T6	3072	441	0	0
T7	841893	136362	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	110694303	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	16107	0	0
T6	3072	441	0	0
T7	841893	15182	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	110694303	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	16107	0	0
T6	3072	441	0	0
T7	841893	15182	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	116669870	0	0
T1	3226	32	0	0
T2	148350	92040	0	0
T3	10352	7604	0	0
T4	3011	64	0	0
T5	101183	19121	0	0
T6	3072	441	0	0
T7	841893	136362	0	0
T18	231190	100382	0	0
T19	528343	349071	0	0
T20	1433	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361817160	360996282	0	0
CheckNGreaterZero_A	985	985	0	0
GntImpliesReady_A	361817160	93989155	0	0
GntImpliesValid_A	361817160	93989155	0	0
GrantKnown_A	361817160	360996282	0	0
IdxKnown_A	361817160	360996282	0	0
IndexIsCorrect_A	361817160	93989155	0	0
NoReadyValidNoGrant_A	361817160	39299206	0	0
Priority_A	361817160	100087058	0	0
ReadyAndValidImplyGrant_A	361817160	93989155	0	0
ReqAndReadyImplyGrant_A	361817160	93989155	0	0
ReqImpliesValid_A	361817160	100087058	0	0
ValidKnown_A	361817160	360996282	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	985	985	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	93989155	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	16470	0	0
T6	3072	104	0	0
T7	841893	15051	0	0
T8	0	101339	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	93989155	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	16470	0	0
T6	3072	104	0	0
T7	841893	15051	0	0
T8	0	101339	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	93989155	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	16470	0	0
T6	3072	104	0	0
T7	841893	15051	0	0
T8	0	101339	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	39299206	0	0
T3	10352	487	0	0
T4	3011	164	0	0
T5	101183	22952	0	0
T6	3072	5	0	0
T7	841893	496342	0	0
T8	0	78654	0	0
T18	231190	0	0	0
T19	528343	0	0	0
T20	1433	0	0	0
T36	208633	1884	0	0
T45	0	138	0	0
T52	1320	0	0	0
T59	0	198	0	0
T67	0	1776	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	100087058	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	19275	0	0
T6	3072	104	0	0
T7	841893	126367	0	0
T8	0	122088	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	93989155	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	16470	0	0
T6	3072	104	0	0
T7	841893	15051	0	0
T8	0	101339	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	93989155	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	16470	0	0
T6	3072	104	0	0
T7	841893	15051	0	0
T8	0	101339	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	100087058	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	19275	0	0
T6	3072	104	0	0
T7	841893	126367	0	0
T8	0	122088	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361817160	360996282	0	0
CheckNGreaterZero_A	985	985	0	0
GntImpliesReady_A	361817160	93989155	0	0
GntImpliesValid_A	361817160	93989155	0	0
GrantKnown_A	361817160	360996282	0	0
IdxKnown_A	361817160	360996282	0	0
IndexIsCorrect_A	361817160	93989155	0	0
NoReadyValidNoGrant_A	361817160	39299206	0	0
Priority_A	361817160	100087058	0	0
ReadyAndValidImplyGrant_A	361817160	93989155	0	0
ReqAndReadyImplyGrant_A	361817160	93989155	0	0
ReqImpliesValid_A	361817160	100087058	0	0
ValidKnown_A	361817160	360996282	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	985	985	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	93989155	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	16470	0	0
T6	3072	104	0	0
T7	841893	15051	0	0
T8	0	101339	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	93989155	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	16470	0	0
T6	3072	104	0	0
T7	841893	15051	0	0
T8	0	101339	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	93989155	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	16470	0	0
T6	3072	104	0	0
T7	841893	15051	0	0
T8	0	101339	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	39299206	0	0
T3	10352	487	0	0
T4	3011	164	0	0
T5	101183	22952	0	0
T6	3072	5	0	0
T7	841893	496342	0	0
T8	0	78654	0	0
T18	231190	0	0	0
T19	528343	0	0	0
T20	1433	0	0	0
T36	208633	1884	0	0
T45	0	138	0	0
T52	1320	0	0	0
T59	0	198	0	0
T67	0	1776	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	100087058	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	19275	0	0
T6	3072	104	0	0
T7	841893	126367	0	0
T8	0	122088	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	93989155	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	16470	0	0
T6	3072	104	0	0
T7	841893	15051	0	0
T8	0	101339	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	93989155	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	16470	0	0
T6	3072	104	0	0
T7	841893	15051	0	0
T8	0	101339	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	100087058	0	0
T3	10352	212	0	0
T4	3011	338	0	0
T5	101183	19275	0	0
T6	3072	104	0	0
T7	841893	126367	0	0
T8	0	122088	0	0
T18	231190	0	0	0
T19	528343	175196	0	0
T20	1433	0	0	0
T32	0	222	0	0
T36	208633	23709	0	0
T41	0	94752	0	0
T52	1320	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361817160	360996282	0	0
T1	3226	3156	0	0
T2	148350	139711	0	0
T3	10352	10197	0	0
T4	3011	2892	0	0
T5	101183	101042	0	0
T6	3072	3002	0	0
T7	841893	841736	0	0
T18	231190	220606	0	0
T19	528343	528335	0	0
T20	1433	1349	0	0