Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.60 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.60 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.60 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.60 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.71 100.00 90.83 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.71 100.00 90.83 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.71 100.00 90.83 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.71 100.00 90.83 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Module : flash_phy_rd_buffers
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT84,T104,T105

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T47

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Module : flash_phy_rd_buffers
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T84,T104,T105
0 0 1 - - Covered T1,T2,T47
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd_buffers
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 2147483647 5341007 0 0
UpdateCheck_A 2147483647 5340994 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5341007 0 0
T1 12780 50 0 0
T2 857984 1152 0 0
T3 18744 74 0 0
T4 2085752 0 0 0
T5 385896 19357 0 0
T7 0 24558 0 0
T8 0 17953 0 0
T9 37032 0 0 0
T12 28600 0 0 0
T13 3147200 0 0 0
T14 6072 0 0 0
T18 10360 0 0 0
T19 222784 626 0 0
T22 0 44599 0 0
T27 0 1358 0 0
T30 0 12478 0 0
T41 0 1 0 0
T45 0 10402 0 0
T47 0 137 0 0
T48 0 1492 0 0
T73 0 35 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5340994 0 0
T1 12780 50 0 0
T2 857984 1152 0 0
T3 18744 74 0 0
T4 2085752 0 0 0
T5 385896 19357 0 0
T7 0 24558 0 0
T8 0 17953 0 0
T9 37032 0 0 0
T12 28600 0 0 0
T13 3147200 0 0 0
T14 6072 0 0 0
T18 10360 0 0 0
T19 222784 626 0 0
T22 0 44599 0 0
T27 0 1358 0 0
T30 0 12478 0 0
T41 0 1 0 0
T45 0 10402 0 0
T47 0 137 0 0
T48 0 1492 0 0
T73 0 35 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT84,T104,T105

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T47,T48

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T84,T104,T105
0 0 1 - - Covered T2,T47,T48
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 362988880 695745 0 0
UpdateCheck_A 362988880 695742 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 695745 0 0
T1 3195 13 0 0
T2 107248 272 0 0
T3 2343 19 0 0
T4 260719 0 0 0
T5 48237 2475 0 0
T7 0 3074 0 0
T8 0 2447 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 98 0 0
T22 0 5537 0 0
T47 0 36 0 0
T48 0 373 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 695742 0 0
T1 3195 13 0 0
T2 107248 272 0 0
T3 2343 19 0 0
T4 260719 0 0 0
T5 48237 2475 0 0
T7 0 3074 0 0
T8 0 2447 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 98 0 0
T22 0 5537 0 0
T47 0 36 0 0
T48 0 373 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT84,T104,T105

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T47,T48

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T84,T104,T105
0 0 1 - - Covered T2,T47,T48
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 362988880 695577 0 0
UpdateCheck_A 362988880 695572 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 695577 0 0
T1 3195 12 0 0
T2 107248 271 0 0
T3 2343 19 0 0
T4 260719 0 0 0
T5 48237 2478 0 0
T7 0 3085 0 0
T8 0 2457 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 98 0 0
T22 0 5585 0 0
T47 0 35 0 0
T48 0 373 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 695572 0 0
T1 3195 12 0 0
T2 107248 271 0 0
T3 2343 19 0 0
T4 260719 0 0 0
T5 48237 2478 0 0
T7 0 3085 0 0
T8 0 2457 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 98 0 0
T22 0 5585 0 0
T47 0 35 0 0
T48 0 373 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT84,T104,T105

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T47

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T84,T104,T105
0 0 1 - - Covered T1,T2,T47
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 362988880 695211 0 0
UpdateCheck_A 362988880 695211 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 695211 0 0
T1 3195 13 0 0
T2 107248 271 0 0
T3 2343 18 0 0
T4 260719 0 0 0
T5 48237 2459 0 0
T7 0 3083 0 0
T8 0 2449 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 97 0 0
T22 0 5579 0 0
T47 0 37 0 0
T48 0 373 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 695211 0 0
T1 3195 13 0 0
T2 107248 271 0 0
T3 2343 18 0 0
T4 260719 0 0 0
T5 48237 2459 0 0
T7 0 3083 0 0
T8 0 2449 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 97 0 0
T22 0 5579 0 0
T47 0 37 0 0
T48 0 373 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT84,T104,T91

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T47,T48

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T84,T104,T91
0 0 1 - - Covered T2,T47,T48
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 362988880 695181 0 0
UpdateCheck_A 362988880 695181 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 695181 0 0
T1 3195 12 0 0
T2 107248 271 0 0
T3 2343 18 0 0
T4 260719 0 0 0
T5 48237 2470 0 0
T7 0 3079 0 0
T8 0 2452 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 97 0 0
T22 0 5577 0 0
T47 0 29 0 0
T48 0 373 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 695181 0 0
T1 3195 12 0 0
T2 107248 271 0 0
T3 2343 18 0 0
T4 260719 0 0 0
T5 48237 2470 0 0
T7 0 3079 0 0
T8 0 2452 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T18 1295 0 0 0
T19 27848 97 0 0
T22 0 5577 0 0
T47 0 29 0 0
T48 0 373 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT2,T5,T19
10CoveredT1,T2,T3
11CoveredT84,T91,T93

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T19

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT23,T24,T75

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T5,T19

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T5,T19

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T84,T91,T93
0 0 1 - - Covered T23,T24,T75
0 0 0 1 - Covered T2,T5,T19
0 0 0 0 1 Covered T2,T5,T19
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 362988880 640116 0 0
UpdateCheck_A 362988880 640113 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 640116 0 0
T2 107248 17 0 0
T3 2343 0 0 0
T4 260719 0 0 0
T5 48237 2370 0 0
T7 0 3059 0 0
T8 0 2030 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T14 1518 0 0 0
T18 1295 0 0 0
T19 27848 59 0 0
T22 0 5555 0 0
T27 0 340 0 0
T30 0 3120 0 0
T41 0 1 0 0
T45 0 2600 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 640113 0 0
T2 107248 17 0 0
T3 2343 0 0 0
T4 260719 0 0 0
T5 48237 2370 0 0
T7 0 3059 0 0
T8 0 2030 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T14 1518 0 0 0
T18 1295 0 0 0
T19 27848 59 0 0
T22 0 5555 0 0
T27 0 340 0 0
T30 0 3120 0 0
T41 0 1 0 0
T45 0 2600 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT2,T5,T19
10CoveredT1,T2,T3
11CoveredT84,T91,T93

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T19

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT23,T24,T26

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T5,T19

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T5,T19

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T84,T91,T93
0 0 1 - - Covered T23,T24,T26
0 0 0 1 - Covered T2,T5,T19
0 0 0 0 1 Covered T2,T5,T19
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 362988880 639872 0 0
UpdateCheck_A 362988880 639871 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 639872 0 0
T2 107248 17 0 0
T3 2343 0 0 0
T4 260719 0 0 0
T5 48237 2371 0 0
T7 0 3057 0 0
T8 0 2047 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T14 1518 0 0 0
T18 1295 0 0 0
T19 27848 59 0 0
T22 0 5583 0 0
T27 0 340 0 0
T30 0 3122 0 0
T45 0 2603 0 0
T73 0 12 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 639871 0 0
T2 107248 17 0 0
T3 2343 0 0 0
T4 260719 0 0 0
T5 48237 2371 0 0
T7 0 3057 0 0
T8 0 2047 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T14 1518 0 0 0
T18 1295 0 0 0
T19 27848 59 0 0
T22 0 5583 0 0
T27 0 340 0 0
T30 0 3122 0 0
T45 0 2603 0 0
T73 0 12 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT2,T5,T19
10CoveredT1,T2,T3
11CoveredT84,T91,T93

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T19

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT23,T24,T50

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T5,T19

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T5,T19

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T84,T91,T93
0 0 1 - - Covered T23,T24,T50
0 0 0 1 - Covered T2,T5,T19
0 0 0 0 1 Covered T2,T5,T19
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 362988880 639908 0 0
UpdateCheck_A 362988880 639907 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 639908 0 0
T2 107248 17 0 0
T3 2343 0 0 0
T4 260719 0 0 0
T5 48237 2369 0 0
T7 0 3061 0 0
T8 0 2039 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T14 1518 0 0 0
T18 1295 0 0 0
T19 27848 59 0 0
T22 0 5596 0 0
T27 0 339 0 0
T30 0 3118 0 0
T45 0 2592 0 0
T73 0 12 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 639907 0 0
T2 107248 17 0 0
T3 2343 0 0 0
T4 260719 0 0 0
T5 48237 2369 0 0
T7 0 3061 0 0
T8 0 2039 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T14 1518 0 0 0
T18 1295 0 0 0
T19 27848 59 0 0
T22 0 5596 0 0
T27 0 339 0 0
T30 0 3118 0 0
T45 0 2592 0 0
T73 0 12 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT2,T5,T19
10CoveredT1,T2,T3
11CoveredT84,T91,T93

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T19

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT23,T24,T76

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T5,T19

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T5,T19

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T84,T91,T93
0 0 1 - - Covered T23,T24,T76
0 0 0 1 - Covered T2,T5,T19
0 0 0 0 1 Covered T2,T5,T19
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 362988880 639397 0 0
UpdateCheck_A 362988880 639397 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 639397 0 0
T2 107248 16 0 0
T3 2343 0 0 0
T4 260719 0 0 0
T5 48237 2365 0 0
T7 0 3060 0 0
T8 0 2032 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T14 1518 0 0 0
T18 1295 0 0 0
T19 27848 59 0 0
T22 0 5587 0 0
T27 0 339 0 0
T30 0 3118 0 0
T45 0 2607 0 0
T73 0 11 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 362988880 639397 0 0
T2 107248 16 0 0
T3 2343 0 0 0
T4 260719 0 0 0
T5 48237 2365 0 0
T7 0 3060 0 0
T8 0 2032 0 0
T9 4629 0 0 0
T12 3575 0 0 0
T13 393400 0 0 0
T14 1518 0 0 0
T18 1295 0 0 0
T19 27848 59 0 0
T22 0 5587 0 0
T27 0 339 0 0
T30 0 3118 0 0
T45 0 2607 0 0
T73 0 11 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%