Line Coverage for Module :
flash_phy_rd
| Line No. | Total | Covered | Percent |
TOTAL | | 118 | 118 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 185 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
ALWAYS | 256 | 4 | 4 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 296 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 320 | 1 | 1 | 100.00 |
CONT_ASSIGN | 325 | 1 | 1 | 100.00 |
ALWAYS | 354 | 12 | 12 | 100.00 |
CONT_ASSIGN | 371 | 1 | 1 | 100.00 |
CONT_ASSIGN | 376 | 1 | 1 | 100.00 |
CONT_ASSIGN | 387 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
CONT_ASSIGN | 398 | 1 | 1 | 100.00 |
CONT_ASSIGN | 416 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 430 | 1 | 1 | 100.00 |
CONT_ASSIGN | 433 | 1 | 1 | 100.00 |
CONT_ASSIGN | 439 | 1 | 1 | 100.00 |
CONT_ASSIGN | 444 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 469 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 500 | 1 | 1 | 100.00 |
CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
CONT_ASSIGN | 507 | 1 | 1 | 100.00 |
CONT_ASSIGN | 508 | 1 | 1 | 100.00 |
ALWAYS | 562 | 5 | 5 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 576 | 1 | 1 | 100.00 |
CONT_ASSIGN | 579 | 1 | 1 | 100.00 |
CONT_ASSIGN | 586 | 1 | 1 | 100.00 |
CONT_ASSIGN | 590 | 1 | 1 | 100.00 |
CONT_ASSIGN | 598 | 1 | 1 | 100.00 |
CONT_ASSIGN | 615 | 1 | 1 | 100.00 |
CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
ALWAYS | 631 | 6 | 6 | 100.00 |
CONT_ASSIGN | 642 | 1 | 1 | 100.00 |
CONT_ASSIGN | 654 | 1 | 1 | 100.00 |
CONT_ASSIGN | 655 | 1 | 1 | 100.00 |
CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
CONT_ASSIGN | 688 | 1 | 1 | 100.00 |
CONT_ASSIGN | 691 | 1 | 1 | 100.00 |
CONT_ASSIGN | 695 | 1 | 1 | 100.00 |
CONT_ASSIGN | 698 | 1 | 1 | 100.00 |
CONT_ASSIGN | 701 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
136 |
1 |
1 |
139 |
4 |
4 |
140 |
4 |
4 |
145 |
4 |
4 |
151 |
1 |
1 |
153 |
3 |
3 |
185 |
1 |
1 |
192 |
4 |
4 |
193 |
4 |
4 |
195 |
4 |
4 |
211 |
4 |
4 |
217 |
4 |
4 |
221 |
4 |
4 |
228 |
1 |
1 |
231 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
259 |
1 |
1 |
|
|
|
MISSING_ELSE |
289 |
1 |
1 |
296 |
1 |
1 |
299 |
1 |
1 |
302 |
1 |
1 |
320 |
1 |
1 |
325 |
1 |
1 |
354 |
1 |
1 |
355 |
1 |
1 |
356 |
1 |
1 |
357 |
1 |
1 |
358 |
1 |
1 |
359 |
1 |
1 |
360 |
1 |
1 |
361 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
365 |
1 |
1 |
366 |
1 |
1 |
|
|
|
MISSING_ELSE |
371 |
1 |
1 |
376 |
1 |
1 |
387 |
1 |
1 |
393 |
1 |
1 |
398 |
1 |
1 |
416 |
1 |
1 |
420 |
1 |
1 |
430 |
1 |
1 |
433 |
1 |
1 |
439 |
1 |
1 |
444 |
1 |
1 |
447 |
1 |
1 |
469 |
1 |
1 |
475 |
1 |
1 |
479 |
1 |
1 |
483 |
1 |
1 |
500 |
1 |
1 |
504 |
1 |
1 |
507 |
1 |
1 |
508 |
1 |
1 |
562 |
1 |
1 |
563 |
1 |
1 |
564 |
1 |
1 |
565 |
1 |
1 |
566 |
1 |
1 |
567 |
|
unreachable |
|
|
|
MISSING_ELSE |
572 |
1 |
1 |
576 |
1 |
1 |
579 |
1 |
1 |
586 |
1 |
1 |
590 |
1 |
1 |
598 |
1 |
1 |
615 |
1 |
1 |
620 |
1 |
1 |
625 |
4 |
4 |
631 |
1 |
1 |
632 |
1 |
1 |
633 |
1 |
1 |
634 |
1 |
1 |
635 |
1 |
1 |
636 |
1 |
1 |
|
|
|
MISSING_ELSE |
642 |
1 |
1 |
654 |
1 |
1 |
655 |
1 |
1 |
676 |
1 |
1 |
688 |
1 |
1 |
691 |
1 |
1 |
695 |
1 |
1 |
698 |
1 |
1 |
701 |
1 |
1 |
Cond Coverage for Module :
flash_phy_rd
| Total | Covered | Percent |
Conditions | 436 | 398 | 91.28 |
Logical | 436 | 398 | 91.28 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 139
EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[0].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[1].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[2].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[3].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[0].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T45,T179 |
1 | 1 | 1 | Covered | T22,T45,T46 |
LINE 145
SUB-EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T22,T45,T131 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[1].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T22,T45,T131 |
LINE 145
SUB-EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T22,T49,T45 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[2].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T179 |
1 | 1 | 1 | Covered | T22,T49,T45 |
LINE 145
SUB-EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[3].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T22,T45,T46 |
LINE 145
SUB-EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 153
EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
-------1------ ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 153
EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 153
EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 166
EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 166
SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
-----------1---------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 166
EXPRESSION (req_o & no_match)
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 185
EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[0].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[1].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[2].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[3].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[0].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[1].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[2].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[3].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[0] | buf_wip[0]) &
4 (read_buf[0].addr == flash_word_addr) &
5 ((~read_buf[0].err)) &
6 gen_buf_match[0].part_match &
7 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T47,T48,T33 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T45,T46,T125 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T5,T7,T46 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[1] | buf_wip[1]) &
4 (read_buf[1].addr == flash_word_addr) &
5 ((~read_buf[1].err)) &
6 gen_buf_match[1].part_match &
7 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Covered | T118 |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T47,T48,T33 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T45,T46,T180 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T22,T45,T46 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[2] | buf_wip[2]) &
4 (read_buf[2].addr == flash_word_addr) &
5 ((~read_buf[2].err)) &
6 gen_buf_match[2].part_match &
7 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T1,T47,T48 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T22,T46,T180 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T46,T124,T125 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[3] | buf_wip[3]) &
4 (read_buf[3].addr == flash_word_addr) &
5 ((~read_buf[3].err)) &
6 gen_buf_match[3].part_match &
7 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Covered | T91 |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T47,T48,T33 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T45,T46,T180 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Covered | T181 |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T5,T46,T178 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T7,T46 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T22,T45 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T46,T124 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T7,T46 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[0].part_match &
3 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T7,T22 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[1].part_match &
3 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T22,T45 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[2].part_match &
3 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T7,T22 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[3].part_match &
3 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T7,T22 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 221
EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T47,T48 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T47,T48 |
0 | 1 | 0 | Covered | T2,T13,T9 |
1 | 0 | 0 | Covered | T2,T23,T24 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T2,T13,T9 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T12,T13 |
1 | 1 | Covered | T13,T47,T48 |
LINE 221
EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T47,T48 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T47,T48 |
0 | 1 | 0 | Covered | T2,T13,T9 |
1 | 0 | 0 | Covered | T2,T23,T24 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T2,T13,T9 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T12,T13 |
1 | 1 | Covered | T13,T47,T48 |
LINE 221
EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T13 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T47 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T47,T48 |
0 | 1 | 0 | Covered | T1,T2,T13 |
1 | 0 | 0 | Covered | T2,T23,T24 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T13 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T12,T13 |
1 | 1 | Covered | T13,T47,T48 |
LINE 221
EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T47,T48 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T47,T48 |
0 | 1 | 0 | Covered | T2,T13,T9 |
1 | 0 | 0 | Covered | T2,T23,T24 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T2,T13,T9 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T12,T13 |
1 | 1 | Covered | T13,T47,T48 |
LINE 231
EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (rdy_o & alloc[0])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (rdy_o & alloc[1])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T30,T45 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (rdy_o & alloc[2])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T22,T30 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (rdy_o & alloc[3])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T22 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 289
EXPRESSION (rd_busy & done_i)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 296
EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 299
EXPRESSION (req_i && rdy_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T7,T8 |
1 | 1 | Covered | T1,T2,T3 |
LINE 302
EXPRESSION (rsp_fifo_vld & data_valid_o)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION (req_o && ack_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T22,T46,T39 |
1 | 1 | Covered | T1,T2,T3 |
LINE 371
EXPRESSION (((~rd_busy)) | rd_done)
------1----- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 376
EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T22 |
1 | 0 | Covered | T15,T16,T17 |
1 | 1 | Covered | T1,T2,T3 |
LINE 387
EXPRESSION (buf_en_q == buf_en_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 393
EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change)
--------------------------------1------------------------------- -----------2----------- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 393
SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 393
SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
--1-- ----2---- ------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T22 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 398
EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match)
--1-- --------2------- ----3---- ------4------ ----5---
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | Covered | T5,T7,T8 |
1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 416
EXPRESSION (rd_done && rd_attrs.ecc)
---1--- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T5,T47 |
1 | 1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
---1--- ------------------------2------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T13 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T47 |
LINE 420
SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T13 |
LINE 430
EXPRESSION (valid_ecc & ecc_multi_err)
----1---- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T47,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T22,T49,T45 |
LINE 439
EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T19 |
LINE 439
SUB-EXPRESSION (data_err | ecc_single_err_o)
----1--- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T19 |
1 | 0 | Covered | T22,T49,T45 |
LINE 444
EXPRESSION (valid_ecc & ecc_single_err)
----1---- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T19 |
LINE 469
EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T15,T16,T17 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 475
EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 475
SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 479
EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
---1--- ---------2--------- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T19,T47,T41 |
1 | 1 | 0 | Covered | T47,T68,T132 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 483
EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
---1--- ------2----- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T46,T180,T182 |
1 | 1 | 1 | Covered | T2,T5,T19 |
LINE 500
EXPRESSION (hint_forward & fifo_data_valid)
------1----- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T19 |
LINE 504
EXPRESSION (fifo_data_ready | fifo_forward_pop)
-------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 507
EXPRESSION (fifo_data_valid & descram_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T5,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 508
EXPRESSION (fifo_data_valid & forward_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T19 |
LINE 539
EXPRESSION (calc_req_o & calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T1,T13,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | T1,T2,T3 |
LINE 564
EXPRESSION (req_o && ack_i && descramble_i)
--1-- --2-- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T22,T46,T124 |
1 | 1 | 0 | Covered | T2,T5,T19 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 566
EXPRESSION (calc_req_o && calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T1,T13,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | T1,T2,T3 |
LINE 576
EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
-------1------- -----2---- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T47,T68,T132 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 586
EXPRESSION
Number Term
1 forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 586
SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 590
EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 590
SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
--------1--------
-1- | Status | Tests |
0 | Covered | T2,T5,T19 |
1 | Covered | T1,T2,T3 |
LINE 598
EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
---1--- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T5,T19 |
LINE 598
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 615
EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 615
SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 615
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 620
EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
------1----- -----2---- --------------------------3-------------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T15,T16,T17 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 620
SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
------1------ -----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 620
SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 636
EXPRESSION (buf_rsp_err | read_buf[i].err)
-----1----- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T45,T179 |
1 | 0 | Not Covered | |
LINE 642
EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 655
EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T14,T22 |
LINE 676
EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 676
SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
---------------------------------------------1---------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 688
EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
-------1------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 691
EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
--------------------------------------1------------------------------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T183,T184 |
1 | 0 | Covered | T1,T14,T22 |
LINE 691
SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
------1----- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T14,T22 |
LINE 691
SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
----1---- ----2--- -----------------3----------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Not Covered | |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T22,T49,T45 |
LINE 691
SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
---------1-------- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T45,T179 |
LINE 695
EXPRESSION (data_valid_o & intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T14,T22 |
Branch Coverage for Module :
flash_phy_rd
| Line No. | Total | Covered | Percent |
Branches |
|
39 |
39 |
100.00 |
TERNARY |
185 |
2 |
2 |
100.00 |
TERNARY |
231 |
2 |
2 |
100.00 |
TERNARY |
296 |
2 |
2 |
100.00 |
TERNARY |
439 |
2 |
2 |
100.00 |
TERNARY |
475 |
2 |
2 |
100.00 |
TERNARY |
586 |
3 |
3 |
100.00 |
TERNARY |
590 |
3 |
3 |
100.00 |
TERNARY |
615 |
3 |
3 |
100.00 |
TERNARY |
642 |
2 |
2 |
100.00 |
TERNARY |
676 |
2 |
2 |
100.00 |
TERNARY |
655 |
2 |
2 |
100.00 |
TERNARY |
166 |
2 |
2 |
100.00 |
IF |
256 |
3 |
3 |
100.00 |
IF |
354 |
4 |
4 |
100.00 |
IF |
562 |
3 |
3 |
100.00 |
IF |
634 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 185 ((|buf_invalid_alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 231 (no_match) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 296 ((|alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 439 ((data_err | ecc_single_err_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 475 (hint_descram) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 586 (forward) ?
-2-: 586 (hint_descram) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T19 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 590 (forward) ?
-2-: 590 ((~hint_forward)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T19 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T2,T5,T19 |
LineNo. Expression
-1-: 615 (forward) ?
-2-: 615 (((~hint_forward) & fifo_data_ready)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T19 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 642 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 676 (rsp_fifo_rdata.intg_ecc_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 655 (data_err_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T14,T22 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 166 (((|buf_invalid_alloc) | all_buf_dependency)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 256 if ((!rst_ni))
-2-: 258 if (idle_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 354 if ((!rst_ni))
-2-: 358 if ((req_o && ack_i))
-3-: 365 if (rd_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 562 if ((!rst_ni))
-2-: 564 if (((req_o && ack_i) && descramble_i))
-3-: 566 if ((calc_req_o && calc_ack_i))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Unreachable |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 634 if (buf_rsp_match[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd
Assertion Details
BufferMatchEcc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
725977760 |
1209599 |
0 |
0 |
T1 |
3195 |
37 |
0 |
0 |
T2 |
214496 |
1127 |
0 |
0 |
T3 |
4686 |
72 |
0 |
0 |
T4 |
521438 |
0 |
0 |
0 |
T5 |
96474 |
2288 |
0 |
0 |
T7 |
0 |
7084 |
0 |
0 |
T8 |
0 |
907 |
0 |
0 |
T9 |
9258 |
0 |
0 |
0 |
T12 |
7150 |
0 |
0 |
0 |
T13 |
786800 |
0 |
0 |
0 |
T14 |
1518 |
0 |
0 |
0 |
T18 |
2590 |
0 |
0 |
0 |
T19 |
55696 |
626 |
0 |
0 |
T22 |
0 |
1555 |
0 |
0 |
T27 |
0 |
1343 |
0 |
0 |
T30 |
0 |
3281 |
0 |
0 |
T45 |
0 |
1336 |
0 |
0 |
T47 |
0 |
115 |
0 |
0 |
T48 |
0 |
1660 |
0 |
0 |
T73 |
0 |
29 |
0 |
0 |
ExclusiveOps_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
725977760 |
724282096 |
0 |
0 |
T1 |
6390 |
6092 |
0 |
0 |
T2 |
214496 |
214486 |
0 |
0 |
T3 |
4686 |
4578 |
0 |
0 |
T4 |
521438 |
521292 |
0 |
0 |
T5 |
96474 |
96306 |
0 |
0 |
T9 |
9258 |
8256 |
0 |
0 |
T12 |
7150 |
5940 |
0 |
0 |
T13 |
786800 |
786776 |
0 |
0 |
T18 |
2590 |
2452 |
0 |
0 |
T19 |
55696 |
55586 |
0 |
0 |
ExclusiveProgHazard_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
725977760 |
724282096 |
0 |
0 |
T1 |
6390 |
6092 |
0 |
0 |
T2 |
214496 |
214486 |
0 |
0 |
T3 |
4686 |
4578 |
0 |
0 |
T4 |
521438 |
521292 |
0 |
0 |
T5 |
96474 |
96306 |
0 |
0 |
T9 |
9258 |
8256 |
0 |
0 |
T12 |
7150 |
5940 |
0 |
0 |
T13 |
786800 |
786776 |
0 |
0 |
T18 |
2590 |
2452 |
0 |
0 |
T19 |
55696 |
55586 |
0 |
0 |
ExclusiveState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
725977760 |
724282096 |
0 |
0 |
T1 |
6390 |
6092 |
0 |
0 |
T2 |
214496 |
214486 |
0 |
0 |
T3 |
4686 |
4578 |
0 |
0 |
T4 |
521438 |
521292 |
0 |
0 |
T5 |
96474 |
96306 |
0 |
0 |
T9 |
9258 |
8256 |
0 |
0 |
T12 |
7150 |
5940 |
0 |
0 |
T13 |
786800 |
786776 |
0 |
0 |
T18 |
2590 |
2452 |
0 |
0 |
T19 |
55696 |
55586 |
0 |
0 |
ForwardCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
725977760 |
3993434 |
0 |
0 |
T2 |
214496 |
1152 |
0 |
0 |
T3 |
4686 |
0 |
0 |
0 |
T4 |
521438 |
0 |
0 |
0 |
T5 |
96474 |
19357 |
0 |
0 |
T9 |
9258 |
0 |
0 |
0 |
T12 |
7150 |
0 |
0 |
0 |
T13 |
786800 |
0 |
0 |
0 |
T14 |
3036 |
0 |
0 |
0 |
T18 |
2590 |
0 |
0 |
0 |
T19 |
55696 |
626 |
0 |
0 |
T23 |
0 |
2133 |
0 |
0 |
T24 |
0 |
2342 |
0 |
0 |
T27 |
0 |
1923 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T41 |
0 |
2 |
0 |
0 |
T45 |
0 |
19630 |
0 |
0 |
T46 |
0 |
21294 |
0 |
0 |
T47 |
0 |
95 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T73 |
0 |
28 |
0 |
0 |
T131 |
0 |
21 |
0 |
0 |
IdleCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
725977760 |
93694129 |
0 |
0 |
T1 |
3195 |
493 |
0 |
0 |
T2 |
214496 |
3559 |
0 |
0 |
T3 |
4686 |
496 |
0 |
0 |
T4 |
521438 |
128 |
0 |
0 |
T5 |
96474 |
41130 |
0 |
0 |
T7 |
0 |
47123 |
0 |
0 |
T8 |
0 |
28166 |
0 |
0 |
T9 |
9258 |
768 |
0 |
0 |
T12 |
7150 |
706 |
0 |
0 |
T13 |
786800 |
1054976 |
0 |
0 |
T14 |
1518 |
0 |
0 |
0 |
T18 |
2590 |
128 |
0 |
0 |
T19 |
55696 |
2006 |
0 |
0 |
T22 |
0 |
98883 |
0 |
0 |
T27 |
0 |
4059 |
0 |
0 |
T30 |
0 |
47512 |
0 |
0 |
T41 |
0 |
2 |
0 |
0 |
MaxBufs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1982 |
1982 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T9 |
2 |
2 |
0 |
0 |
T12 |
2 |
2 |
0 |
0 |
T13 |
2 |
2 |
0 |
0 |
T18 |
2 |
2 |
0 |
0 |
T19 |
2 |
2 |
0 |
0 |
OneHotAlloc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
725977760 |
724282096 |
0 |
0 |
T1 |
6390 |
6092 |
0 |
0 |
T2 |
214496 |
214486 |
0 |
0 |
T3 |
4686 |
4578 |
0 |
0 |
T4 |
521438 |
521292 |
0 |
0 |
T5 |
96474 |
96306 |
0 |
0 |
T9 |
9258 |
8256 |
0 |
0 |
T12 |
7150 |
5940 |
0 |
0 |
T13 |
786800 |
786776 |
0 |
0 |
T18 |
2590 |
2452 |
0 |
0 |
T19 |
55696 |
55586 |
0 |
0 |
OneHotMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
725977760 |
724282096 |
0 |
0 |
T1 |
6390 |
6092 |
0 |
0 |
T2 |
214496 |
214486 |
0 |
0 |
T3 |
4686 |
4578 |
0 |
0 |
T4 |
521438 |
521292 |
0 |
0 |
T5 |
96474 |
96306 |
0 |
0 |
T9 |
9258 |
8256 |
0 |
0 |
T12 |
7150 |
5940 |
0 |
0 |
T13 |
786800 |
786776 |
0 |
0 |
T18 |
2590 |
2452 |
0 |
0 |
T19 |
55696 |
55586 |
0 |
0 |
OneHotRspMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
725977760 |
724282096 |
0 |
0 |
T1 |
6390 |
6092 |
0 |
0 |
T2 |
214496 |
214486 |
0 |
0 |
T3 |
4686 |
4578 |
0 |
0 |
T4 |
521438 |
521292 |
0 |
0 |
T5 |
96474 |
96306 |
0 |
0 |
T9 |
9258 |
8256 |
0 |
0 |
T12 |
7150 |
5940 |
0 |
0 |
T13 |
786800 |
786776 |
0 |
0 |
T18 |
2590 |
2452 |
0 |
0 |
T19 |
55696 |
55586 |
0 |
0 |
OneHotUpdate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
725977760 |
724282096 |
0 |
0 |
T1 |
6390 |
6092 |
0 |
0 |
T2 |
214496 |
214486 |
0 |
0 |
T3 |
4686 |
4578 |
0 |
0 |
T4 |
521438 |
521292 |
0 |
0 |
T5 |
96474 |
96306 |
0 |
0 |
T9 |
9258 |
8256 |
0 |
0 |
T12 |
7150 |
5940 |
0 |
0 |
T13 |
786800 |
786776 |
0 |
0 |
T18 |
2590 |
2452 |
0 |
0 |
T19 |
55696 |
55586 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
| Line No. | Total | Covered | Percent |
TOTAL | | 118 | 118 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 185 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
ALWAYS | 256 | 4 | 4 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 296 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 320 | 1 | 1 | 100.00 |
CONT_ASSIGN | 325 | 1 | 1 | 100.00 |
ALWAYS | 354 | 12 | 12 | 100.00 |
CONT_ASSIGN | 371 | 1 | 1 | 100.00 |
CONT_ASSIGN | 376 | 1 | 1 | 100.00 |
CONT_ASSIGN | 387 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
CONT_ASSIGN | 398 | 1 | 1 | 100.00 |
CONT_ASSIGN | 416 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 430 | 1 | 1 | 100.00 |
CONT_ASSIGN | 433 | 1 | 1 | 100.00 |
CONT_ASSIGN | 439 | 1 | 1 | 100.00 |
CONT_ASSIGN | 444 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 469 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 500 | 1 | 1 | 100.00 |
CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
CONT_ASSIGN | 507 | 1 | 1 | 100.00 |
CONT_ASSIGN | 508 | 1 | 1 | 100.00 |
ALWAYS | 562 | 5 | 5 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 576 | 1 | 1 | 100.00 |
CONT_ASSIGN | 579 | 1 | 1 | 100.00 |
CONT_ASSIGN | 586 | 1 | 1 | 100.00 |
CONT_ASSIGN | 590 | 1 | 1 | 100.00 |
CONT_ASSIGN | 598 | 1 | 1 | 100.00 |
CONT_ASSIGN | 615 | 1 | 1 | 100.00 |
CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
ALWAYS | 631 | 6 | 6 | 100.00 |
CONT_ASSIGN | 642 | 1 | 1 | 100.00 |
CONT_ASSIGN | 654 | 1 | 1 | 100.00 |
CONT_ASSIGN | 655 | 1 | 1 | 100.00 |
CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
CONT_ASSIGN | 688 | 1 | 1 | 100.00 |
CONT_ASSIGN | 691 | 1 | 1 | 100.00 |
CONT_ASSIGN | 695 | 1 | 1 | 100.00 |
CONT_ASSIGN | 698 | 1 | 1 | 100.00 |
CONT_ASSIGN | 701 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
136 |
1 |
1 |
139 |
4 |
4 |
140 |
4 |
4 |
145 |
4 |
4 |
151 |
1 |
1 |
153 |
3 |
3 |
185 |
1 |
1 |
192 |
4 |
4 |
193 |
4 |
4 |
195 |
4 |
4 |
211 |
4 |
4 |
217 |
4 |
4 |
221 |
4 |
4 |
228 |
1 |
1 |
231 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
259 |
1 |
1 |
|
|
|
MISSING_ELSE |
289 |
1 |
1 |
296 |
1 |
1 |
299 |
1 |
1 |
302 |
1 |
1 |
320 |
1 |
1 |
325 |
1 |
1 |
354 |
1 |
1 |
355 |
1 |
1 |
356 |
1 |
1 |
357 |
1 |
1 |
358 |
1 |
1 |
359 |
1 |
1 |
360 |
1 |
1 |
361 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
365 |
1 |
1 |
366 |
1 |
1 |
|
|
|
MISSING_ELSE |
371 |
1 |
1 |
376 |
1 |
1 |
387 |
1 |
1 |
393 |
1 |
1 |
398 |
1 |
1 |
416 |
1 |
1 |
420 |
1 |
1 |
430 |
1 |
1 |
433 |
1 |
1 |
439 |
1 |
1 |
444 |
1 |
1 |
447 |
1 |
1 |
469 |
1 |
1 |
475 |
1 |
1 |
479 |
1 |
1 |
483 |
1 |
1 |
500 |
1 |
1 |
504 |
1 |
1 |
507 |
1 |
1 |
508 |
1 |
1 |
562 |
1 |
1 |
563 |
1 |
1 |
564 |
1 |
1 |
565 |
1 |
1 |
566 |
1 |
1 |
567 |
|
unreachable |
|
|
|
MISSING_ELSE |
572 |
1 |
1 |
576 |
1 |
1 |
579 |
1 |
1 |
586 |
1 |
1 |
590 |
1 |
1 |
598 |
1 |
1 |
615 |
1 |
1 |
620 |
1 |
1 |
625 |
4 |
4 |
631 |
1 |
1 |
632 |
1 |
1 |
633 |
1 |
1 |
634 |
1 |
1 |
635 |
1 |
1 |
636 |
1 |
1 |
|
|
|
MISSING_ELSE |
642 |
1 |
1 |
654 |
1 |
1 |
655 |
1 |
1 |
676 |
1 |
1 |
688 |
1 |
1 |
691 |
1 |
1 |
695 |
1 |
1 |
698 |
1 |
1 |
701 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
| Total | Covered | Percent |
Conditions | 436 | 395 | 90.60 |
Logical | 436 | 395 | 90.60 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 139
EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[0].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[1].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[2].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[3].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[0].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T45 |
1 | 1 | 1 | Covered | T22,T45,T46 |
LINE 145
SUB-EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T22,T45,T131 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[1].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T22,T45,T131 |
LINE 145
SUB-EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T22,T49,T45 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[2].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T22,T49,T45 |
LINE 145
SUB-EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[3].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T22,T45,T46 |
LINE 145
SUB-EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 153
EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
-------1------ ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 153
EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 153
EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 166
EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 166
SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
-----------1---------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 166
EXPRESSION (req_o & no_match)
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 185
EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[0].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[1].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[2].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[3].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[0].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[1].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[2].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[3].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[0] | buf_wip[0]) &
4 (read_buf[0].addr == flash_word_addr) &
5 ((~read_buf[0].err)) &
6 gen_buf_match[0].part_match &
7 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T47,T48,T33 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T45,T46,T125 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T5,T180,T127 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[1] | buf_wip[1]) &
4 (read_buf[1].addr == flash_word_addr) &
5 ((~read_buf[1].err)) &
6 gen_buf_match[1].part_match &
7 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T47,T48,T33 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T180,T125,T127 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T22,T45,T46 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[2] | buf_wip[2]) &
4 (read_buf[2].addr == flash_word_addr) &
5 ((~read_buf[2].err)) &
6 gen_buf_match[2].part_match &
7 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T1,T47,T48 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T22,T46,T125 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T126,T129,T185 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[3] | buf_wip[3]) &
4 (read_buf[3].addr == flash_word_addr) &
5 ((~read_buf[3].err)) &
6 gen_buf_match[3].part_match &
7 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T47,T48,T33 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T45,T46,T180 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Covered | T181 |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T46,T39,T126 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T7,T180 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T22,T45 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T126,T129 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T46,T39 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[0].part_match &
3 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T7,T22 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[1].part_match &
3 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T22,T45 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[2].part_match &
3 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T46,T59 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[3].part_match &
3 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T46,T59 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 221
EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T47 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T47,T48 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T47,T48 |
0 | 1 | 0 | Covered | T2,T13,T48 |
1 | 0 | 0 | Covered | T2,T24,T25 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T2,T13,T48 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T12,T13 |
1 | 1 | Covered | T13,T47,T48 |
LINE 221
EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T47 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T47,T48 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T47,T48 |
0 | 1 | 0 | Covered | T2,T13,T48 |
1 | 0 | 0 | Covered | T2,T24,T25 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T2,T13,T48 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T12,T13 |
1 | 1 | Covered | T13,T47,T48 |
LINE 221
EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T13 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T47 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T47,T48 |
0 | 1 | 0 | Covered | T1,T2,T13 |
1 | 0 | 0 | Covered | T2,T24,T25 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T13 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T12,T13 |
1 | 1 | Covered | T13,T47,T48 |
LINE 221
EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T47 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T47,T48 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T47,T48 |
0 | 1 | 0 | Covered | T2,T13,T48 |
1 | 0 | 0 | Covered | T2,T24,T25 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T2,T13,T48 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T12,T13 |
1 | 1 | Covered | T13,T47,T48 |
LINE 231
EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (rdy_o & alloc[0])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (rdy_o & alloc[1])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (rdy_o & alloc[2])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T30,T45 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (rdy_o & alloc[3])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T22,T45 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 289
EXPRESSION (rd_busy & done_i)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 296
EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 299
EXPRESSION (req_i && rdy_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T7,T8 |
1 | 1 | Covered | T1,T2,T3 |
LINE 302
EXPRESSION (rsp_fifo_vld & data_valid_o)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION (req_o && ack_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T22,T46,T39 |
1 | 1 | Covered | T1,T2,T3 |
LINE 371
EXPRESSION (((~rd_busy)) | rd_done)
------1----- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 376
EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T22 |
1 | 0 | Covered | T15,T16,T17 |
1 | 1 | Covered | T1,T2,T3 |
LINE 387
EXPRESSION (buf_en_q == buf_en_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 393
EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change)
--------------------------------1------------------------------- -----------2----------- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 393
SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 393
SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
--1-- ----2---- ------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T22 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 398
EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match)
--1-- --------2------- ----3---- ------4------ ----5---
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | Covered | T5,T7,T8 |
1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 416
EXPRESSION (rd_done && rd_attrs.ecc)
---1--- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T5,T47 |
1 | 1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
---1--- ------------------------2------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T13 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T47 |
LINE 420
SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T13 |
LINE 430
EXPRESSION (valid_ecc & ecc_multi_err)
----1---- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T47,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T22,T49,T45 |
LINE 439
EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T19 |
LINE 439
SUB-EXPRESSION (data_err | ecc_single_err_o)
----1--- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T19 |
1 | 0 | Covered | T22,T49,T45 |
LINE 444
EXPRESSION (valid_ecc & ecc_single_err)
----1---- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T19 |
LINE 469
EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T15,T16,T17 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 475
EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 475
SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 479
EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
---1--- ---------2--------- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T19,T47,T41 |
1 | 1 | 0 | Covered | T47,T68,T132 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 483
EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
---1--- ------2----- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T46,T180,T186 |
1 | 1 | 1 | Covered | T2,T5,T19 |
LINE 500
EXPRESSION (hint_forward & fifo_data_valid)
------1----- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T19 |
LINE 504
EXPRESSION (fifo_data_ready | fifo_forward_pop)
-------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 507
EXPRESSION (fifo_data_valid & descram_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T5,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 508
EXPRESSION (fifo_data_valid & forward_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T19 |
LINE 539
EXPRESSION (calc_req_o & calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T1,T13,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | T1,T2,T3 |
LINE 564
EXPRESSION (req_o && ack_i && descramble_i)
--1-- --2-- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T22,T46,T124 |
1 | 1 | 0 | Covered | T2,T5,T19 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 566
EXPRESSION (calc_req_o && calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T1,T13,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | T1,T2,T3 |
LINE 576
EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
-------1------- -----2---- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T47,T68,T132 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 586
EXPRESSION
Number Term
1 forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 586
SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 590
EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 590
SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
--------1--------
-1- | Status | Tests |
0 | Covered | T2,T5,T19 |
1 | Covered | T1,T2,T3 |
LINE 598
EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
---1--- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T5,T19 |
LINE 598
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 615
EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 615
SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 615
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 620
EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
------1----- -----2---- --------------------------3-------------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T15,T16,T17 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 620
SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
------1------ -----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 620
SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 636
EXPRESSION (buf_rsp_err | read_buf[i].err)
-----1----- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T45 |
1 | 0 | Not Covered | |
LINE 642
EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 655
EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T14,T22 |
LINE 676
EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 676
SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
---------------------------------------------1---------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 688
EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
-------1------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 691
EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
--------------------------------------1------------------------------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T183,T184 |
1 | 0 | Covered | T1,T14,T22 |
LINE 691
SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
------1----- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T14,T22 |
LINE 691
SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
----1---- ----2--- -----------------3----------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Not Covered | |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T22,T49,T45 |
LINE 691
SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
---------1-------- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T45 |
LINE 695
EXPRESSION (data_valid_o & intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T14,T22 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
| Line No. | Total | Covered | Percent |
Branches |
|
39 |
39 |
100.00 |
TERNARY |
185 |
2 |
2 |
100.00 |
TERNARY |
231 |
2 |
2 |
100.00 |
TERNARY |
296 |
2 |
2 |
100.00 |
TERNARY |
439 |
2 |
2 |
100.00 |
TERNARY |
475 |
2 |
2 |
100.00 |
TERNARY |
586 |
3 |
3 |
100.00 |
TERNARY |
590 |
3 |
3 |
100.00 |
TERNARY |
615 |
3 |
3 |
100.00 |
TERNARY |
642 |
2 |
2 |
100.00 |
TERNARY |
676 |
2 |
2 |
100.00 |
TERNARY |
655 |
2 |
2 |
100.00 |
TERNARY |
166 |
2 |
2 |
100.00 |
IF |
256 |
3 |
3 |
100.00 |
IF |
354 |
4 |
4 |
100.00 |
IF |
562 |
3 |
3 |
100.00 |
IF |
634 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 185 ((|buf_invalid_alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 231 (no_match) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 296 ((|alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 439 ((data_err | ecc_single_err_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 475 (hint_descram) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 586 (forward) ?
-2-: 586 (hint_descram) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T19 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 590 (forward) ?
-2-: 590 ((~hint_forward)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T19 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T2,T5,T19 |
LineNo. Expression
-1-: 615 (forward) ?
-2-: 615 (((~hint_forward) & fifo_data_ready)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T19 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 642 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 676 (rsp_fifo_rdata.intg_ecc_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 655 (data_err_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T14,T22 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 166 (((|buf_invalid_alloc) | all_buf_dependency)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 256 if ((!rst_ni))
-2-: 258 if (idle_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 354 if ((!rst_ni))
-2-: 358 if ((req_o && ack_i))
-3-: 365 if (rd_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 562 if ((!rst_ni))
-2-: 564 if (((req_o && ack_i) && descramble_i))
-3-: 566 if ((calc_req_o && calc_ack_i))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Unreachable |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 634 if (buf_rsp_match[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Assertion Details
BufferMatchEcc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
702694 |
0 |
0 |
T1 |
3195 |
37 |
0 |
0 |
T2 |
107248 |
1073 |
0 |
0 |
T3 |
2343 |
72 |
0 |
0 |
T4 |
260719 |
0 |
0 |
0 |
T5 |
48237 |
1187 |
0 |
0 |
T7 |
0 |
3345 |
0 |
0 |
T8 |
0 |
511 |
0 |
0 |
T9 |
4629 |
0 |
0 |
0 |
T12 |
3575 |
0 |
0 |
0 |
T13 |
393400 |
0 |
0 |
0 |
T18 |
1295 |
0 |
0 |
0 |
T19 |
27848 |
390 |
0 |
0 |
T22 |
0 |
1016 |
0 |
0 |
T47 |
0 |
115 |
0 |
0 |
T48 |
0 |
1660 |
0 |
0 |
ExclusiveOps_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
ExclusiveProgHazard_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
ExclusiveState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
ForwardCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
2163746 |
0 |
0 |
T2 |
107248 |
1085 |
0 |
0 |
T3 |
2343 |
0 |
0 |
0 |
T4 |
260719 |
0 |
0 |
0 |
T5 |
48237 |
9882 |
0 |
0 |
T9 |
4629 |
0 |
0 |
0 |
T12 |
3575 |
0 |
0 |
0 |
T13 |
393400 |
0 |
0 |
0 |
T14 |
1518 |
0 |
0 |
0 |
T18 |
1295 |
0 |
0 |
0 |
T19 |
27848 |
390 |
0 |
0 |
T27 |
0 |
565 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T45 |
0 |
9230 |
0 |
0 |
T47 |
0 |
95 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T131 |
0 |
21 |
0 |
0 |
IdleCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
48875703 |
0 |
0 |
T1 |
3195 |
493 |
0 |
0 |
T2 |
107248 |
3371 |
0 |
0 |
T3 |
2343 |
496 |
0 |
0 |
T4 |
260719 |
128 |
0 |
0 |
T5 |
48237 |
21079 |
0 |
0 |
T9 |
4629 |
768 |
0 |
0 |
T12 |
3575 |
706 |
0 |
0 |
T13 |
393400 |
530688 |
0 |
0 |
T18 |
1295 |
128 |
0 |
0 |
T19 |
27848 |
1298 |
0 |
0 |
MaxBufs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
991 |
991 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OneHotAlloc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
OneHotMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
OneHotRspMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
OneHotUpdate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
| Line No. | Total | Covered | Percent |
TOTAL | | 118 | 118 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 185 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
ALWAYS | 256 | 4 | 4 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 296 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 320 | 1 | 1 | 100.00 |
CONT_ASSIGN | 325 | 1 | 1 | 100.00 |
ALWAYS | 354 | 12 | 12 | 100.00 |
CONT_ASSIGN | 371 | 1 | 1 | 100.00 |
CONT_ASSIGN | 376 | 1 | 1 | 100.00 |
CONT_ASSIGN | 387 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
CONT_ASSIGN | 398 | 1 | 1 | 100.00 |
CONT_ASSIGN | 416 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 430 | 1 | 1 | 100.00 |
CONT_ASSIGN | 433 | 1 | 1 | 100.00 |
CONT_ASSIGN | 439 | 1 | 1 | 100.00 |
CONT_ASSIGN | 444 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 469 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 483 | 1 | 1 | 100.00 |
CONT_ASSIGN | 500 | 1 | 1 | 100.00 |
CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
CONT_ASSIGN | 507 | 1 | 1 | 100.00 |
CONT_ASSIGN | 508 | 1 | 1 | 100.00 |
ALWAYS | 562 | 5 | 5 | 100.00 |
CONT_ASSIGN | 572 | 1 | 1 | 100.00 |
CONT_ASSIGN | 576 | 1 | 1 | 100.00 |
CONT_ASSIGN | 579 | 1 | 1 | 100.00 |
CONT_ASSIGN | 586 | 1 | 1 | 100.00 |
CONT_ASSIGN | 590 | 1 | 1 | 100.00 |
CONT_ASSIGN | 598 | 1 | 1 | 100.00 |
CONT_ASSIGN | 615 | 1 | 1 | 100.00 |
CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
CONT_ASSIGN | 625 | 1 | 1 | 100.00 |
ALWAYS | 631 | 6 | 6 | 100.00 |
CONT_ASSIGN | 642 | 1 | 1 | 100.00 |
CONT_ASSIGN | 654 | 1 | 1 | 100.00 |
CONT_ASSIGN | 655 | 1 | 1 | 100.00 |
CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
CONT_ASSIGN | 688 | 1 | 1 | 100.00 |
CONT_ASSIGN | 691 | 1 | 1 | 100.00 |
CONT_ASSIGN | 695 | 1 | 1 | 100.00 |
CONT_ASSIGN | 698 | 1 | 1 | 100.00 |
CONT_ASSIGN | 701 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
136 |
1 |
1 |
139 |
4 |
4 |
140 |
4 |
4 |
145 |
4 |
4 |
151 |
1 |
1 |
153 |
3 |
3 |
185 |
1 |
1 |
192 |
4 |
4 |
193 |
4 |
4 |
195 |
4 |
4 |
211 |
4 |
4 |
217 |
4 |
4 |
221 |
4 |
4 |
228 |
1 |
1 |
231 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
259 |
1 |
1 |
|
|
|
MISSING_ELSE |
289 |
1 |
1 |
296 |
1 |
1 |
299 |
1 |
1 |
302 |
1 |
1 |
320 |
1 |
1 |
325 |
1 |
1 |
354 |
1 |
1 |
355 |
1 |
1 |
356 |
1 |
1 |
357 |
1 |
1 |
358 |
1 |
1 |
359 |
1 |
1 |
360 |
1 |
1 |
361 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
365 |
1 |
1 |
366 |
1 |
1 |
|
|
|
MISSING_ELSE |
371 |
1 |
1 |
376 |
1 |
1 |
387 |
1 |
1 |
393 |
1 |
1 |
398 |
1 |
1 |
416 |
1 |
1 |
420 |
1 |
1 |
430 |
1 |
1 |
433 |
1 |
1 |
439 |
1 |
1 |
444 |
1 |
1 |
447 |
1 |
1 |
469 |
1 |
1 |
475 |
1 |
1 |
479 |
1 |
1 |
483 |
1 |
1 |
500 |
1 |
1 |
504 |
1 |
1 |
507 |
1 |
1 |
508 |
1 |
1 |
562 |
1 |
1 |
563 |
1 |
1 |
564 |
1 |
1 |
565 |
1 |
1 |
566 |
1 |
1 |
567 |
|
unreachable |
|
|
|
MISSING_ELSE |
572 |
1 |
1 |
576 |
1 |
1 |
579 |
1 |
1 |
586 |
1 |
1 |
590 |
1 |
1 |
598 |
1 |
1 |
615 |
1 |
1 |
620 |
1 |
1 |
625 |
4 |
4 |
631 |
1 |
1 |
632 |
1 |
1 |
633 |
1 |
1 |
634 |
1 |
1 |
635 |
1 |
1 |
636 |
1 |
1 |
|
|
|
MISSING_ELSE |
642 |
1 |
1 |
654 |
1 |
1 |
655 |
1 |
1 |
676 |
1 |
1 |
688 |
1 |
1 |
691 |
1 |
1 |
695 |
1 |
1 |
698 |
1 |
1 |
701 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
| Total | Covered | Percent |
Conditions | 436 | 396 | 90.83 |
Logical | 436 | 396 | 90.83 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 139
EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 139
EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 139
EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 139
EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 140
EXPRESSION (read_buf[0].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 140
EXPRESSION (read_buf[1].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 140
EXPRESSION (read_buf[2].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 140
EXPRESSION (read_buf[3].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 145
EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T5,T19 |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[0].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T5,T19 |
1 | 1 | 0 | Covered | T179 |
1 | 1 | 1 | Covered | T22,T45,T46 |
LINE 145
SUB-EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 145
EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T5,T19 |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[1].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T5,T19 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T22,T45,T46 |
LINE 145
SUB-EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 145
EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T5,T19 |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[2].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T5,T19 |
1 | 1 | 0 | Covered | T179 |
1 | 1 | 1 | Covered | T22,T45,T46 |
LINE 145
SUB-EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 145
EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T5,T19 |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (read_buf[3].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T5,T19 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T22,T45,T46 |
LINE 145
SUB-EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 153
EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
-------1------ ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T19 |
LINE 153
EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T19 |
LINE 153
EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T19 |
LINE 166
EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T2,T5,T19 |
1 | Covered | T1,T2,T3 |
LINE 166
SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
-----------1---------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T5,T19 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 166
EXPRESSION (req_o & no_match)
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T13,T5 |
LINE 185
EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
-----------1----------
-1- | Status | Tests |
0 | Covered | T2,T5,T19 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[0].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[1].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[2].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (read_buf[3].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[0].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[1].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[2].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[3].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[0] | buf_wip[0]) &
4 (read_buf[0].addr == flash_word_addr) &
5 ((~read_buf[0].err)) &
6 gen_buf_match[0].part_match &
7 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T187,T188,T189 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T2,T5,T19 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T45,T46,T125 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T5,T7,T46 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
LINE 195
SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T2,T5,T19 |
LINE 195
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[1] | buf_wip[1]) &
4 (read_buf[1].addr == flash_word_addr) &
5 ((~read_buf[1].err)) &
6 gen_buf_match[1].part_match &
7 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Covered | T118 |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T190,T145,T191 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T2,T5,T19 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T45,T46,T180 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T182,T126,T192 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
LINE 195
SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T2,T5,T19 |
LINE 195
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[2] | buf_wip[2]) &
4 (read_buf[2].addr == flash_word_addr) &
5 ((~read_buf[2].err)) &
6 gen_buf_match[2].part_match &
7 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T145,T191,T193 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T2,T5,T19 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T46,T180,T125 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T46,T124,T125 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
LINE 195
SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T2,T5,T19 |
LINE 195
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[3] | buf_wip[3]) &
4 (read_buf[3].addr == flash_word_addr) &
5 ((~read_buf[3].err)) &
6 gen_buf_match[3].part_match &
7 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Covered | T91 |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T76,T143,T145 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T2,T5,T19 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T45,T46,T127 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T5,T46,T178 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
LINE 195
SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T2,T5,T19 |
LINE 195
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T7,T46 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T182,T126,T192 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T46,T124,T125 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T46,T178 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[0].part_match &
3 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T7,T45 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[1].part_match &
3 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T59,T39,T35 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[2].part_match &
3 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T22,T45 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION
Number Term
1 (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[3].part_match &
3 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T5,T22,T46 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 217
SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 221
EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T9,T23 |
1 | 0 | Covered | T2,T5,T19 |
1 | 1 | Covered | T23,T24,T75 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T84,T145 |
0 | 1 | 0 | Covered | T13,T9,T75 |
1 | 0 | 0 | Covered | T23,T24,T26 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T13 |
1 | 1 | Covered | T13,T9,T75 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T13,T27 |
1 | 1 | Covered | T13,T84,T145 |
LINE 221
EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T9,T23 |
1 | 0 | Covered | T2,T5,T19 |
1 | 1 | Covered | T23,T24,T26 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T84,T145 |
0 | 1 | 0 | Covered | T13,T9,T84 |
1 | 0 | 0 | Covered | T23,T24,T26 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T13 |
1 | 1 | Covered | T13,T9,T84 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T13,T27 |
1 | 1 | Covered | T13,T84,T145 |
LINE 221
EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T9,T23 |
1 | 0 | Covered | T2,T5,T19 |
1 | 1 | Covered | T23,T24,T50 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T50,T84 |
0 | 1 | 0 | Covered | T13,T9,T84 |
1 | 0 | 0 | Covered | T23,T24,T26 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T13 |
1 | 1 | Covered | T13,T9,T84 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T13,T27 |
1 | 1 | Covered | T13,T50,T84 |
LINE 221
EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T9,T23 |
1 | 0 | Covered | T2,T5,T19 |
1 | 1 | Covered | T23,T24,T76 |
LINE 221
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T84,T145 |
0 | 1 | 0 | Covered | T13,T9,T76 |
1 | 0 | 0 | Covered | T23,T24,T26 |
LINE 221
SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T13 |
1 | 1 | Covered | T13,T9,T76 |
LINE 221
SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T13,T27 |
1 | 1 | Covered | T13,T84,T145 |
LINE 231
EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
----1---
-1- | Status | Tests |
0 | Covered | T2,T5,T19 |
1 | Covered | T1,T2,T3 |
LINE 238
EXPRESSION (rdy_o & alloc[0])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T45,T46 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T19 |
LINE 238
EXPRESSION (rdy_o & alloc[1])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T30,T45 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T19 |
LINE 238
EXPRESSION (rdy_o & alloc[2])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T22,T45 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T19 |
LINE 238
EXPRESSION (rdy_o & alloc[3])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T22,T45 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T19 |
LINE 289
EXPRESSION (rd_busy & done_i)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T13 |
1 | 0 | Covered | T2,T13,T5 |
1 | 1 | Covered | T2,T13,T5 |
LINE 296
EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 299
EXPRESSION (req_i && rdy_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T7,T8 |
1 | 1 | Covered | T2,T13,T5 |
LINE 302
EXPRESSION (rsp_fifo_vld & data_valid_o)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T13,T5 |
1 | 1 | Covered | T2,T13,T5 |
LINE 358
EXPRESSION (req_o && ack_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T22,T46,T39 |
1 | 1 | Covered | T2,T13,T5 |
LINE 371
EXPRESSION (((~rd_busy)) | rd_done)
------1----- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T13,T5 |
0 | 1 | Covered | T2,T13,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 376
EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T22 |
1 | 0 | Covered | T15,T16,T17 |
1 | 1 | Covered | T1,T2,T3 |
LINE 387
EXPRESSION (buf_en_q == buf_en_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 393
EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change)
--------------------------------1------------------------------- -----------2----------- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 393
SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
----1---
-1- | Status | Tests |
0 | Covered | T2,T5,T19 |
1 | Covered | T1,T2,T3 |
LINE 393
SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
--1-- ----2---- ------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T13,T5 |
1 | 1 | 0 | Covered | T7,T8,T22 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 398
EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match)
--1-- --------2------- ----3---- ------4------ ----5---
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | Covered | T5,T7,T8 |
1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 0 | Covered | T2,T5,T19 |
1 | 1 | 1 | 1 | 1 | Covered | T2,T13,T5 |
LINE 416
EXPRESSION (rd_done && rd_attrs.ecc)
---1--- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T19,T7 |
1 | 0 | Covered | T2,T5,T27 |
1 | 1 | Covered | T13,T19,T7 |
LINE 420
EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
---1--- ------------------------2------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T13 |
1 | 0 | Covered | T13,T19,T7 |
1 | 1 | Covered | T2,T5,T23 |
LINE 420
SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T13 |
LINE 430
EXPRESSION (valid_ecc & ecc_multi_err)
----1---- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T22 |
1 | 0 | Covered | T13,T19,T7 |
1 | 1 | Covered | T22,T45,T46 |
LINE 439
EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T19,T8,T22 |
LINE 439
SUB-EXPRESSION (data_err | ecc_single_err_o)
----1--- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T19,T8,T22 |
1 | 0 | Covered | T22,T45,T46 |
LINE 444
EXPRESSION (valid_ecc & ecc_single_err)
----1---- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T19,T6 |
1 | 0 | Covered | T13,T19,T7 |
1 | 1 | Covered | T19,T8,T22 |
LINE 469
EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T15,T16,T17 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 475
EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T13,T7,T8 |
LINE 475
SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T13,T7,T8 |
1 | 1 | Covered | T13,T7,T8 |
LINE 479
EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
---1--- ---------2--------- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T13,T7,T8 |
1 | 0 | 1 | Covered | T19,T41,T27 |
1 | 1 | 0 | Covered | T68,T132,T194 |
1 | 1 | 1 | Covered | T13,T7,T8 |
LINE 483
EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
---1--- ------2----- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T7,T8 |
1 | 1 | 0 | Covered | T180,T182,T186 |
1 | 1 | 1 | Covered | T2,T5,T19 |
LINE 500
EXPRESSION (hint_forward & fifo_data_valid)
------1----- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T7,T8 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T19 |
LINE 504
EXPRESSION (fifo_data_ready | fifo_forward_pop)
-------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T13,T7,T8 |
LINE 507
EXPRESSION (fifo_data_valid & descram_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T5,T19 |
1 | 1 | Covered | T13,T7,T8 |
LINE 508
EXPRESSION (fifo_data_valid & forward_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T13,T7,T8 |
1 | 1 | Covered | T2,T5,T19 |
LINE 539
EXPRESSION (calc_req_o & calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T13,T9,T22 |
1 | 0 | Covered | T13,T7,T8 |
1 | 1 | Unreachable | T13,T7,T8 |
LINE 564
EXPRESSION (req_o && ack_i && descramble_i)
--1-- --2-- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T22,T124,T125 |
1 | 1 | 0 | Covered | T2,T5,T19 |
1 | 1 | 1 | Covered | T13,T7,T8 |
LINE 566
EXPRESSION (calc_req_o && calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | T13,T9,T22 |
1 | 0 | Covered | T13,T7,T8 |
1 | 1 | Unreachable | T13,T7,T8 |
LINE 576
EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
-------1------- -----2---- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T68,T132,T194 |
1 | 1 | 1 | Covered | T13,T7,T8 |
LINE 586
EXPRESSION
Number Term
1 forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 586
SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T13,T7,T8 |
LINE 590
EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 590
SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
--------1--------
-1- | Status | Tests |
0 | Covered | T2,T5,T19 |
1 | Covered | T1,T2,T3 |
LINE 598
EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
---1--- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T7,T8 |
1 | 0 | Covered | T2,T5,T19 |
LINE 598
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T7,T8 |
LINE 615
EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 615
SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T13,T7,T8 |
LINE 615
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T7,T8 |
LINE 620
EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
------1----- -----2---- --------------------------3-------------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T15,T16,T17 |
1 | 0 | 1 | Covered | T13,T15,T84 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T13,T5 |
LINE 620
SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
------1------ -----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T5,T19 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 620
SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T2,T5,T19 |
1 | 1 | 1 | 0 | Covered | T2,T5,T19 |
1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T2,T5,T19 |
1 | 1 | 1 | 0 | Covered | T2,T5,T19 |
1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T2,T5,T19 |
1 | 1 | 1 | 0 | Covered | T2,T5,T19 |
1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
LINE 625
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T2,T5,T19 |
1 | 1 | 1 | 0 | Covered | T2,T5,T19 |
1 | 1 | 1 | 1 | Covered | T2,T5,T19 |
LINE 636
EXPRESSION (buf_rsp_err | read_buf[i].err)
-----1----- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T5,T19 |
0 | 1 | Covered | T179 |
1 | 0 | Not Covered | |
LINE 642
EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T19 |
LINE 655
EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T22,T45,T73 |
LINE 676
EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T13,T19,T7 |
LINE 676
SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
---------------------------------------------1---------------------------------------------
-1- | Status | Tests |
0 | Covered | T13,T19,T7 |
1 | Covered | T13,T7,T8 |
LINE 688
EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
-------1------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T5,T19 |
1 | 0 | Covered | T2,T13,T5 |
LINE 691
EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
--------------------------------------1------------------------------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T22,T45,T73 |
LINE 691
SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
------1----- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T7,T8 |
1 | 0 | Covered | T2,T13,T5 |
1 | 1 | Covered | T22,T45,T73 |
LINE 691
SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
----1---- ----2--- -----------------3----------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Not Covered | |
0 | 1 | 0 | Covered | T13,T7,T8 |
1 | 0 | 0 | Covered | T22,T45,T46 |
LINE 691
SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
---------1-------- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T5,T19 |
1 | 1 | Covered | T179 |
LINE 695
EXPRESSION (data_valid_o & intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T7,T8 |
1 | 0 | Covered | T2,T13,T5 |
1 | 1 | Covered | T22,T45,T73 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
| Line No. | Total | Covered | Percent |
Branches |
|
39 |
39 |
100.00 |
TERNARY |
185 |
2 |
2 |
100.00 |
TERNARY |
231 |
2 |
2 |
100.00 |
TERNARY |
296 |
2 |
2 |
100.00 |
TERNARY |
439 |
2 |
2 |
100.00 |
TERNARY |
475 |
2 |
2 |
100.00 |
TERNARY |
586 |
3 |
3 |
100.00 |
TERNARY |
590 |
3 |
3 |
100.00 |
TERNARY |
615 |
3 |
3 |
100.00 |
TERNARY |
642 |
2 |
2 |
100.00 |
TERNARY |
676 |
2 |
2 |
100.00 |
TERNARY |
655 |
2 |
2 |
100.00 |
TERNARY |
166 |
2 |
2 |
100.00 |
IF |
256 |
3 |
3 |
100.00 |
IF |
354 |
4 |
4 |
100.00 |
IF |
562 |
3 |
3 |
100.00 |
IF |
634 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 185 ((|buf_invalid_alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T5,T19 |
LineNo. Expression
-1-: 231 (no_match) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T5,T19 |
LineNo. Expression
-1-: 296 ((|alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T5,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 439 ((data_err | ecc_single_err_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T19,T8,T22 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 475 (hint_descram) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T13,T7,T8 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 586 (forward) ?
-2-: 586 (hint_descram) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T19 |
0 |
1 |
Covered |
T13,T7,T8 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 590 (forward) ?
-2-: 590 ((~hint_forward)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T19 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T2,T5,T19 |
LineNo. Expression
-1-: 615 (forward) ?
-2-: 615 (((~hint_forward) & fifo_data_ready)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T19 |
0 |
1 |
Covered |
T13,T7,T8 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 642 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T5,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 676 (rsp_fifo_rdata.intg_ecc_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T13,T19,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 655 (data_err_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T22,T45,T73 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 166 (((|buf_invalid_alloc) | all_buf_dependency)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T5,T19 |
LineNo. Expression
-1-: 256 if ((!rst_ni))
-2-: 258 if (idle_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T2,T13,T5 |
LineNo. Expression
-1-: 354 if ((!rst_ni))
-2-: 358 if ((req_o && ack_i))
-3-: 365 if (rd_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T13,T5 |
0 |
0 |
1 |
Covered |
T2,T13,T5 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 562 if ((!rst_ni))
-2-: 564 if (((req_o && ack_i) && descramble_i))
-3-: 566 if ((calc_req_o && calc_ack_i))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T13,T7,T8 |
0 |
0 |
1 |
Unreachable |
T13,T7,T8 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 634 if (buf_rsp_match[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T5,T19 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Assertion Details
BufferMatchEcc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
506905 |
0 |
0 |
T2 |
107248 |
54 |
0 |
0 |
T3 |
2343 |
0 |
0 |
0 |
T4 |
260719 |
0 |
0 |
0 |
T5 |
48237 |
1101 |
0 |
0 |
T7 |
0 |
3739 |
0 |
0 |
T8 |
0 |
396 |
0 |
0 |
T9 |
4629 |
0 |
0 |
0 |
T12 |
3575 |
0 |
0 |
0 |
T13 |
393400 |
0 |
0 |
0 |
T14 |
1518 |
0 |
0 |
0 |
T18 |
1295 |
0 |
0 |
0 |
T19 |
27848 |
236 |
0 |
0 |
T22 |
0 |
539 |
0 |
0 |
T27 |
0 |
1343 |
0 |
0 |
T30 |
0 |
3281 |
0 |
0 |
T45 |
0 |
1336 |
0 |
0 |
T73 |
0 |
29 |
0 |
0 |
ExclusiveOps_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
ExclusiveProgHazard_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
ExclusiveState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
ForwardCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
1829688 |
0 |
0 |
T2 |
107248 |
67 |
0 |
0 |
T3 |
2343 |
0 |
0 |
0 |
T4 |
260719 |
0 |
0 |
0 |
T5 |
48237 |
9475 |
0 |
0 |
T9 |
4629 |
0 |
0 |
0 |
T12 |
3575 |
0 |
0 |
0 |
T13 |
393400 |
0 |
0 |
0 |
T14 |
1518 |
0 |
0 |
0 |
T18 |
1295 |
0 |
0 |
0 |
T19 |
27848 |
236 |
0 |
0 |
T23 |
0 |
2133 |
0 |
0 |
T24 |
0 |
2342 |
0 |
0 |
T27 |
0 |
1358 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T45 |
0 |
10400 |
0 |
0 |
T46 |
0 |
21294 |
0 |
0 |
T73 |
0 |
28 |
0 |
0 |
IdleCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
44818426 |
0 |
0 |
T2 |
107248 |
188 |
0 |
0 |
T3 |
2343 |
0 |
0 |
0 |
T4 |
260719 |
0 |
0 |
0 |
T5 |
48237 |
20051 |
0 |
0 |
T7 |
0 |
47123 |
0 |
0 |
T8 |
0 |
28166 |
0 |
0 |
T9 |
4629 |
0 |
0 |
0 |
T12 |
3575 |
0 |
0 |
0 |
T13 |
393400 |
524288 |
0 |
0 |
T14 |
1518 |
0 |
0 |
0 |
T18 |
1295 |
0 |
0 |
0 |
T19 |
27848 |
708 |
0 |
0 |
T22 |
0 |
98883 |
0 |
0 |
T27 |
0 |
4059 |
0 |
0 |
T30 |
0 |
47512 |
0 |
0 |
T41 |
0 |
2 |
0 |
0 |
MaxBufs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
991 |
991 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OneHotAlloc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
OneHotMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
OneHotRspMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
OneHotUpdate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988880 |
362141048 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |