Unified Coverage Report :: Module :: prim_arbiter_tree

Module : prim_arbiter_tree

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random	94.17	92.31	97.69			100.00	86.67
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.65	100.00	90.60			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	100.00	90.83			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_tree

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Module : prim_arbiter_tree

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T45,T46
1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T22
1	0	Covered	T7,T8,T22

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T22
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_tree

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	725977760	724282096	0	0
CheckNGreaterZero_A	1982	1982	0	0
GntImpliesReady_A	725977760	5287284	0	0
GntImpliesValid_A	725977760	5287284	0	0
GrantKnown_A	725977760	724282096	0	0
IdxKnown_A	725977760	724282096	0	0
IndexIsCorrect_A	725977760	5287284	0	0
LockArbDecision_A	725977760	0	0	0
NoReadyValidNoGrant_A	725977760	520060789	0	0
ReadyAndValidImplyGrant_A	725977760	5287284	0	0
ReqAndReadyImplyGrant_A	725977760	5287284	0	0
ReqImpliesValid_A	725977760	196325892	0	0
ReqStaysHighUntilGranted0_M	725977760	0	0	0
RoundRobin_A	725977760	49054	0	1968
ValidKnown_A	725977760	724282096	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	724282096	0	0
T1	6390	6092	0	0
T2	214496	214486	0	0
T3	4686	4578	0	0
T4	521438	521292	0	0
T5	96474	96306	0	0
T9	9258	8256	0	0
T12	7150	5940	0	0
T13	786800	786776	0	0
T18	2590	2452	0	0
T19	55696	55586	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1982	1982	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T9	2	2	0	0
T12	2	2	0	0
T13	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	5287284	0	0
T1	3195	45	0	0
T2	214496	1132	0	0
T3	4686	70	0	0
T4	521438	0	0	0
T5	96474	19349	0	0
T7	0	24550	0	0
T8	0	17945	0	0
T9	9258	0	0	0
T12	7150	0	0	0
T13	786800	0	0	0
T14	1518	0	0	0
T18	2590	0	0	0
T19	55696	618	0	0
T22	0	40952	0	0
T27	0	1354	0	0
T30	0	12474	0	0
T45	0	9588	0	0
T47	0	96	0	0
T48	0	568	0	0
T73	0	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	5287284	0	0
T1	3195	45	0	0
T2	214496	1132	0	0
T3	4686	70	0	0
T4	521438	0	0	0
T5	96474	19349	0	0
T7	0	24550	0	0
T8	0	17945	0	0
T9	9258	0	0	0
T12	7150	0	0	0
T13	786800	0	0	0
T14	1518	0	0	0
T18	2590	0	0	0
T19	55696	618	0	0
T22	0	40952	0	0
T27	0	1354	0	0
T30	0	12474	0	0
T45	0	9588	0	0
T47	0	96	0	0
T48	0	568	0	0
T73	0	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	724282096	0	0
T1	6390	6092	0	0
T2	214496	214486	0	0
T3	4686	4578	0	0
T4	521438	521292	0	0
T5	96474	96306	0	0
T9	9258	8256	0	0
T12	7150	5940	0	0
T13	786800	786776	0	0
T18	2590	2452	0	0
T19	55696	55586	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	724282096	0	0
T1	6390	6092	0	0
T2	214496	214486	0	0
T3	4686	4578	0	0
T4	521438	521292	0	0
T5	96474	96306	0	0
T9	9258	8256	0	0
T12	7150	5940	0	0
T13	786800	786776	0	0
T18	2590	2452	0	0
T19	55696	55586	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	5287284	0	0
T1	3195	45	0	0
T2	214496	1132	0	0
T3	4686	70	0	0
T4	521438	0	0	0
T5	96474	19349	0	0
T7	0	24550	0	0
T8	0	17945	0	0
T9	9258	0	0	0
T12	7150	0	0	0
T13	786800	0	0	0
T14	1518	0	0	0
T18	2590	0	0	0
T19	55696	618	0	0
T22	0	40952	0	0
T27	0	1354	0	0
T30	0	12474	0	0
T45	0	9588	0	0
T47	0	96	0	0
T48	0	568	0	0
T73	0	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	520060789	0	0
T1	6390	4289	0	0
T2	214496	905909	0	0
T3	4686	2695	0	0
T4	521438	521260	0	0
T5	96474	774	0	0
T9	9258	8064	0	0
T12	7150	5763	0	0
T13	786800	760402	0	0
T18	2590	2420	0	0
T19	55696	32904	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	5287284	0	0
T1	3195	45	0	0
T2	214496	1132	0	0
T3	4686	70	0	0
T4	521438	0	0	0
T5	96474	19349	0	0
T7	0	24550	0	0
T8	0	17945	0	0
T9	9258	0	0	0
T12	7150	0	0	0
T13	786800	0	0	0
T14	1518	0	0	0
T18	2590	0	0	0
T19	55696	618	0	0
T22	0	40952	0	0
T27	0	1354	0	0
T30	0	12474	0	0
T45	0	9588	0	0
T47	0	96	0	0
T48	0	568	0	0
T73	0	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	5287284	0	0
T1	3195	45	0	0
T2	214496	1132	0	0
T3	4686	70	0	0
T4	521438	0	0	0
T5	96474	19349	0	0
T7	0	24550	0	0
T8	0	17945	0	0
T9	9258	0	0	0
T12	7150	0	0	0
T13	786800	0	0	0
T14	1518	0	0	0
T18	2590	0	0	0
T19	55696	618	0	0
T22	0	40952	0	0
T27	0	1354	0	0
T30	0	12474	0	0
T45	0	9588	0	0
T47	0	96	0	0
T48	0	568	0	0
T73	0	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	196325892	0	0
T1	3195	1734	0	0
T2	214496	290927	0	0
T3	4686	1847	0	0
T4	521438	0	0	0
T5	96474	95492	0	0
T7	0	235902	0	0
T8	0	102989	0	0
T9	9258	0	0	0
T12	7150	0	0	0
T13	786800	0	0	0
T14	1518	0	0	0
T18	2590	0	0	0
T19	55696	22642	0	0
T22	0	597988	0	0
T27	0	128714	0	0
T30	0	123652	0	0
T45	0	44349	0	0
T47	0	4525	0	0
T48	0	38992	0	0
T73	0	1661	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	49054	0	1968
T22	652162	283	0	2
T27	272810	0	0	2
T30	248694	0	0	2
T31	0	381	0	0
T33	660856	0	0	2
T39	0	1100	0	0
T41	2036	0	0	2
T45	107678	0	0	2
T46	0	519	0	0
T49	10348	0	0	2
T73	5908	0	0	2
T123	0	31	0	0
T124	0	386	0	0
T125	0	254	0	0
T126	0	1521	0	0
T127	0	870	0	0
T128	0	34	0	0
T129	0	1231	0	0
T130	3312	0	0	2
T131	4438	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	724282096	0	0
T1	6390	6092	0	0
T2	214496	214486	0	0
T3	4686	4578	0	0
T4	521438	521292	0	0
T5	96474	96306	0	0
T9	9258	8256	0	0
T12	7150	5940	0	0
T13	786800	786776	0	0
T18	2590	2452	0	0
T19	55696	55586	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T47
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T45,T46
1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T22
1	0	Covered	T7,T8,T22

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T22
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362988880	362141048	0	0
CheckNGreaterZero_A	991	991	0	0
GntImpliesReady_A	362988880	2735272	0	0
GntImpliesValid_A	362988880	2735272	0	0
GrantKnown_A	362988880	362141048	0	0
IdxKnown_A	362988880	362141048	0	0
IndexIsCorrect_A	362988880	2735272	0	0
LockArbDecision_A	362988880	0	0	0
NoReadyValidNoGrant_A	362988880	256252100	0	0
ReadyAndValidImplyGrant_A	362988880	2735272	0	0
ReqAndReadyImplyGrant_A	362988880	2735272	0	0
ReqImpliesValid_A	362988880	101591873	0	0
ReqStaysHighUntilGranted0_M	362988880	0	0	0
RoundRobin_A	362988880	30094	0	984
ValidKnown_A	362988880	362141048	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2735272	0	0
T1	3195	45	0	0
T2	107248	1069	0	0
T3	2343	70	0	0
T4	260719	0	0	0
T5	48237	9878	0	0
T7	0	12317	0	0
T8	0	9801	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T18	1295	0	0	0
T19	27848	386	0	0
T22	0	20590	0	0
T47	0	96	0	0
T48	0	568	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2735272	0	0
T1	3195	45	0	0
T2	107248	1069	0	0
T3	2343	70	0	0
T4	260719	0	0	0
T5	48237	9878	0	0
T7	0	12317	0	0
T8	0	9801	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T18	1295	0	0	0
T19	27848	386	0	0
T22	0	20590	0	0
T47	0	96	0	0
T48	0	568	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2735272	0	0
T1	3195	45	0	0
T2	107248	1069	0	0
T3	2343	70	0	0
T4	260719	0	0	0
T5	48237	9878	0	0
T7	0	12317	0	0
T8	0	9801	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T18	1295	0	0	0
T19	27848	386	0	0
T22	0	20590	0	0
T47	0	96	0	0
T48	0	568	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	256252100	0	0
T1	3195	1243	0	0
T2	107248	886787	0	0
T3	2343	406	0	0
T4	260719	260614	0	0
T5	48237	369	0	0
T9	4629	3936	0	0
T12	3575	2793	0	0
T13	393400	380121	0	0
T18	1295	1194	0	0
T19	27848	16369	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2735272	0	0
T1	3195	45	0	0
T2	107248	1069	0	0
T3	2343	70	0	0
T4	260719	0	0	0
T5	48237	9878	0	0
T7	0	12317	0	0
T8	0	9801	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T18	1295	0	0	0
T19	27848	386	0	0
T22	0	20590	0	0
T47	0	96	0	0
T48	0	568	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2735272	0	0
T1	3195	45	0	0
T2	107248	1069	0	0
T3	2343	70	0	0
T4	260719	0	0	0
T5	48237	9878	0	0
T7	0	12317	0	0
T8	0	9801	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T18	1295	0	0	0
T19	27848	386	0	0
T22	0	20590	0	0
T47	0	96	0	0
T48	0	568	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	101591873	0	0
T1	3195	1734	0	0
T2	107248	185597	0	0
T3	2343	1847	0	0
T4	260719	0	0	0
T5	48237	47748	0	0
T7	0	117946	0	0
T8	0	51491	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T18	1295	0	0	0
T19	27848	11388	0	0
T22	0	301476	0	0
T47	0	4525	0	0
T48	0	38992	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	30094	0	984
T22	326081	184	0	1
T27	136405	0	0	1
T30	124347	0	0	1
T33	330428	0	0	1
T39	0	1005	0	0
T41	1018	0	0	1
T45	53839	0	0	1
T46	0	347	0	0
T49	5174	0	0	1
T73	2954	0	0	1
T123	0	31	0	0
T124	0	162	0	0
T125	0	159	0	0
T126	0	634	0	0
T127	0	133	0	0
T128	0	23	0	0
T129	0	526	0	0
T130	1656	0	0	1
T131	2219	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T5,T19
1	1	Covered	T2,T5,T19

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T5,T19
1	1	Covered	T2,T5,T19

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T5,T19
1	1	Covered	T2,T5,T19

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T22,T45,T46
1	1	Covered	T2,T5,T19

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T19
1	1	0	Covered	T2,T5,T19
1	1	1	Covered	T2,T5,T19

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T19
1	1	0	Covered	T2,T5,T19
1	1	1	Covered	T2,T5,T19

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T19
1	1	0	Covered	T2,T5,T19
1	1	1	Covered	T2,T5,T19

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T13,T5
1	0	1	Covered	T2,T5,T19
1	1	0	Covered	T2,T5,T19
1	1	1	Covered	T2,T5,T19

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T19

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T19
0	1	Covered	T2,T5,T19
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19
1	1	Covered	T2,T5,T19

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T19

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T19
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19
1	1	Covered	T2,T5,T19

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T19

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T19
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19
1	1	Covered	T2,T5,T19

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T19

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T19
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19
1	1	Covered	T2,T5,T19

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T19
0	1	Covered	T2,T5,T19
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T19

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T19
0	1	Covered	T2,T5,T19
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T19

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T19
0	1	Covered	T2,T5,T19
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T19

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T22
1	0	Covered	T7,T8,T22

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T22
1	0	Covered	T2,T5,T19

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T5,T19

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T19
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T19
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T5,T19
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T19
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T19
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T5,T19
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T19

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19
1	1	Covered	T2,T5,T19

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T19

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T2,T5,T19
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T19
1	1	Covered	T2,T5,T19

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T5,T19
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T19
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T19
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T19
1	0	Covered	T2,T5,T19

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T19

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T19

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T19

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T19

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T19

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T19

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362988880	362141048	0	0
CheckNGreaterZero_A	991	991	0	0
GntImpliesReady_A	362988880	2552012	0	0
GntImpliesValid_A	362988880	2552012	0	0
GrantKnown_A	362988880	362141048	0	0
IdxKnown_A	362988880	362141048	0	0
IndexIsCorrect_A	362988880	2552012	0	0
LockArbDecision_A	362988880	0	0	0
NoReadyValidNoGrant_A	362988880	263808689	0	0
ReadyAndValidImplyGrant_A	362988880	2552012	0	0
ReqAndReadyImplyGrant_A	362988880	2552012	0	0
ReqImpliesValid_A	362988880	94734019	0	0
ReqStaysHighUntilGranted0_M	362988880	0	0	0
RoundRobin_A	362988880	18960	0	984
ValidKnown_A	362988880	362141048	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2552012	0	0
T2	107248	63	0	0
T3	2343	0	0	0
T4	260719	0	0	0
T5	48237	9471	0	0
T7	0	12233	0	0
T8	0	8144	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	232	0	0
T22	0	20362	0	0
T27	0	1354	0	0
T30	0	12474	0	0
T45	0	9588	0	0
T73	0	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2552012	0	0
T2	107248	63	0	0
T3	2343	0	0	0
T4	260719	0	0	0
T5	48237	9471	0	0
T7	0	12233	0	0
T8	0	8144	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	232	0	0
T22	0	20362	0	0
T27	0	1354	0	0
T30	0	12474	0	0
T45	0	9588	0	0
T73	0	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2552012	0	0
T2	107248	63	0	0
T3	2343	0	0	0
T4	260719	0	0	0
T5	48237	9471	0	0
T7	0	12233	0	0
T8	0	8144	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	232	0	0
T22	0	20362	0	0
T27	0	1354	0	0
T30	0	12474	0	0
T45	0	9588	0	0
T73	0	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	263808689	0	0
T1	3195	3046	0	0
T2	107248	19122	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	405	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	380281	0	0
T18	1295	1226	0	0
T19	27848	16535	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2552012	0	0
T2	107248	63	0	0
T3	2343	0	0	0
T4	260719	0	0	0
T5	48237	9471	0	0
T7	0	12233	0	0
T8	0	8144	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	232	0	0
T22	0	20362	0	0
T27	0	1354	0	0
T30	0	12474	0	0
T45	0	9588	0	0
T73	0	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2552012	0	0
T2	107248	63	0	0
T3	2343	0	0	0
T4	260719	0	0	0
T5	48237	9471	0	0
T7	0	12233	0	0
T8	0	8144	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	232	0	0
T22	0	20362	0	0
T27	0	1354	0	0
T30	0	12474	0	0
T45	0	9588	0	0
T73	0	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	94734019	0	0
T2	107248	105330	0	0
T3	2343	0	0	0
T4	260719	0	0	0
T5	48237	47744	0	0
T7	0	117956	0	0
T8	0	51498	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	27848	11254	0	0
T22	0	296512	0	0
T27	0	128714	0	0
T30	0	123652	0	0
T45	0	44349	0	0
T73	0	1661	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	18960	0	984
T22	326081	99	0	1
T27	136405	0	0	1
T30	124347	0	0	1
T31	0	381	0	0
T33	330428	0	0	1
T39	0	95	0	0
T41	1018	0	0	1
T45	53839	0	0	1
T46	0	172	0	0
T49	5174	0	0	1
T73	2954	0	0	1
T124	0	224	0	0
T125	0	95	0	0
T126	0	887	0	0
T127	0	737	0	0
T128	0	11	0	0
T129	0	705	0	0
T130	1656	0	0	1
T131	2219	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0