Line Coverage for Module :
flash_ctrl_lcmgr
| Line No. | Total | Covered | Percent |
TOTAL | | 242 | 239 | 98.76 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 152 | 3 | 3 | 100.00 |
CONT_ASSIGN | 170 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
ALWAYS | 174 | 7 | 7 | 100.00 |
CONT_ASSIGN | 185 | 1 | 1 | 100.00 |
ALWAYS | 227 | 5 | 5 | 100.00 |
CONT_ASSIGN | 243 | 1 | 1 | 100.00 |
CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
ALWAYS | 251 | 3 | 3 | 100.00 |
CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
CONT_ASSIGN | 262 | 1 | 1 | 100.00 |
ALWAYS | 264 | 6 | 6 | 100.00 |
CONT_ASSIGN | 278 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
ALWAYS | 359 | 9 | 9 | 100.00 |
CONT_ASSIGN | 380 | 1 | 1 | 100.00 |
ALWAYS | 386 | 85 | 84 | 98.82 |
CONT_ASSIGN | 607 | 1 | 1 | 100.00 |
ALWAYS | 613 | 3 | 3 | 100.00 |
ALWAYS | 673 | 7 | 7 | 100.00 |
ALWAYS | 688 | 10 | 10 | 100.00 |
ALWAYS | 705 | 2 | 2 | 100.00 |
CONT_ASSIGN | 714 | 1 | 1 | 100.00 |
CONT_ASSIGN | 715 | 1 | 1 | 100.00 |
CONT_ASSIGN | 737 | 1 | 1 | 100.00 |
CONT_ASSIGN | 741 | 1 | 1 | 100.00 |
CONT_ASSIGN | 742 | 1 | 1 | 100.00 |
CONT_ASSIGN | 754 | 1 | 1 | 100.00 |
ALWAYS | 761 | 66 | 64 | 96.97 |
CONT_ASSIGN | 891 | 1 | 1 | 100.00 |
CONT_ASSIGN | 892 | 1 | 1 | 100.00 |
CONT_ASSIGN | 893 | 1 | 1 | 100.00 |
CONT_ASSIGN | 894 | 0 | 0 | |
CONT_ASSIGN | 895 | 0 | 0 | |
CONT_ASSIGN | 896 | 1 | 1 | 100.00 |
CONT_ASSIGN | 897 | 1 | 1 | 100.00 |
CONT_ASSIGN | 898 | 1 | 1 | 100.00 |
CONT_ASSIGN | 900 | 1 | 1 | 100.00 |
CONT_ASSIGN | 902 | 1 | 1 | 100.00 |
CONT_ASSIGN | 905 | 1 | 1 | 100.00 |
CONT_ASSIGN | 906 | 1 | 1 | 100.00 |
CONT_ASSIGN | 908 | 1 | 1 | 100.00 |
CONT_ASSIGN | 909 | 1 | 1 | 100.00 |
CONT_ASSIGN | 911 | 1 | 1 | 100.00 |
CONT_ASSIGN | 914 | 1 | 1 | 100.00 |
CONT_ASSIGN | 918 | 1 | 1 | 100.00 |
CONT_ASSIGN | 921 | 1 | 1 | 100.00 |
ALWAYS | 932 | 0 | 0 | |
CONT_ASSIGN | 939 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
149 |
1 |
1 |
152 |
3 |
3 |
170 |
1 |
1 |
171 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
181 |
1 |
1 |
185 |
1 |
1 |
227 |
1 |
1 |
228 |
1 |
1 |
229 |
1 |
1 |
231 |
1 |
1 |
232 |
1 |
1 |
243 |
1 |
1 |
247 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
254 |
1 |
1 |
261 |
1 |
1 |
262 |
1 |
1 |
264 |
1 |
1 |
265 |
1 |
1 |
266 |
1 |
1 |
268 |
1 |
1 |
270 |
1 |
1 |
271 |
1 |
1 |
|
|
|
MISSING_ELSE |
278 |
1 |
1 |
279 |
1 |
1 |
280 |
1 |
1 |
359 |
1 |
1 |
360 |
1 |
1 |
361 |
1 |
1 |
363 |
1 |
1 |
364 |
1 |
1 |
365 |
1 |
1 |
|
|
|
MISSING_ELSE |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
|
|
|
MISSING_ELSE |
380 |
1 |
1 |
386 |
1 |
1 |
389 |
1 |
1 |
390 |
1 |
1 |
391 |
1 |
1 |
392 |
1 |
1 |
395 |
1 |
1 |
396 |
1 |
1 |
397 |
1 |
1 |
398 |
1 |
1 |
399 |
1 |
1 |
402 |
1 |
1 |
404 |
1 |
1 |
405 |
1 |
1 |
406 |
1 |
1 |
409 |
1 |
1 |
411 |
1 |
1 |
412 |
1 |
1 |
415 |
1 |
1 |
416 |
1 |
1 |
419 |
1 |
1 |
420 |
1 |
1 |
423 |
1 |
1 |
425 |
1 |
1 |
427 |
1 |
1 |
433 |
1 |
1 |
434 |
1 |
1 |
435 |
1 |
1 |
436 |
1 |
1 |
|
|
|
MISSING_ELSE |
441 |
1 |
1 |
442 |
1 |
1 |
443 |
1 |
1 |
444 |
1 |
1 |
445 |
1 |
1 |
446 |
1 |
1 |
|
|
|
MISSING_ELSE |
451 |
1 |
1 |
452 |
1 |
1 |
453 |
1 |
1 |
454 |
1 |
1 |
455 |
1 |
1 |
457 |
1 |
1 |
|
|
|
MISSING_ELSE |
464 |
1 |
1 |
467 |
1 |
1 |
468 |
1 |
1 |
469 |
1 |
1 |
472 |
1 |
1 |
473 |
1 |
1 |
474 |
1 |
1 |
475 |
1 |
1 |
476 |
1 |
1 |
477 |
1 |
1 |
478 |
1 |
1 |
|
|
|
MISSING_ELSE |
483 |
1 |
1 |
484 |
1 |
1 |
485 |
1 |
1 |
487 |
1 |
1 |
488 |
1 |
1 |
489 |
1 |
1 |
491 |
1 |
1 |
497 |
1 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
|
|
|
MISSING_ELSE |
505 |
1 |
1 |
506 |
1 |
1 |
507 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
512 |
1 |
1 |
513 |
1 |
1 |
514 |
1 |
1 |
516 |
1 |
1 |
520 |
1 |
1 |
521 |
1 |
1 |
522 |
1 |
1 |
|
|
|
MISSING_ELSE |
531 |
1 |
1 |
532 |
1 |
1 |
533 |
1 |
1 |
534 |
0 |
1 |
536 |
1 |
1 |
543 |
1 |
1 |
544 |
1 |
1 |
545 |
1 |
1 |
549 |
1 |
1 |
550 |
1 |
1 |
551 |
1 |
1 |
552 |
1 |
1 |
569 |
1 |
1 |
572 |
1 |
1 |
|
|
|
MISSING_ELSE |
607 |
1 |
1 |
613 |
3 |
3 |
673 |
1 |
1 |
674 |
1 |
1 |
675 |
1 |
1 |
676 |
1 |
1 |
678 |
1 |
1 |
679 |
1 |
1 |
680 |
1 |
1 |
688 |
1 |
1 |
689 |
1 |
1 |
690 |
1 |
1 |
691 |
1 |
1 |
692 |
1 |
1 |
693 |
1 |
1 |
694 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
696 |
1 |
1 |
697 |
1 |
1 |
698 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
705 |
1 |
1 |
706 |
1 |
1 |
|
|
|
MISSING_ELSE |
714 |
1 |
1 |
715 |
1 |
1 |
737 |
1 |
1 |
741 |
1 |
1 |
742 |
1 |
1 |
754 |
1 |
1 |
761 |
1 |
1 |
762 |
1 |
1 |
763 |
1 |
1 |
764 |
1 |
1 |
765 |
1 |
1 |
766 |
1 |
1 |
767 |
1 |
1 |
768 |
1 |
1 |
769 |
1 |
1 |
770 |
1 |
1 |
771 |
1 |
1 |
772 |
1 |
1 |
773 |
1 |
1 |
774 |
1 |
1 |
775 |
1 |
1 |
777 |
1 |
1 |
784 |
1 |
1 |
785 |
1 |
1 |
786 |
1 |
1 |
787 |
1 |
1 |
788 |
1 |
1 |
|
|
|
MISSING_ELSE |
793 |
1 |
1 |
794 |
0 |
1 |
795 |
1 |
1 |
796 |
1 |
1 |
798 |
1 |
1 |
799 |
1 |
1 |
800 |
1 |
1 |
805 |
1 |
1 |
806 |
1 |
1 |
807 |
1 |
1 |
808 |
1 |
1 |
809 |
1 |
1 |
|
|
|
MISSING_ELSE |
814 |
1 |
1 |
815 |
1 |
1 |
819 |
1 |
1 |
820 |
0 |
1 |
821 |
1 |
1 |
822 |
1 |
1 |
824 |
1 |
1 |
825 |
1 |
1 |
826 |
1 |
1 |
831 |
1 |
1 |
832 |
1 |
1 |
833 |
1 |
1 |
835 |
1 |
1 |
836 |
1 |
1 |
|
|
|
MISSING_ELSE |
841 |
1 |
1 |
842 |
1 |
1 |
844 |
1 |
1 |
845 |
1 |
1 |
846 |
1 |
1 |
847 |
1 |
1 |
|
|
|
MISSING_ELSE |
852 |
1 |
1 |
853 |
1 |
1 |
854 |
1 |
1 |
856 |
1 |
1 |
857 |
1 |
1 |
858 |
1 |
1 |
859 |
1 |
1 |
|
|
|
MISSING_ELSE |
862 |
1 |
1 |
863 |
1 |
1 |
|
|
|
MISSING_ELSE |
868 |
1 |
1 |
872 |
1 |
1 |
873 |
1 |
1 |
874 |
1 |
1 |
891 |
1 |
1 |
892 |
1 |
1 |
893 |
1 |
1 |
894 |
|
unreachable |
895 |
|
unreachable |
896 |
1 |
1 |
897 |
1 |
1 |
898 |
1 |
1 |
900 |
1 |
1 |
902 |
1 |
1 |
905 |
1 |
1 |
906 |
1 |
1 |
908 |
1 |
1 |
909 |
1 |
1 |
911 |
1 |
1 |
914 |
1 |
1 |
918 |
1 |
1 |
921 |
1 |
1 |
932 |
|
unreachable |
933 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
939 |
1 |
1 |
Cond Coverage for Module :
flash_ctrl_lcmgr
| Total | Covered | Percent |
Conditions | 96 | 87 | 90.62 |
Logical | 96 | 87 | 90.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 170
EXPRESSION (phase == PhaseSeed)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 171
EXPRESSION (phase == PhaseRma)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T13,T63 |
LINE 185
EXPRESSION (seed_err_q | seed_err_d)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T67,T80,T81 |
1 | 0 | Not Covered | |
LINE 231
EXPRESSION (addr_cnt_err_q | addr_cnt_err_d)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T15,T16,T17 |
1 | 0 | Covered | T15,T16,T17 |
LINE 232
EXPRESSION (seed_cnt_err_q | seed_cnt_err_d)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T15,T16,T17 |
1 | 0 | Covered | T15,T16,T17 |
LINE 247
EXPRESSION (data_invalid_q | (rvalid_i & ((~data_intg_ok))))
-------1------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T14,T82,T83 |
1 | 0 | Covered | T14,T82,T83 |
LINE 247
SUB-EXPRESSION (rvalid_i & ((~data_intg_ok)))
----1--- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T82,T83 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T14,T82,T83 |
LINE 266
EXPRESSION (seed_phase && validate_q && rvalid_i)
-----1---- -----2---- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 270
EXPRESSION (seed_phase && rvalid_i)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T15,T84 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 363
EXPRESSION (addr_key_req_d && addr_key_ack_q)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T64,T85,T86 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 368
EXPRESSION (data_key_req_d && data_key_ack_q)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T87,T88,T86 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 457
EXPRESSION (provision_en_i ? StReadSeeds : StWait)
-------1------
-1- | Status | Tests |
0 | Covered | T89,T87,T90 |
1 | Covered | T1,T2,T3 |
LINE 473
EXPRESSION (seed_cnt_q == flash_ctrl_pkg::NumSeeds)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 516
EXPRESSION ((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)
--------------------------1------------------------- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T84,T91 |
1 | 0 | Covered | T13,T84,T91 |
1 | 1 | Covered | T13,T84,T91 |
LINE 516
SUB-EXPRESSION (rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0])
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T12,T13,T63 |
1 | Covered | T13,T84,T91 |
LINE 678
EXPRESSION (page_err_q | page_err_d)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T15,T16,T17 |
1 | 0 | Covered | T15,T16,T17 |
LINE 679
EXPRESSION (word_err_q | word_err_d)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T15,T16,T17 |
1 | 0 | Covered | T15,T16,T17 |
LINE 680
EXPRESSION (rma_idx_err_q | rma_idx_err_d)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T15,T16,T17 |
1 | 0 | Covered | T15,T16,T17 |
LINE 693
EXPRESSION (wvalid_o && wready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T13,T92,T84 |
LINE 697
EXPRESSION (rvalid_i && rready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T84,T91 |
1 | 0 | Unreachable | |
1 | 1 | Covered | T13,T84,T91 |
LINE 705
EXPRESSION (prog_cnt_en && wvalid_o && wready_i)
-----1----- ----2--- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T13,T92,T84 |
LINE 835
EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)
-----------------------1---------------------- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T92,T84 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T13,T92,T84 |
LINE 835
SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T13,T92,T84 |
1 | Covered | T13,T92,T84 |
LINE 856
EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)
-----------------------1---------------------- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T13,T84,T91 |
1 | 1 | Covered | T13,T84,T91 |
LINE 856
SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T13,T84,T91 |
1 | Covered | T13,T84,T91 |
LINE 862
EXPRESSION (rvalid_i && rready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T84,T91 |
1 | 0 | Unreachable | |
1 | 1 | Covered | T13,T84,T91 |
LINE 863
EXPRESSION (prog_data[beat_cnt] != rdata_i[(flash_ctrl_pkg::BusWidth - 1):0])
---------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T13,T84,T91 |
1 | Covered | T93,T94,T95 |
LINE 892
EXPRESSION (seed_phase ? start : rma_start)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 893
EXPRESSION (seed_phase ? op : rma_op)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 896
EXPRESSION (seed_phase ? part_sel : rma_part_sel)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 897
EXPRESSION (seed_phase ? info_sel : rma_info_sel)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 898
EXPRESSION (seed_phase ? num_words : rma_num_words)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 900
EXPRESSION (seed_phase ? ({addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}) : ({rma_addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 906
EXPRESSION (seed_phase | rma_phase)
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T12,T13,T63 |
1 | 0 | Covered | T1,T2,T3 |
LINE 914
EXPRESSION (page_err_q | word_err_q | fsm_err | state_err | rma_idx_err_q | addr_cnt_err_q | seed_cnt_err_q)
-----1---- -----2---- ---3--- ----4---- ------5------ -------6------ -------7------
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | Covered | T15,T16,T17 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | Covered | T15,T16,T17 |
0 | 0 | 0 | 0 | 1 | 0 | 0 | Covered | T15,T16,T17 |
0 | 0 | 0 | 1 | 0 | 0 | 0 | Covered | T15,T93,T16 |
0 | 0 | 1 | 0 | 0 | 0 | 0 | Covered | T15,T16,T17 |
0 | 1 | 0 | 0 | 0 | 0 | 0 | Covered | T15,T16,T17 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T15,T16,T17 |
FSM Coverage for Module :
flash_ctrl_lcmgr
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
11 |
11 |
100.00 |
(Not included in score) |
Transitions |
25 |
21 |
84.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
StDisabled |
545 |
Covered |
T12,T9,T14 |
StEntropyReseed |
499 |
Covered |
T12,T13,T63 |
StIdle |
432 |
Covered |
T1,T2,T3 |
StInvalid |
520 |
Covered |
T15,T93,T16 |
StReadEval |
478 |
Covered |
T1,T2,T3 |
StReadSeeds |
457 |
Covered |
T1,T2,T3 |
StReqAddrKey |
436 |
Covered |
T1,T2,T3 |
StReqDataKey |
446 |
Covered |
T1,T2,T3 |
StRmaRsp |
520 |
Covered |
T13,T84,T91 |
StRmaWipe |
434 |
Covered |
T12,T13,T63 |
StWait |
457 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
StEntropyReseed->StDisabled |
572 |
Covered |
T63,T96,T89 |
StEntropyReseed->StRmaWipe |
507 |
Covered |
T12,T13,T63 |
StIdle->StDisabled |
572 |
Covered |
T15,T16,T17 |
StIdle->StReqAddrKey |
436 |
Covered |
T1,T2,T3 |
StIdle->StRmaWipe |
434 |
Covered |
T92,T97,T98 |
StInvalid->StDisabled |
572 |
Not Covered |
|
StReadEval->StDisabled |
572 |
Covered |
T12,T64,T99 |
StReadEval->StReadSeeds |
485 |
Covered |
T1,T2,T3 |
StReadSeeds->StDisabled |
572 |
Covered |
T14,T82,T83 |
StReadSeeds->StReadEval |
478 |
Covered |
T1,T2,T3 |
StReadSeeds->StWait |
475 |
Covered |
T1,T2,T3 |
StReqAddrKey->StDisabled |
572 |
Not Covered |
|
StReqAddrKey->StReqDataKey |
446 |
Covered |
T1,T2,T3 |
StReqAddrKey->StRmaWipe |
444 |
Covered |
T64,T85,T86 |
StReqDataKey->StDisabled |
572 |
Not Covered |
|
StReqDataKey->StReadSeeds |
457 |
Covered |
T1,T2,T3 |
StReqDataKey->StRmaWipe |
454 |
Covered |
T87,T88,T86 |
StReqDataKey->StWait |
457 |
Covered |
T89,T87,T90 |
StRmaRsp->StDisabled |
572 |
Covered |
T84,T91 |
StRmaRsp->StInvalid |
534 |
Not Covered |
|
StRmaWipe->StDisabled |
572 |
Covered |
T97,T100,T101 |
StRmaWipe->StInvalid |
520 |
Covered |
T93,T102,T103 |
StRmaWipe->StRmaRsp |
520 |
Covered |
T13,T84,T91 |
StWait->StDisabled |
572 |
Covered |
T9,T104,T105 |
StWait->StEntropyReseed |
499 |
Covered |
T12,T13,T63 |
Summary for FSM :: rma_state_q
| Total | Covered | Percent | |
States |
10 |
10 |
100.00 |
(Not included in score) |
Transitions |
13 |
11 |
84.62 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: rma_state_q
states | Line No. | Covered | Tests |
StRmaDisabled |
785 |
Covered |
T12,T13,T9 |
StRmaErase |
796 |
Covered |
T12,T13,T63 |
StRmaEraseWait |
809 |
Covered |
T13,T92,T84 |
StRmaIdle |
800 |
Covered |
T1,T2,T3 |
StRmaInvalid |
872 |
Covered |
T15,T16,T17 |
StRmaPageSel |
787 |
Covered |
T12,T13,T63 |
StRmaProgram |
822 |
Covered |
T13,T92,T84 |
StRmaProgramWait |
836 |
Covered |
T13,T92,T84 |
StRmaRdVerify |
847 |
Covered |
T13,T84,T91 |
StRmaWordSel |
815 |
Covered |
T13,T92,T84 |
transitions | Line No. | Covered | Tests |
StRmaErase->StRmaEraseWait |
809 |
Covered |
T13,T92,T84 |
StRmaEraseWait->StRmaWordSel |
815 |
Covered |
T13,T92,T84 |
StRmaIdle->StRmaDisabled |
785 |
Covered |
T12,T13,T9 |
StRmaIdle->StRmaPageSel |
787 |
Covered |
T12,T13,T63 |
StRmaPageSel->StRmaDisabled |
794 |
Not Covered |
|
StRmaPageSel->StRmaErase |
796 |
Covered |
T12,T13,T63 |
StRmaPageSel->StRmaIdle |
800 |
Covered |
T13,T84,T91 |
StRmaProgram->StRmaProgramWait |
836 |
Covered |
T13,T92,T84 |
StRmaProgramWait->StRmaRdVerify |
847 |
Covered |
T13,T84,T91 |
StRmaRdVerify->StRmaWordSel |
859 |
Covered |
T13,T84,T91 |
StRmaWordSel->StRmaDisabled |
820 |
Not Covered |
|
StRmaWordSel->StRmaPageSel |
826 |
Covered |
T13,T84,T91 |
StRmaWordSel->StRmaProgram |
822 |
Covered |
T13,T92,T84 |
Branch Coverage for Module :
flash_ctrl_lcmgr
| Line No. | Total | Covered | Percent |
Branches |
|
94 |
89 |
94.68 |
TERNARY |
892 |
2 |
2 |
100.00 |
TERNARY |
893 |
2 |
2 |
100.00 |
TERNARY |
896 |
2 |
2 |
100.00 |
TERNARY |
897 |
2 |
2 |
100.00 |
TERNARY |
898 |
2 |
2 |
100.00 |
TERNARY |
900 |
2 |
2 |
100.00 |
IF |
152 |
2 |
2 |
100.00 |
IF |
174 |
2 |
2 |
100.00 |
IF |
227 |
2 |
2 |
100.00 |
IF |
251 |
2 |
2 |
100.00 |
IF |
264 |
4 |
4 |
100.00 |
IF |
359 |
5 |
5 |
100.00 |
CASE |
427 |
27 |
25 |
92.59 |
IF |
569 |
2 |
2 |
100.00 |
IF |
613 |
2 |
2 |
100.00 |
IF |
673 |
2 |
2 |
100.00 |
IF |
688 |
7 |
6 |
85.71 |
IF |
705 |
2 |
2 |
100.00 |
CASE |
777 |
23 |
21 |
91.30 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 892 (seed_phase) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 893 (seed_phase) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 896 (seed_phase) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 897 (seed_phase) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 898 (seed_phase) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 900 (seed_phase) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 152 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 174 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 227 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 251 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 264 if ((!rst_ni))
-2-: 266 if (((seed_phase && validate_q) && rvalid_i))
-3-: 270 if ((seed_phase && rvalid_i))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 359 if ((!rst_ni))
-2-: 363 if ((addr_key_req_d && addr_key_ack_q))
-3-: 368 if ((data_key_req_d && data_key_ack_q))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 427 case (state_q)
-2-: 433 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqInit]))
-3-: 435 if (init_q)
-4-: 443 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey]))
-5-: 445 if (addr_key_ack_q)
-6-: 453 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey]))
-7-: 455 if (data_key_ack_q)
-8-: 457 (provision_en_i) ?
-9-: 473 if ((seed_cnt_q == flash_ctrl_pkg::NumSeeds))
-10-: 476 if (done_i)
-11-: 487 if (validate_q)
-12-: 498 if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqWait]))
-13-: 506 if (edn_ack_i)
-14-: 516 if (((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done))
-15-: 521 if (rma_wipe_done)
-16-: 533 if (lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | Status | Tests |
StIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T92,T97,T98 |
StIdle |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReqAddrKey |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T64,T85,T86 |
StReqAddrKey |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReqAddrKey |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReqDataKey |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T87,T88,T86 |
StReqDataKey |
- |
- |
- |
- |
0 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReqDataKey |
- |
- |
- |
- |
0 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T89,T87,T90 |
StReqDataKey |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReadSeeds |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReadSeeds |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReadSeeds |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReadEval |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReadEval |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T12,T13,T63 |
StWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StEntropyReseed |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T12,T13,T63 |
StEntropyReseed |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Not Covered |
|
StRmaWipe |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T13,T84,T91 |
StRmaWipe |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T13,T84,T91 |
StRmaWipe |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T12,T13,T63 |
StRmaRsp |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Not Covered |
|
StRmaRsp |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T13,T84,T91 |
StDisabled |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T12,T9,T14 |
StInvalid |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T15,T93,T16 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T15,T16,T17 |
LineNo. Expression
-1-: 569 if (((prim_mubi_pkg::mubi4_test_true_loose(disable_i) && (state_d != StInvalid)) && (!rma_done)))
Branches:
-1- | Status | Tests |
1 |
Covered |
T12,T9,T14 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 613 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 673 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 688 if ((!rst_ni))
-2-: 690 if (beat_cnt_clr)
-3-: 692 if (prog_cnt_en)
-4-: 693 if ((wvalid_o && wready_i))
-5-: 696 if (rd_cnt_en)
-6-: 697 if ((rvalid_i && rready_o))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
- |
Covered |
T13,T84,T91 |
0 |
0 |
1 |
1 |
- |
- |
Covered |
T13,T92,T84 |
0 |
0 |
1 |
0 |
- |
- |
Not Covered |
|
0 |
0 |
0 |
- |
1 |
1 |
Covered |
T13,T84,T91 |
0 |
0 |
0 |
- |
1 |
0 |
Covered |
T13,T84,T91 |
0 |
0 |
0 |
- |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 705 if (((prog_cnt_en && wvalid_o) && wready_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T13,T92,T84 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 777 case (rma_state_q)
-2-: 784 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-: 786 if (rma_wipe_req_int)
-4-: 793 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-5-: 795 if ((page_cnt < end_page))
-6-: 807 if (done_i)
-7-: 819 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-8-: 821 if ((word_cnt < flash_ctrl_pkg::BusWordsPerPage))
-9-: 835 if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i))
-10-: 844 if (done_i)
-11-: 856 if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i))
-12-: 862 if ((rvalid_i && rready_o))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | Status | Tests |
StRmaIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T12,T13,T9 |
StRmaIdle |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T12,T13,T63 |
StRmaIdle |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StRmaPageSel |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StRmaPageSel |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T12,T13,T63 |
StRmaPageSel |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T84,T91 |
StRmaErase |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T13,T92,T84 |
StRmaErase |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T12,T13,T63 |
StRmaEraseWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T92,T84 |
StRmaWordSel |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Not Covered |
|
StRmaWordSel |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
Covered |
T13,T92,T84 |
StRmaWordSel |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T13,T84,T91 |
StRmaProgram |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T13,T92,T84 |
StRmaProgram |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T13,T92,T84 |
StRmaProgramWait |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T13,T84,T91 |
StRmaProgramWait |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T13,T92,T84 |
StRmaRdVerify |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T13,T84,T91 |
StRmaRdVerify |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T13,T84,T91 |
StRmaRdVerify |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T13,T84,T91 |
StRmaRdVerify |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T13,T84,T91 |
StRmaDisabled |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T12,T13,T9 |
StRmaInvalid |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T15,T16,T17 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T15,T16,T17 |
Assert Coverage for Module :
flash_ctrl_lcmgr
Assertion Details
DisableChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
350118667 |
4261792 |
0 |
23 |
T5 |
48237 |
0 |
0 |
0 |
T7 |
118703 |
0 |
0 |
0 |
T9 |
4629 |
555 |
0 |
0 |
T12 |
3575 |
2 |
0 |
0 |
T13 |
393400 |
0 |
0 |
0 |
T14 |
1518 |
3 |
0 |
0 |
T15 |
0 |
41995 |
0 |
0 |
T18 |
1295 |
0 |
0 |
0 |
T19 |
27848 |
0 |
0 |
0 |
T32 |
0 |
0 |
0 |
1 |
T47 |
10150 |
0 |
0 |
0 |
T48 |
171418 |
0 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T82 |
0 |
3 |
0 |
0 |
T83 |
0 |
3 |
0 |
0 |
T96 |
0 |
1 |
0 |
0 |
T97 |
0 |
240182 |
0 |
0 |
T104 |
0 |
0 |
0 |
1 |
T105 |
0 |
0 |
0 |
1 |
T106 |
0 |
0 |
0 |
1 |
T107 |
0 |
0 |
0 |
1 |
T108 |
0 |
0 |
0 |
1 |
T109 |
0 |
0 |
0 |
1 |
T110 |
0 |
0 |
0 |
1 |
T111 |
0 |
0 |
0 |
1 |
T112 |
0 |
0 |
0 |
1 |
ProgRdVerify_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347077776 |
1516183 |
0 |
0 |
T5 |
48237 |
0 |
0 |
0 |
T6 |
211270 |
0 |
0 |
0 |
T7 |
118703 |
0 |
0 |
0 |
T9 |
4629 |
0 |
0 |
0 |
T13 |
393400 |
65920 |
0 |
0 |
T14 |
1518 |
0 |
0 |
0 |
T18 |
1295 |
0 |
0 |
0 |
T19 |
27848 |
0 |
0 |
0 |
T47 |
10150 |
0 |
0 |
0 |
T48 |
171418 |
0 |
0 |
0 |
T84 |
0 |
65920 |
0 |
0 |
T91 |
0 |
65920 |
0 |
0 |
T113 |
0 |
65920 |
0 |
0 |
T114 |
0 |
65920 |
0 |
0 |
T115 |
0 |
65920 |
0 |
0 |
T116 |
0 |
65920 |
0 |
0 |
T117 |
0 |
65920 |
0 |
0 |
T118 |
0 |
65920 |
0 |
0 |
T119 |
0 |
131840 |
0 |
0 |
u_rma_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988907 |
362141075 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
362988907 |
362141075 |
0 |
0 |
T1 |
3195 |
3046 |
0 |
0 |
T2 |
107248 |
107243 |
0 |
0 |
T3 |
2343 |
2289 |
0 |
0 |
T4 |
260719 |
260646 |
0 |
0 |
T5 |
48237 |
48153 |
0 |
0 |
T9 |
4629 |
4128 |
0 |
0 |
T12 |
3575 |
2970 |
0 |
0 |
T13 |
393400 |
393388 |
0 |
0 |
T18 |
1295 |
1226 |
0 |
0 |
T19 |
27848 |
27793 |
0 |
0 |