SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.22 | 97.14 | 92.20 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
93.66 | 98.76 | 90.62 | 84.21 | 94.68 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
72.41 | 88.24 | 83.33 | 57.14 | 83.33 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.22 | 97.14 | 92.20 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
72.29 | 86.27 | 88.89 | 57.14 | 79.17 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.26 | 97.67 | 85.11 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 9910 | 9910 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 20412 |
gen_no_flops.OutputDelay_A | 714267794 | 712572130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9910 | 9910 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T5 | 10 | 10 | 0 | 0 |
T9 | 10 | 10 | 0 | 0 |
T12 | 10 | 10 | 0 | 0 |
T13 | 10 | 10 | 0 | 0 |
T18 | 10 | 10 | 0 | 0 |
T19 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 31950 | 30460 | 0 | 0 |
T2 | 1072480 | 1072430 | 0 | 0 |
T3 | 23430 | 22890 | 0 | 0 |
T4 | 2607190 | 2606460 | 0 | 0 |
T5 | 482370 | 481530 | 0 | 0 |
T9 | 46290 | 41280 | 0 | 0 |
T12 | 35750 | 29700 | 0 | 0 |
T13 | 3934000 | 3933880 | 0 | 0 |
T18 | 3810 | 3120 | 0 | 0 |
T19 | 278480 | 277930 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 20412 |
T1 | 25560 | 24320 | 0 | 24 |
T2 | 857984 | 857936 | 0 | 24 |
T3 | 18744 | 18288 | 0 | 24 |
T4 | 2085752 | 2085144 | 0 | 24 |
T5 | 385896 | 385200 | 0 | 24 |
T9 | 37032 | 32880 | 0 | 24 |
T12 | 28600 | 23544 | 0 | 24 |
T13 | 3147200 | 3147104 | 0 | 24 |
T14 | 0 | 0 | 0 | 24 |
T18 | 3048 | 2496 | 0 | 0 |
T19 | 222784 | 222320 | 0 | 24 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 714267794 | 712572130 | 0 | 0 |
T1 | 6390 | 6092 | 0 | 0 |
T2 | 214496 | 214486 | 0 | 0 |
T3 | 4686 | 4578 | 0 | 0 |
T4 | 521438 | 521292 | 0 | 0 |
T5 | 96474 | 96306 | 0 | 0 |
T9 | 9258 | 8256 | 0 | 0 |
T12 | 7150 | 5940 | 0 | 0 |
T13 | 786800 | 786776 | 0 | 0 |
T18 | 762 | 624 | 0 | 0 |
T19 | 55696 | 55586 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 991 | 991 | 0 | 0 |
OutputsKnown_A | 357133924 | 356286092 | 0 | 0 |
gen_flops.OutputDelay_A | 357133924 | 356252786 | 0 | 2562 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356286092 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356252786 | 0 | 2562 |
T1 | 3195 | 3040 | 0 | 3 |
T2 | 107248 | 107242 | 0 | 3 |
T3 | 2343 | 2286 | 0 | 3 |
T4 | 260719 | 260643 | 0 | 3 |
T5 | 48237 | 48150 | 0 | 3 |
T9 | 4629 | 4110 | 0 | 3 |
T12 | 3575 | 2943 | 0 | 3 |
T13 | 393400 | 393388 | 0 | 3 |
T14 | 0 | 0 | 0 | 3 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27790 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 991 | 991 | 0 | 0 |
OutputsKnown_A | 357133924 | 356286092 | 0 | 0 |
gen_flops.OutputDelay_A | 357133924 | 356252786 | 0 | 2562 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356286092 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356252786 | 0 | 2562 |
T1 | 3195 | 3040 | 0 | 3 |
T2 | 107248 | 107242 | 0 | 3 |
T3 | 2343 | 2286 | 0 | 3 |
T4 | 260719 | 260643 | 0 | 3 |
T5 | 48237 | 48150 | 0 | 3 |
T9 | 4629 | 4110 | 0 | 3 |
T12 | 3575 | 2943 | 0 | 3 |
T13 | 393400 | 393388 | 0 | 3 |
T14 | 0 | 0 | 0 | 3 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27790 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 991 | 991 | 0 | 0 |
OutputsKnown_A | 357133924 | 356286092 | 0 | 0 |
gen_flops.OutputDelay_A | 357133924 | 356252786 | 0 | 2562 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356286092 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356252786 | 0 | 2562 |
T1 | 3195 | 3040 | 0 | 3 |
T2 | 107248 | 107242 | 0 | 3 |
T3 | 2343 | 2286 | 0 | 3 |
T4 | 260719 | 260643 | 0 | 3 |
T5 | 48237 | 48150 | 0 | 3 |
T9 | 4629 | 4110 | 0 | 3 |
T12 | 3575 | 2943 | 0 | 3 |
T13 | 393400 | 393388 | 0 | 3 |
T14 | 0 | 0 | 0 | 3 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27790 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 991 | 991 | 0 | 0 |
OutputsKnown_A | 357133924 | 356286092 | 0 | 0 |
gen_flops.OutputDelay_A | 357133924 | 356252786 | 0 | 2562 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356286092 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356252786 | 0 | 2562 |
T1 | 3195 | 3040 | 0 | 3 |
T2 | 107248 | 107242 | 0 | 3 |
T3 | 2343 | 2286 | 0 | 3 |
T4 | 260719 | 260643 | 0 | 3 |
T5 | 48237 | 48150 | 0 | 3 |
T9 | 4629 | 4110 | 0 | 3 |
T12 | 3575 | 2943 | 0 | 3 |
T13 | 393400 | 393388 | 0 | 3 |
T14 | 0 | 0 | 0 | 3 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27790 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 991 | 991 | 0 | 0 |
OutputsKnown_A | 357133924 | 356286092 | 0 | 0 |
gen_flops.OutputDelay_A | 357133924 | 356252786 | 0 | 2562 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356286092 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356252786 | 0 | 2562 |
T1 | 3195 | 3040 | 0 | 3 |
T2 | 107248 | 107242 | 0 | 3 |
T3 | 2343 | 2286 | 0 | 3 |
T4 | 260719 | 260643 | 0 | 3 |
T5 | 48237 | 48150 | 0 | 3 |
T9 | 4629 | 4110 | 0 | 3 |
T12 | 3575 | 2943 | 0 | 3 |
T13 | 393400 | 393388 | 0 | 3 |
T14 | 0 | 0 | 0 | 3 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27790 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 991 | 991 | 0 | 0 |
OutputsKnown_A | 357133924 | 356286092 | 0 | 0 |
gen_flops.OutputDelay_A | 357133924 | 356252786 | 0 | 2562 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356286092 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133924 | 356252786 | 0 | 2562 |
T1 | 3195 | 3040 | 0 | 3 |
T2 | 107248 | 107242 | 0 | 3 |
T3 | 2343 | 2286 | 0 | 3 |
T4 | 260719 | 260643 | 0 | 3 |
T5 | 48237 | 48150 | 0 | 3 |
T9 | 4629 | 4110 | 0 | 3 |
T12 | 3575 | 2943 | 0 | 3 |
T13 | 393400 | 393388 | 0 | 3 |
T14 | 0 | 0 | 0 | 3 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27790 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 991 | 991 | 0 | 0 |
OutputsKnown_A | 357133897 | 356286065 | 0 | 0 |
gen_no_flops.OutputDelay_A | 357133897 | 356286065 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133897 | 356286065 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133897 | 356286065 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 991 | 991 | 0 | 0 |
OutputsKnown_A | 357120266 | 356272434 | 0 | 0 |
gen_flops.OutputDelay_A | 357120266 | 356239212 | 0 | 2478 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357120266 | 356272434 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357120266 | 356239212 | 0 | 2478 |
T1 | 3195 | 3040 | 0 | 3 |
T2 | 107248 | 107242 | 0 | 3 |
T3 | 2343 | 2286 | 0 | 3 |
T4 | 260719 | 260643 | 0 | 3 |
T5 | 48237 | 48150 | 0 | 3 |
T9 | 4629 | 4110 | 0 | 3 |
T12 | 3575 | 2943 | 0 | 3 |
T13 | 393400 | 393388 | 0 | 3 |
T14 | 0 | 0 | 0 | 3 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27790 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 991 | 991 | 0 | 0 |
OutputsKnown_A | 357133897 | 356286065 | 0 | 0 |
gen_no_flops.OutputDelay_A | 357133897 | 356286065 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133897 | 356286065 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133897 | 356286065 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 991 | 991 | 0 | 0 |
OutputsKnown_A | 357133897 | 356286065 | 0 | 0 |
gen_flops.OutputDelay_A | 357133897 | 356252774 | 0 | 2562 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 991 | 991 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133897 | 356286065 | 0 | 0 |
T1 | 3195 | 3046 | 0 | 0 |
T2 | 107248 | 107243 | 0 | 0 |
T3 | 2343 | 2289 | 0 | 0 |
T4 | 260719 | 260646 | 0 | 0 |
T5 | 48237 | 48153 | 0 | 0 |
T9 | 4629 | 4128 | 0 | 0 |
T12 | 3575 | 2970 | 0 | 0 |
T13 | 393400 | 393388 | 0 | 0 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 357133897 | 356252774 | 0 | 2562 |
T1 | 3195 | 3040 | 0 | 3 |
T2 | 107248 | 107242 | 0 | 3 |
T3 | 2343 | 2286 | 0 | 3 |
T4 | 260719 | 260643 | 0 | 3 |
T5 | 48237 | 48150 | 0 | 3 |
T9 | 4629 | 4110 | 0 | 3 |
T12 | 3575 | 2943 | 0 | 3 |
T13 | 393400 | 393388 | 0 | 3 |
T14 | 0 | 0 | 0 | 3 |
T18 | 381 | 312 | 0 | 0 |
T19 | 27848 | 27790 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |