Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21686216	1		T1	5453		T2	5556		T3	106265
full_word	7602511	1		T1	23300		T2	22385		T3	105517

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29288427	1		T1	28753		T2	27941		T3	211782
auto[TlIntgErrCmd]	109	1		T191	7		T192	4		T231	13
auto[TlIntgErrData]	93	1		T191	7		T192	7		T231	4
auto[TlIntgErrBoth]	98	1		T191	6		T192	9		T231	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	24977453	1		T1	23934		T2	5212		T3	211484
auto[1]	4311274	1		T1	4819		T2	22729		T3	298

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21068269	1		T1	3780		T2	3155		T3	106231
auto[TlIntgErrNone]	partial	auto[1]	617677	1		T1	1673		T2	2401		T3	34
auto[TlIntgErrNone]	full_word	auto[0]	3909042	1		T1	20154		T2	2057		T3	105253
auto[TlIntgErrNone]	full_word	auto[1]	3693439	1		T1	3146		T2	20328		T3	264
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T191	4		T192	3		T231	7
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T191	2		T192	1		T231	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T363	1		T368	1		T255	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T191	1		T231	1		T365	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T191	4		T192	3		T231	3
auto[TlIntgErrData]	partial	auto[1]	35	1		T191	2		T192	3		T231	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T364	1		T363	1		T368	1
auto[TlIntgErrData]	full_word	auto[1]	8	1		T191	1		T192	1		T252	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T192	3		T231	1		T257	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T191	6		T192	5		T231	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T252	1		T362	1		T367	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T192	1		T231	1		T363	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23609	1		T190	69		T191	19		T193	1440
full_word	4344091	1		T1	16322		T6	16503		T7	16715

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4367417	1		T1	16322		T6	16503		T7	16715
auto[TlIntgErrCmd]	94	1		T191	7		T192	5		T231	3
auto[TlIntgErrData]	100	1		T191	7		T192	6		T231	8
auto[TlIntgErrBoth]	89	1		T191	6		T192	7		T231	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4338096	1		T1	16322		T6	16503		T7	16715
auto[1]	29604	1		T190	125		T191	10		T193	1920

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1427	1		T190	3		T193	134		T216	78
auto[TlIntgErrNone]	partial	auto[1]	21922	1		T190	66		T193	1306		T216	1088
auto[TlIntgErrNone]	full_word	auto[0]	4336546	1		T1	16322		T6	16503		T7	16715
auto[TlIntgErrNone]	full_word	auto[1]	7522	1		T190	59		T193	614		T216	343
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T191	4		T192	2		T231	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1		T191	3		T192	3		T231	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T369	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T252	1		T313	1		T365	1
auto[TlIntgErrData]	partial	auto[0]	50	1		T191	5		T192	2		T231	5
auto[TlIntgErrData]	partial	auto[1]	41	1		T191	1		T192	4		T231	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T191	1		T252	1		T313	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T370	1		T363	1		T254	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T192	4		T231	3		T252	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T191	6		T192	3		T231	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T231	1		T362	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T257	1		T364	1		T368	1