Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.25	75.02			96.30	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_to_prog_fifo	78.54	93.44	65.77			69.23	85.71
tb.dut.u_to_rd_fifo	89.49	95.38	77.39			85.19	100.00
tb.dut.u_tl_adapter_eflash	91.93	96.92	81.90			88.89	100.00

---

Module Instance : tb.dut.u_to_prog_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.54	93.44	65.77			69.23	85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.52	82.67	63.51			66.67	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	67.62	76.92	68.57			25.00	100.00
u_reqfifo	87.85	95.00	73.08			83.33	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	68.01	91.43	51.85			68.75	60.00
u_sram_byte	100.00	100.00
u_sramreqfifo	64.11	86.11	47.83			62.50	60.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Module Instance : tb.dut.u_to_rd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.49	95.38	77.39			85.19	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.53	85.78	76.15	100.00		80.72	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	66.91	76.92	65.71			25.00	100.00
u_reqfifo	87.85	95.00	73.08			83.33	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	97.84	100.00	89.19	100.00		100.00	100.00
u_sram_byte	100.00	100.00
u_sramreqfifo	86.89	95.00	69.23			83.33	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Module Instance : tb.dut.u_tl_adapter_eflash

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.93	96.92	81.90			88.89	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.98	89.60	80.17	100.00		90.11	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_cmd_intg_check.u_cmd_intg_chk	100.00	100.00		100.00			100.00
u_err	67.62	76.92	68.57			25.00	100.00
u_reqfifo	95.19	100.00	80.77			100.00	100.00
u_rsp_gen	100.00	100.00					100.00
u_rspfifo	96.32	100.00	85.29			100.00	100.00
u_sram_byte	100.00	100.00
u_sramreqfifo	95.19	100.00	80.77			100.00	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
78.54	93.44

tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		61	57	93.44
ALWAYS	93	3	3	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
ALWAYS	229	8	6	75.00
ALWAYS	249	6	5	83.33
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	354	6	6	100.00
ALWAYS	366	5	5	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	0	0
CONT_ASSIGN	408	0	0
CONT_ASSIGN	415	0	0
ALWAYS	421	3	2	66.67
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	452	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
94	1	1
95	1	1
96		unreachable
			MISSING_ELSE
102	1	1
107	1	1
114	1	1
125	1	1
139	1	1
151	1	1
222	1	1
223	1	1
224	1	1
229	1	1
231	1	1
232	1	1
234	0	1
235	1	1
236	0	1
239	1	1
242	1	1
249	1	1
251	1	1
252	1	1
253	0	1
255	1	1
258	1	1
263	1	1
267	1	1
286	1	1
291	1	1
297	1	1
301	1	1
321	1	1
322	1	1
323	1	1
324	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
377	1	1
378	1	1
387	1	1
388	1	1
390	1	1
391	1	1
398	1	1
401	1	1
405	1	1
406		unreachable
408		unreachable
415		unreachable
421	1	1
425	1	1
427	0	1
			MISSING_ELSE
442	1	1
447	1	1
452		unreachable

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
89.49	95.38

tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		65	62	95.38
ALWAYS	93	4	4	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
ALWAYS	229	8	6	75.00
ALWAYS	249	6	5	83.33
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	354	6	6	100.00
ALWAYS	366	5	5	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
ALWAYS	421	3	3	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	452	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
94	1	1
95	1	1
96	1	1
			MISSING_ELSE
102	1	1
107	1	1
114	1	1
119	1	1
139	1	1
151	1	1
222	1	1
223	1	1
224	1	1
229	1	1
231	1	1
232	1	1
234	0	1
235	1	1
236	1	1
239	0	1
242	1	1
249	1	1
251	1	1
252	1	1
253	1	1
255	0	1
258	1	1
263	1	1
267	1	1
286	1	1
291	1	1
297	1	1
301	1	1
321	1	1
322	1	1
323	1	1
324	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
377	1	1
378	1	1
387	1	1
388	1	1
390	1	1
391	1	1
398	1	1
401	1	1
405	1	1
406	1	1
408	1	1
415	1	1
421	1	1
425	1	1
427	1	1
			MISSING_ELSE
442	1	1
447	1	1
452		unreachable

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
91.93	96.92

tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		65	63	96.92
ALWAYS	93	4	4	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
ALWAYS	229	8	7	87.50
ALWAYS	249	6	5	83.33
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	354	6	6	100.00
ALWAYS	366	5	5	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
ALWAYS	421	3	3	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	452	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
94	1	1
95	1	1
96	1	1
			MISSING_ELSE
102	1	1
107	1	1
114	1	1
119	1	1
139	1	1
151	1	1
222	1	1
223	1	1
224	1	1
229	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
239	0	1
242	1	1
249	1	1
251	1	1
252	1	1
253	1	1
255	0	1
258	1	1
263	1	1
267	1	1
286	1	1
291	1	1
297	1	1
301	1	1
321	1	1
322	1	1
323	1	1
324	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
377	1	1
378	1	1
387	1	1
388	1	1
390	1	1
391	1	1
398	1	1
401	1	1
405	1	1
406	1	1
408	1	1
415	1	1
421	1	1
425	1	1
427	1	1
			MISSING_ELSE
442	1	1
447	1	1
452		unreachable

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
78.54	65.77

tb.dut.u_to_prog_fifo

	Total	Covered	Percent
Conditions	111	73	65.77
Logical	111	73	65.77
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T15
1	1	Covered	T2,T3,T4

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T25
1	1	Covered	T2,T3,T4

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T25
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T3,T15,T25
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T4

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Unreachable

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
89.49	77.39

tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	115	89	77.39
Logical	115	89	77.39
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T12,T13
0	1	0	Covered	T5,T12,T13
1	0	0	Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T3,T4
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T4

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T20,T21
1	1	Covered	T1,T3,T4

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Not Covered
1	0	Covered	T5,T26,T27

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T3,T4

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T26,T27
1	1	Covered	T1,T3,T4

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T5,T26,T27

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T21
1	0	1	Covered	T4,T15,T28
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T20
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T28
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
91.93	81.90

tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	116	95	81.90
Logical	116	95	81.90
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T26,T29,T30

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T26,T29,T30
0	1	0	Unreachable
1	0	0	Covered	T26,T29,T30

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T11,T31,T32
1	0	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T14
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T31,T32

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T18
0	1	Covered	T34,T18,T19
1	0	Covered	T2,T31,T32

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T33,T34,T18
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T21,T31
1	Covered	T1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T14
1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T6,T7
0	0	0	0	0	1	Covered	T30
0	0	0	0	1	0	Covered	T11,T31,T35
0	0	0	1	0	0	Covered	T36,T37,T38
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T18,T19
1	1	Covered	T1,T6,T7

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T6,T7

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T6,T7

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T26,T36,T37
1	0	Covered	T39,T40,T41

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T26,T36,T37
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T6,T7

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T40,T41
1	1	Covered	T1,T6,T7

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T26,T36,T37
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Covered	T39,T40,T41

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T42,T43
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T26,T36,T37
1	1	1	Covered	T1,T6,T7

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T14
1	Covered	T1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T6,T7

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Not Covered
1	1	Covered	T1,T6,T7

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T36,T37
1	1	Covered	T1,T6,T7

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		27	26	96.30
TERNARY	107	2	2	100.00
TERNARY	291	2	2	100.00
TERNARY	297	3	2	66.67
TERNARY	324	2	2	100.00
TERNARY	447	2	2	100.00
IF	93	3	3	100.00
IF	231	4	4	100.00
IF	251	3	3	100.00
IF	357	2	2	100.00
IF	369	2	2	100.00
IF	425	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	297	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	297	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	447	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	93	if ((!rst_ni))
-2-:	95	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T26,T12
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if (reqfifo_rvalid)
-2-:	232	if (reqfifo_rdata.error)
-3-:	235	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T26,T36,T37
1	0	1	Covered	T1,T3,T4
1	0	0	Covered	T2,T3,T4
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	if (reqfifo_rvalid)
-2-:	252	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	357	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	425	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	1269568962	1267109736	0	0
DataIntgOptions_A	3177	3177	0	0
ReqOutKnown_A	1269568962	1267109736	0	0
SramDwHasByteGranularity_A	3177	3177	0	0
SramDwIsMultipleOfTlulWidth_A	3177	3177	0	0
TlOutKnown_A	1269568962	1267109736	0	0
TlOutPayloadKnown_A	1269568962	13928328	0	0
TlOutPayloadKnown_AKnownEnable	1269568962	1267109736	0	0
WdataOutKnown_A	1269568962	1267109736	0	0
WeOutKnown_A	1269568962	1267109736	0	0
WmaskOutKnown_A	1269568962	1267109736	0	0
adapterNoReadOrWrite	3177	3177	0	0
rvalidHighReqFifoEmpty	1269568962	7617473	0	0
rvalidHighWhenRspFifoFull	1268962897	7611097	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269568962	1267109736	0	0
T1	411747	411390	0	0
T2	1273413	1273386	0	0
T3	735873	735870	0	0
T4	411522	411498	0	0
T5	381267	304362	0	0
T6	341925	341397	0	0
T7	343839	343440	0	0
T14	4422	4137	0	0
T15	485892	485679	0	0
T16	2580723	2580309	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3177	3177	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T14	3	3	0	0
T15	3	3	0	0
T16	3	3	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269568962	1267109736	0	0
T1	411747	411390	0	0
T2	1273413	1273386	0	0
T3	735873	735870	0	0
T4	411522	411498	0	0
T5	381267	304362	0	0
T6	341925	341397	0	0
T7	343839	343440	0	0
T14	4422	4137	0	0
T15	485892	485679	0	0
T16	2580723	2580309	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3177	3177	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T14	3	3	0	0
T15	3	3	0	0
T16	3	3	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3177	3177	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T14	3	3	0	0
T15	3	3	0	0
T16	3	3	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269568962	1267109736	0	0
T1	411747	411390	0	0
T2	1273413	1273386	0	0
T3	735873	735870	0	0
T4	411522	411498	0	0
T5	381267	304362	0	0
T6	341925	341397	0	0
T7	343839	343440	0	0
T14	4422	4137	0	0
T15	485892	485679	0	0
T16	2580723	2580309	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269568962	13928328	0	0
T1	274498	35298	0	0
T2	1273413	16496	0	0
T3	735873	264	0	0
T4	411522	65932	0	0
T5	381267	1138	0	0
T6	341925	34679	0	0
T7	343839	33483	0	0
T14	4422	0	0	0
T15	485892	39088	0	0
T16	2580723	30820	0	0
T20	0	147	0	0
T21	0	148	0	0
T25	2072	8	0	0
T39	0	40709	0	0
T44	0	4944	0	0
T45	0	26	0	0
T46	0	800	0	0
T47	0	19	0	0
T48	0	41149	0	0
T49	0	10	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269568962	1267109736	0	0
T1	411747	411390	0	0
T2	1273413	1273386	0	0
T3	735873	735870	0	0
T4	411522	411498	0	0
T5	381267	304362	0	0
T6	341925	341397	0	0
T7	343839	343440	0	0
T14	4422	4137	0	0
T15	485892	485679	0	0
T16	2580723	2580309	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269568962	1267109736	0	0
T1	411747	411390	0	0
T2	1273413	1273386	0	0
T3	735873	735870	0	0
T4	411522	411498	0	0
T5	381267	304362	0	0
T6	341925	341397	0	0
T7	343839	343440	0	0
T14	4422	4137	0	0
T15	485892	485679	0	0
T16	2580723	2580309	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269568962	1267109736	0	0
T1	411747	411390	0	0
T2	1273413	1273386	0	0
T3	735873	735870	0	0
T4	411522	411498	0	0
T5	381267	304362	0	0
T6	341925	341397	0	0
T7	343839	343440	0	0
T14	4422	4137	0	0
T15	485892	485679	0	0
T16	2580723	2580309	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269568962	1267109736	0	0
T1	411747	411390	0	0
T2	1273413	1273386	0	0
T3	735873	735870	0	0
T4	411522	411498	0	0
T5	381267	304362	0	0
T6	341925	341397	0	0
T7	343839	343440	0	0
T14	4422	4137	0	0
T15	485892	485679	0	0
T16	2580723	2580309	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	3177	3177	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T14	3	3	0	0
T15	3	3	0	0
T16	3	3	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269568962	7617473	0	0
T1	274498	35298	0	0
T2	848942	0	0	0
T3	490582	162	0	0
T4	274348	4881	0	0
T5	254178	1138	0	0
T6	227950	34679	0	0
T7	229226	33483	0	0
T14	2948	0	0	0
T15	323928	4096	0	0
T16	1720482	30820	0	0
T20	0	127	0	0
T39	0	40709	0	0
T44	0	3208	0	0
T45	0	6	0	0
T47	0	19	0	0
T48	0	41149	0	0
T49	0	10	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	1268962897	7611097	0	0
T1	274498	35298	0	0
T2	848942	0	0	0
T3	490582	162	0	0
T4	274348	4881	0	0
T5	127269	0	0	0
T6	227950	34679	0	0
T7	229226	33483	0	0
T14	2948	0	0	0
T15	323928	4096	0	0
T16	1720482	30820	0	0
T20	0	127	0	0
T21	0	223	0	0
T39	0	40709	0	0
T44	0	3208	0	0
T45	0	6	0	0
T47	0	19	0	0
T48	0	41149	0	0
T49	0	10	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		61	57	93.44
ALWAYS	93	3	3	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
ALWAYS	229	8	6	75.00
ALWAYS	249	6	5	83.33
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	354	6	6	100.00
ALWAYS	366	5	5	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	0	0
CONT_ASSIGN	408	0	0
CONT_ASSIGN	415	0	0
ALWAYS	421	3	2	66.67
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	452	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
94	1	1
95	1	1
96		unreachable
			MISSING_ELSE
102	1	1
107	1	1
114	1	1
125	1	1
139	1	1
151	1	1
222	1	1
223	1	1
224	1	1
229	1	1
231	1	1
232	1	1
234	0	1
235	1	1
236	0	1
239	1	1
242	1	1
249	1	1
251	1	1
252	1	1
253	0	1
255	1	1
258	1	1
263	1	1
267	1	1
286	1	1
291	1	1
297	1	1
301	1	1
321	1	1
322	1	1
323	1	1
324	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
377	1	1
378	1	1
387	1	1
388	1	1
390	1	1
391	1	1
398	1	1
401	1	1
405	1	1
406		unreachable
408		unreachable
415		unreachable
421	1	1
425	1	1
427	0	1
			MISSING_ELSE
442	1	1
447	1	1
452		unreachable

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Covered	Percent
Conditions	111	73	65.77
Logical	111	73	65.77
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T15
1	1	Covered	T2,T3,T4

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T25
1	1	Covered	T2,T3,T4

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T25
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T3,T15,T25
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T4

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Unreachable

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
Branches		26	18	69.23
TERNARY	107	2	2	100.00
TERNARY	291	2	1	50.00
TERNARY	297	3	1	33.33
TERNARY	324	2	2	100.00
TERNARY	447	2	1	50.00
IF	93	2	2	100.00
IF	231	4	2	50.00
IF	251	3	2	66.67
IF	357	2	2	100.00
IF	369	2	2	100.00
IF	425	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	297	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	297	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	447	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	93	if ((!rst_ni))
-2-:	95	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Unreachable
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if (reqfifo_rvalid)
-2-:	232	if (reqfifo_rdata.error)
-3-:	235	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	1	Not Covered
1	0	0	Covered	T2,T3,T4
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	if (reqfifo_rvalid)
-2-:	252	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	357	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	425	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	12	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	12	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	423189654	422369912	0	0
DataIntgOptions_A	1059	1059	0	0
ReqOutKnown_A	423189654	422369912	0	0
SramDwHasByteGranularity_A	1059	1059	0	0
SramDwIsMultipleOfTlulWidth_A	1059	1059	0	0
TlOutKnown_A	423189654	422369912	0	0
TlOutPayloadKnown_A	423189654	3203360	0	0
TlOutPayloadKnown_AKnownEnable	423189654	422369912	0	0
WdataOutKnown_A	423189654	422369912	0	0
WeOutKnown_A	423189654	422369912	0	0
WmaskOutKnown_A	423189654	422369912	0	0
adapterNoReadOrWrite	1059	1059	0	0
rvalidHighReqFifoEmpty	423189654	0	0	0
rvalidHighWhenRspFifoFull	423189654	0	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	3203360	0	0
T2	424471	16496	0	0
T3	245291	102	0	0
T4	137174	44024	0	0
T5	127089	0	0	0
T6	113975	0	0	0
T7	114613	0	0	0
T14	1474	0	0	0
T15	161964	20447	0	0
T16	860241	0	0	0
T20	0	20	0	0
T21	0	148	0	0
T25	2072	8	0	0
T44	0	1736	0	0
T45	0	20	0	0
T46	0	800	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	0	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	0	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		65	62	95.38
ALWAYS	93	4	4	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
ALWAYS	229	8	6	75.00
ALWAYS	249	6	5	83.33
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	354	6	6	100.00
ALWAYS	366	5	5	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
ALWAYS	421	3	3	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	452	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
94	1	1
95	1	1
96	1	1
			MISSING_ELSE
102	1	1
107	1	1
114	1	1
119	1	1
139	1	1
151	1	1
222	1	1
223	1	1
224	1	1
229	1	1
231	1	1
232	1	1
234	0	1
235	1	1
236	1	1
239	0	1
242	1	1
249	1	1
251	1	1
252	1	1
253	1	1
255	0	1
258	1	1
263	1	1
267	1	1
286	1	1
291	1	1
297	1	1
301	1	1
321	1	1
322	1	1
323	1	1
324	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
377	1	1
378	1	1
387	1	1
388	1	1
390	1	1
391	1	1
398	1	1
401	1	1
405	1	1
406	1	1
408	1	1
415	1	1
421	1	1
425	1	1
427	1	1
			MISSING_ELSE
442	1	1
447	1	1
452		unreachable

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	115	89	77.39
Logical	115	89	77.39
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
1	0	Unreachable

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T12,T13
0	1	0	Covered	T5,T12,T13
1	0	0	Unreachable

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T3,T4
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T4

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T20,T21
1	1	Covered	T1,T3,T4

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Not Covered
1	0	Covered	T5,T26,T27

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T3,T4

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T26,T27
1	1	Covered	T1,T3,T4

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T5,T26,T27

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T21
1	0	1	Covered	T4,T15,T28
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T20
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T28
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
Branches		27	23	85.19
TERNARY	107	2	2	100.00
TERNARY	291	2	2	100.00
TERNARY	297	3	2	66.67
TERNARY	324	2	2	100.00
TERNARY	447	2	2	100.00
IF	93	3	3	100.00
IF	231	4	2	50.00
IF	251	3	2	66.67
IF	357	2	2	100.00
IF	369	2	2	100.00
IF	425	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	297	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	297	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	447	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	93	if ((!rst_ni))
-2-:	95	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T12,T13
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if (reqfifo_rvalid)
-2-:	232	if (reqfifo_rdata.error)
-3-:	235	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	1	Covered	T1,T3,T4
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	if (reqfifo_rvalid)
-2-:	252	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T4
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	357	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	425	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	423189654	422369912	0	0
DataIntgOptions_A	1059	1059	0	0
ReqOutKnown_A	423189654	422369912	0	0
SramDwHasByteGranularity_A	1059	1059	0	0
SramDwIsMultipleOfTlulWidth_A	1059	1059	0	0
TlOutKnown_A	423189654	422369912	0	0
TlOutPayloadKnown_A	423189654	4562270	0	0
TlOutPayloadKnown_AKnownEnable	423189654	422369912	0	0
WdataOutKnown_A	423189654	422369912	0	0
WeOutKnown_A	423189654	422369912	0	0
WmaskOutKnown_A	423189654	422369912	0	0
adapterNoReadOrWrite	1059	1059	0	0
rvalidHighReqFifoEmpty	423189654	3155630	0	0
rvalidHighWhenRspFifoFull	422583589	3149254	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	4562270	0	0
T1	137249	18976	0	0
T2	424471	0	0	0
T3	245291	162	0	0
T4	137174	21908	0	0
T5	127089	1138	0	0
T6	113975	18176	0	0
T7	114613	16768	0	0
T14	1474	0	0	0
T15	161964	18641	0	0
T16	860241	14016	0	0
T20	0	31	0	0
T44	0	3208	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	3155630	0	0
T1	137249	18976	0	0
T2	424471	0	0	0
T3	245291	162	0	0
T4	137174	4881	0	0
T5	127089	1138	0	0
T6	113975	18176	0	0
T7	114613	16768	0	0
T14	1474	0	0	0
T15	161964	4096	0	0
T16	860241	14016	0	0
T20	0	31	0	0
T44	0	3208	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	422583589	3149254	0	0
T1	137249	18976	0	0
T2	424471	0	0	0
T3	245291	162	0	0
T4	137174	4881	0	0
T5	180	0	0	0
T6	113975	18176	0	0
T7	114613	16768	0	0
T14	1474	0	0	0
T15	161964	4096	0	0
T16	860241	14016	0	0
T20	0	31	0	0
T21	0	223	0	0
T44	0	3208	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		65	63	96.92
ALWAYS	93	4	4	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
ALWAYS	229	8	7	87.50
ALWAYS	249	6	5	83.33
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	354	6	6	100.00
ALWAYS	366	5	5	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
ALWAYS	421	3	3	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	452	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
94	1	1
95	1	1
96	1	1
			MISSING_ELSE
102	1	1
107	1	1
114	1	1
119	1	1
139	1	1
151	1	1
222	1	1
223	1	1
224	1	1
229	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
239	0	1
242	1	1
249	1	1
251	1	1
252	1	1
253	1	1
255	0	1
258	1	1
263	1	1
267	1	1
286	1	1
291	1	1
297	1	1
301	1	1
321	1	1
322	1	1
323	1	1
324	1	1
354	1	1
355	1	1
357	1	1
358	1	1
359	1	1
360	1	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
377	1	1
378	1	1
387	1	1
388	1	1
390	1	1
391	1	1
398	1	1
401	1	1
405	1	1
406	1	1
408	1	1
415	1	1
421	1	1
425	1	1
427	1	1
			MISSING_ELSE
442	1	1
447	1	1
452		unreachable

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	116	95	81.90
Logical	116	95	81.90
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T26,T29,T30

 LINE       102
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T26,T29,T30
0	1	0	Unreachable
1	0	0	Covered	T26,T29,T30

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T11,T31,T32
1	0	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T14
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T31,T32

 LINE       107
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T18
0	1	Covered	T34,T18,T19
1	0	Covered	T2,T31,T32

 LINE       107
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T33,T34,T18
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T21,T31
1	Covered	T1,T2,T3

 LINE       119
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T14
1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T6,T7
0	0	0	0	0	1	Covered	T30
0	0	0	0	1	0	Covered	T11,T31,T35
0	0	0	1	0	0	Covered	T36,T37,T38
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       222
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       223
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T18,T19
1	1	Covered	T1,T6,T7

 LINE       224
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T6,T7

 LINE       235
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T6,T7

 LINE       252
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T6,T7

 LINE       253
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T26,T36,T37
1	0	Covered	T39,T40,T41

 LINE       263
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T26,T36,T37
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T6,T7

 LINE       263
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       291
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       291
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T40,T41
1	1	Covered	T1,T6,T7

 LINE       297
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T26,T36,T37
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       297
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       301
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       301
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       301
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       301
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       301
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Covered	T39,T40,T41

 LINE       301
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T7
1	0	1	Covered	T42,T43
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       301
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       321
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T26,T36,T37
1	1	1	Covered	T1,T6,T7

 LINE       323
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       324
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       360
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Not Covered

 LINE       360
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T7
1	1	Not Covered

 LINE       391
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       391
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T14
1	Covered	T1,T2,T3

 LINE       405
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T6,T7

 LINE       408
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Not Covered
1	1	Covered	T1,T6,T7

 LINE       447
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

 LINE       447
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T36,T37
1	1	Covered	T1,T6,T7

 LINE       447
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T7

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
Branches		27	24	88.89
TERNARY	107	2	2	100.00
TERNARY	291	2	2	100.00
TERNARY	297	3	2	66.67
TERNARY	324	2	2	100.00
TERNARY	447	2	2	100.00
IF	93	3	3	100.00
IF	231	4	3	75.00
IF	251	3	2	66.67
IF	357	2	2	100.00
IF	369	2	2	100.00
IF	425	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	291	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	297	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	297	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	447	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	93	if ((!rst_ni))
-2-:	95	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T26,T29,T30
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if (reqfifo_rvalid)
-2-:	232	if (reqfifo_rdata.error)
-3-:	235	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T26,T36,T37
1	0	1	Covered	T1,T6,T7
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	if (reqfifo_rvalid)
-2-:	252	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T6,T7
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	357	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	425	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	423189654	422369912	0	0
DataIntgOptions_A	1059	1059	0	0
ReqOutKnown_A	423189654	422369912	0	0
SramDwHasByteGranularity_A	1059	1059	0	0
SramDwIsMultipleOfTlulWidth_A	1059	1059	0	0
TlOutKnown_A	423189654	422369912	0	0
TlOutPayloadKnown_A	423189654	6162698	0	0
TlOutPayloadKnown_AKnownEnable	423189654	422369912	0	0
WdataOutKnown_A	423189654	422369912	0	0
WeOutKnown_A	423189654	422369912	0	0
WmaskOutKnown_A	423189654	422369912	0	0
adapterNoReadOrWrite	1059	1059	0	0
rvalidHighReqFifoEmpty	423189654	4461843	0	0
rvalidHighWhenRspFifoFull	423189654	4461843	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	6162698	0	0
T1	137249	16322	0	0
T2	424471	0	0	0
T3	245291	0	0	0
T4	137174	0	0	0
T5	127089	0	0	0
T6	113975	16503	0	0
T7	114613	16715	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	16804	0	0
T20	0	96	0	0
T39	0	40709	0	0
T45	0	6	0	0
T47	0	19	0	0
T48	0	41149	0	0
T49	0	10	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	4461843	0	0
T1	137249	16322	0	0
T2	424471	0	0	0
T3	245291	0	0	0
T4	137174	0	0	0
T5	127089	0	0	0
T6	113975	16503	0	0
T7	114613	16715	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	16804	0	0
T20	0	96	0	0
T39	0	40709	0	0
T45	0	6	0	0
T47	0	19	0	0
T48	0	41149	0	0
T49	0	10	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	4461843	0	0
T1	137249	16322	0	0
T2	424471	0	0	0
T3	245291	0	0	0
T4	137174	0	0	0
T5	127089	0	0	0
T6	113975	16503	0	0
T7	114613	16715	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	16804	0	0
T20	0	96	0	0
T39	0	40709	0	0
T45	0	6	0	0
T47	0	19	0	0
T48	0	41149	0	0
T49	0	10	0	0