Unified Coverage Report :: Module :: prim_generic_flash

Module : prim_generic_flash

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic	80.00	80.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	98.05	94.40	100.00	93.75	97.78	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_flash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_flash_banks[0].u_prim_flash_bank	94.54	96.05	89.78		93.75	93.10	100.00
gen_prim_flash_banks[1].u_prim_flash_bank	94.54	96.05	89.78		93.75	93.10	100.00
u_reg_top	98.94	99.31	95.82	100.00		99.56	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_flash

	Line No.	Total	Covered	Percent
TOTAL		10	8	80.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	101	0	0
CONT_ASSIGN	102	0	0
CONT_ASSIGN	103	0	0
CONT_ASSIGN	104	1	0	0.00
CONT_ASSIGN	105	1	0	0.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	142	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	1	1
101		unreachable
102		unreachable
103		unreachable
104	0	1
105	0	1
106	1	1
107	1	1
108	1	1
129	1	1
133	1	1
138	1	1
142	1	1