Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1692758616	1689479648	0	0
CheckNGreaterZero_A	4236	4236	0	0
GntImpliesReady_A	1692758616	442979768	0	0
GntImpliesValid_A	1692758616	442979768	0	0
GrantKnown_A	1692758616	1689479648	0	0
IdxKnown_A	1692758616	1689479648	0	0
IndexIsCorrect_A	1692758616	442979768	0	0
NoReadyValidNoGrant_A	1692758616	180170324	0	0
Priority_A	1692758616	467636342	0	0
ReadyAndValidImplyGrant_A	1692758616	442979768	0	0
ReqAndReadyImplyGrant_A	1692758616	442979768	0	0
ReqImpliesValid_A	1692758616	467636342	0	0
ValidKnown_A	1692758616	1689479648	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	1689479648	0	0
T1	548996	548520	0	0
T2	1697884	1697848	0	0
T3	981164	981160	0	0
T4	548696	548664	0	0
T5	508356	405816	0	0
T6	455900	455196	0	0
T7	458452	457920	0	0
T14	5896	5516	0	0
T15	647856	647572	0	0
T16	3440964	3440412	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4236	4236	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	442979768	0	0
T1	548996	69938	0	0
T2	1697884	842004	0	0
T3	981164	1662320	0	0
T4	548696	1987540	0	0
T5	508356	0	0	0
T6	455900	67816	0	0
T7	458452	66644	0	0
T14	5896	64	0	0
T15	647856	27792	0	0
T16	3440964	61716	0	0
T20	0	688	0	0
T21	0	5278	0	0
T25	0	1136	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	442979768	0	0
T1	548996	69938	0	0
T2	1697884	842004	0	0
T3	981164	1662320	0	0
T4	548696	1987540	0	0
T5	508356	0	0	0
T6	455900	67816	0	0
T7	458452	66644	0	0
T14	5896	64	0	0
T15	647856	27792	0	0
T16	3440964	61716	0	0
T20	0	688	0	0
T21	0	5278	0	0
T25	0	1136	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	1689479648	0	0
T1	548996	548520	0	0
T2	1697884	1697848	0	0
T3	981164	981160	0	0
T4	548696	548664	0	0
T5	508356	405816	0	0
T6	455900	455196	0	0
T7	458452	457920	0	0
T14	5896	5516	0	0
T15	647856	647572	0	0
T16	3440964	3440412	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	1689479648	0	0
T1	548996	548520	0	0
T2	1697884	1697848	0	0
T3	981164	981160	0	0
T4	548696	548664	0	0
T5	508356	405816	0	0
T6	455900	455196	0	0
T7	458452	457920	0	0
T14	5896	5516	0	0
T15	647856	647572	0	0
T16	3440964	3440412	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	442979768	0	0
T1	548996	69938	0	0
T2	1697884	842004	0	0
T3	981164	1662320	0	0
T4	548696	1987540	0	0
T5	508356	0	0	0
T6	455900	67816	0	0
T7	458452	66644	0	0
T14	5896	64	0	0
T15	647856	27792	0	0
T16	3440964	61716	0	0
T20	0	688	0	0
T21	0	5278	0	0
T25	0	1136	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	180170324	0	0
T1	548996	187354	0	0
T2	1697884	3392	0	0
T3	981164	2110204	0	0
T4	548696	8278	0	0
T5	508356	9552	0	0
T6	455900	111394	0	0
T7	458452	127310	0	0
T14	5896	256	0	0
T15	647856	128	0	0
T16	3440964	2019954	0	0
T20	0	316	0	0
T21	0	484	0	0
T45	0	358	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	467636342	0	0
T1	548996	72746	0	0
T2	1697884	842004	0	0
T3	981164	1662320	0	0
T4	548696	1987540	0	0
T5	508356	0	0	0
T6	455900	78096	0	0
T7	458452	75334	0	0
T14	5896	64	0	0
T15	647856	27792	0	0
T16	3440964	543578	0	0
T20	0	696	0	0
T21	0	5278	0	0
T25	0	1136	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	442979768	0	0
T1	548996	69938	0	0
T2	1697884	842004	0	0
T3	981164	1662320	0	0
T4	548696	1987540	0	0
T5	508356	0	0	0
T6	455900	67816	0	0
T7	458452	66644	0	0
T14	5896	64	0	0
T15	647856	27792	0	0
T16	3440964	61716	0	0
T20	0	688	0	0
T21	0	5278	0	0
T25	0	1136	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	442979768	0	0
T1	548996	69938	0	0
T2	1697884	842004	0	0
T3	981164	1662320	0	0
T4	548696	1987540	0	0
T5	508356	0	0	0
T6	455900	67816	0	0
T7	458452	66644	0	0
T14	5896	64	0	0
T15	647856	27792	0	0
T16	3440964	61716	0	0
T20	0	688	0	0
T21	0	5278	0	0
T25	0	1136	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	467636342	0	0
T1	548996	72746	0	0
T2	1697884	842004	0	0
T3	981164	1662320	0	0
T4	548696	1987540	0	0
T5	508356	0	0	0
T6	455900	78096	0	0
T7	458452	75334	0	0
T14	5896	64	0	0
T15	647856	27792	0	0
T16	3440964	543578	0	0
T20	0	696	0	0
T21	0	5278	0	0
T25	0	1136	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1692758616	1689479648	0	0
T1	548996	548520	0	0
T2	1697884	1697848	0	0
T3	981164	981160	0	0
T4	548696	548664	0	0
T5	508356	405816	0	0
T6	455900	455196	0	0
T7	458452	457920	0	0
T14	5896	5516	0	0
T15	647856	647572	0	0
T16	3440964	3440412	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423189654	422369912	0	0
CheckNGreaterZero_A	1059	1059	0	0
GntImpliesReady_A	423189654	120868503	0	0
GntImpliesValid_A	423189654	120868503	0	0
GrantKnown_A	423189654	422369912	0	0
IdxKnown_A	423189654	422369912	0	0
IndexIsCorrect_A	423189654	120868503	0	0
NoReadyValidNoGrant_A	423189654	46451417	0	0
Priority_A	423189654	126931369	0	0
ReadyAndValidImplyGrant_A	423189654	120868503	0	0
ReqAndReadyImplyGrant_A	423189654	120868503	0	0
ReqImpliesValid_A	423189654	126931369	0	0
ValidKnown_A	423189654	422369912	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	120868503	0	0
T1	137249	20186	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	18655	0	0
T7	114613	16690	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	16711	0	0
T25	0	292	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	120868503	0	0
T1	137249	20186	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	18655	0	0
T7	114613	16690	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	16711	0	0
T25	0	292	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	120868503	0	0
T1	137249	20186	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	18655	0	0
T7	114613	16690	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	16711	0	0
T25	0	292	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	46451417	0	0
T1	137249	53502	0	0
T2	424471	1696	0	0
T3	245291	530621	0	0
T4	137174	3305	0	0
T5	127089	2498	0	0
T6	113975	31012	0	0
T7	114613	29560	0	0
T14	1474	128	0	0
T15	161964	64	0	0
T16	860241	537945	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	126931369	0	0
T1	137249	21134	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	21802	0	0
T7	114613	19599	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	145004	0	0
T25	0	292	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	120868503	0	0
T1	137249	20186	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	18655	0	0
T7	114613	16690	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	16711	0	0
T25	0	292	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	120868503	0	0
T1	137249	20186	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	18655	0	0
T7	114613	16690	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	16711	0	0
T25	0	292	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	126931369	0	0
T1	137249	21134	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	21802	0	0
T7	114613	19599	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	145004	0	0
T25	0	292	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423189654	422369912	0	0
CheckNGreaterZero_A	1059	1059	0	0
GntImpliesReady_A	423189654	120650659	0	0
GntImpliesValid_A	423189654	120650659	0	0
GrantKnown_A	423189654	422369912	0	0
IdxKnown_A	423189654	422369912	0	0
IndexIsCorrect_A	423189654	120650659	0	0
NoReadyValidNoGrant_A	423189654	46451419	0	0
Priority_A	423189654	126713523	0	0
ReadyAndValidImplyGrant_A	423189654	120650659	0	0
ReqAndReadyImplyGrant_A	423189654	120650659	0	0
ReqImpliesValid_A	423189654	126713523	0	0
ValidKnown_A	423189654	422369912	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	120650659	0	0
T1	137249	20186	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	18655	0	0
T7	114613	16690	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	16711	0	0
T25	0	292	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	120650659	0	0
T1	137249	20186	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	18655	0	0
T7	114613	16690	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	16711	0	0
T25	0	292	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	120650659	0	0
T1	137249	20186	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	18655	0	0
T7	114613	16690	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	16711	0	0
T25	0	292	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	46451419	0	0
T1	137249	53502	0	0
T2	424471	1696	0	0
T3	245291	530621	0	0
T4	137174	3305	0	0
T5	127089	2498	0	0
T6	113975	31012	0	0
T7	114613	29560	0	0
T14	1474	128	0	0
T15	161964	64	0	0
T16	860241	537945	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	126713523	0	0
T1	137249	21134	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	21802	0	0
T7	114613	19599	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	145004	0	0
T25	0	292	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	120650659	0	0
T1	137249	20186	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	18655	0	0
T7	114613	16690	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	16711	0	0
T25	0	292	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	120650659	0	0
T1	137249	20186	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	18655	0	0
T7	114613	16690	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	16711	0	0
T25	0	292	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	126713523	0	0
T1	137249	21134	0	0
T2	424471	263900	0	0
T3	245291	417989	0	0
T4	137174	946171	0	0
T5	127089	0	0	0
T6	113975	21802	0	0
T7	114613	19599	0	0
T14	1474	32	0	0
T15	161964	13896	0	0
T16	860241	145004	0	0
T25	0	292	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423189654	422369912	0	0
CheckNGreaterZero_A	1059	1059	0	0
GntImpliesReady_A	423189654	100730303	0	0
GntImpliesValid_A	423189654	100730303	0	0
GrantKnown_A	423189654	422369912	0	0
IdxKnown_A	423189654	422369912	0	0
IndexIsCorrect_A	423189654	100730303	0	0
NoReadyValidNoGrant_A	423189654	43633744	0	0
Priority_A	423189654	106995725	0	0
ReadyAndValidImplyGrant_A	423189654	100730303	0	0
ReqAndReadyImplyGrant_A	423189654	100730303	0	0
ReqImpliesValid_A	423189654	106995725	0	0
ValidKnown_A	423189654	422369912	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	100730303	0	0
T1	137249	14783	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	15253	0	0
T7	114613	16632	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	14147	0	0
T20	0	344	0	0
T21	0	2639	0	0
T25	0	276	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	100730303	0	0
T1	137249	14783	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	15253	0	0
T7	114613	16632	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	14147	0	0
T20	0	344	0	0
T21	0	2639	0	0
T25	0	276	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	100730303	0	0
T1	137249	14783	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	15253	0	0
T7	114613	16632	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	14147	0	0
T20	0	344	0	0
T21	0	2639	0	0
T25	0	276	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	43633744	0	0
T1	137249	40175	0	0
T2	424471	0	0	0
T3	245291	524481	0	0
T4	137174	834	0	0
T5	127089	2278	0	0
T6	113975	24685	0	0
T7	114613	34095	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	472032	0	0
T20	0	158	0	0
T21	0	242	0	0
T45	0	179	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	106995725	0	0
T1	137249	15239	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	17246	0	0
T7	114613	18068	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	126785	0	0
T20	0	348	0	0
T21	0	2639	0	0
T25	0	276	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	100730303	0	0
T1	137249	14783	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	15253	0	0
T7	114613	16632	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	14147	0	0
T20	0	344	0	0
T21	0	2639	0	0
T25	0	276	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	100730303	0	0
T1	137249	14783	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	15253	0	0
T7	114613	16632	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	14147	0	0
T20	0	344	0	0
T21	0	2639	0	0
T25	0	276	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	106995725	0	0
T1	137249	15239	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	17246	0	0
T7	114613	18068	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	126785	0	0
T20	0	348	0	0
T21	0	2639	0	0
T25	0	276	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423189654	422369912	0	0
CheckNGreaterZero_A	1059	1059	0	0
GntImpliesReady_A	423189654	100730303	0	0
GntImpliesValid_A	423189654	100730303	0	0
GrantKnown_A	423189654	422369912	0	0
IdxKnown_A	423189654	422369912	0	0
IndexIsCorrect_A	423189654	100730303	0	0
NoReadyValidNoGrant_A	423189654	43633744	0	0
Priority_A	423189654	106995725	0	0
ReadyAndValidImplyGrant_A	423189654	100730303	0	0
ReqAndReadyImplyGrant_A	423189654	100730303	0	0
ReqImpliesValid_A	423189654	106995725	0	0
ValidKnown_A	423189654	422369912	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	100730303	0	0
T1	137249	14783	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	15253	0	0
T7	114613	16632	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	14147	0	0
T20	0	344	0	0
T21	0	2639	0	0
T25	0	276	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	100730303	0	0
T1	137249	14783	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	15253	0	0
T7	114613	16632	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	14147	0	0
T20	0	344	0	0
T21	0	2639	0	0
T25	0	276	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	100730303	0	0
T1	137249	14783	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	15253	0	0
T7	114613	16632	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	14147	0	0
T20	0	344	0	0
T21	0	2639	0	0
T25	0	276	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	43633744	0	0
T1	137249	40175	0	0
T2	424471	0	0	0
T3	245291	524481	0	0
T4	137174	834	0	0
T5	127089	2278	0	0
T6	113975	24685	0	0
T7	114613	34095	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	472032	0	0
T20	0	158	0	0
T21	0	242	0	0
T45	0	179	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	106995725	0	0
T1	137249	15239	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	17246	0	0
T7	114613	18068	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	126785	0	0
T20	0	348	0	0
T21	0	2639	0	0
T25	0	276	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	100730303	0	0
T1	137249	14783	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	15253	0	0
T7	114613	16632	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	14147	0	0
T20	0	344	0	0
T21	0	2639	0	0
T25	0	276	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	100730303	0	0
T1	137249	14783	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	15253	0	0
T7	114613	16632	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	14147	0	0
T20	0	344	0	0
T21	0	2639	0	0
T25	0	276	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	106995725	0	0
T1	137249	15239	0	0
T2	424471	157102	0	0
T3	245291	413171	0	0
T4	137174	47599	0	0
T5	127089	0	0	0
T6	113975	17246	0	0
T7	114613	18068	0	0
T14	1474	0	0	0
T15	161964	0	0	0
T16	860241	126785	0	0
T20	0	348	0	0
T21	0	2639	0	0
T25	0	276	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423189654	422369912	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0