Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425753375	36292630	0	0
DepthKnown_A	425753375	424847601	0	0
RvalidKnown_A	425753375	424847601	0	0
WreadyKnown_A	425753375	424847601	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	36292630	0	0
T1	137249	28753	0	0
T2	424471	27941	0	0
T3	245291	212793	0	0
T4	137174	130510	0	0
T5	127089	11521	0	0
T6	113975	27481	0	0
T7	114613	24921	0	0
T14	1474	23	0	0
T15	161964	16332	0	0
T16	860241	22013	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425753375	39038805	0	0
DepthKnown_A	425753375	424847601	0	0
RvalidKnown_A	425753375	424847601	0	0
WreadyKnown_A	425753375	424847601	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	39038805	0	0
T1	137249	28753	0	0
T2	424471	27941	0	0
T3	245291	211782	0	0
T4	137174	588410	0	0
T5	127089	11521	0	0
T6	113975	27481	0	0
T7	114613	24921	0	0
T14	1474	23	0	0
T15	161964	67960	0	0
T16	860241	22013	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425753375	7599776	0	0
DepthKnown_A	425753375	424847601	0	0
RvalidKnown_A	425753375	424847601	0	0
WreadyKnown_A	425753375	424847601	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	7599776	0	0
T2	424471	16496	0	0
T3	245291	1008	0	0
T4	137174	9685	0	0
T5	127089	2061	0	0
T6	113975	0	0	0
T7	114613	0	0	0
T14	1474	0	0	0
T15	161964	5893	0	0
T16	860241	0	0	0
T20	0	136	0	0
T21	0	1211	0	0
T25	2072	10	0	0
T44	0	1736	0	0
T45	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425753375	3230684	0	0
DepthKnown_A	425753375	424847601	0	0
RvalidKnown_A	425753375	424847601	0	0
WreadyKnown_A	425753375	424847601	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	3230684	0	0
T2	424471	16496	0	0
T3	245291	102	0	0
T4	137174	44024	0	0
T5	127089	2061	0	0
T6	113975	0	0	0
T7	114613	0	0	0
T14	1474	0	0	0
T15	161964	20447	0	0
T16	860241	0	0	0
T20	0	20	0	0
T21	0	148	0	0
T25	2072	8	0	0
T44	0	1736	0	0
T45	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425753375	424847601	0	0
T1	137249	137130	0	0
T2	424471	424462	0	0
T3	245291	245290	0	0
T4	137174	137166	0	0
T5	127089	101454	0	0
T6	113975	113799	0	0
T7	114613	114480	0	0
T14	1474	1379	0	0
T15	161964	161893	0	0
T16	860241	860103	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0