| T1083 |
/workspace/coverage/default/36.flash_ctrl_connect.3908491356 |
|
|
Feb 21 01:09:45 PM PST 24 |
Feb 21 01:10:02 PM PST 24 |
15001000 ps |
| T1084 |
/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.458061618 |
|
|
Feb 21 01:07:33 PM PST 24 |
Feb 21 01:07:47 PM PST 24 |
25690700 ps |
| T1085 |
/workspace/coverage/default/73.flash_ctrl_connect.323886047 |
|
|
Feb 21 01:10:51 PM PST 24 |
Feb 21 01:11:07 PM PST 24 |
20542600 ps |
| T1086 |
/workspace/coverage/default/44.flash_ctrl_connect.3731112322 |
|
|
Feb 21 01:10:17 PM PST 24 |
Feb 21 01:10:33 PM PST 24 |
31892300 ps |
| T1087 |
/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3130817653 |
|
|
Feb 21 01:06:49 PM PST 24 |
Feb 21 01:08:01 PM PST 24 |
3421114500 ps |
| T1088 |
/workspace/coverage/default/5.flash_ctrl_otp_reset.1447786049 |
|
|
Feb 21 01:04:38 PM PST 24 |
Feb 21 01:06:55 PM PST 24 |
39420100 ps |
| T1089 |
/workspace/coverage/default/49.flash_ctrl_disable.333906705 |
|
|
Feb 21 01:10:42 PM PST 24 |
Feb 21 01:11:04 PM PST 24 |
11842600 ps |
| T1090 |
/workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.58668866 |
|
|
Feb 21 01:08:15 PM PST 24 |
Feb 21 01:11:20 PM PST 24 |
17115859200 ps |
| T1091 |
/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1382815164 |
|
|
Feb 21 01:02:52 PM PST 24 |
Feb 21 01:11:50 PM PST 24 |
196216869400 ps |
| T1092 |
/workspace/coverage/default/30.flash_ctrl_rw_evict.113309798 |
|
|
Feb 21 01:09:23 PM PST 24 |
Feb 21 01:09:57 PM PST 24 |
62307900 ps |
| T1093 |
/workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2741543024 |
|
|
Feb 21 01:07:38 PM PST 24 |
Feb 21 01:08:17 PM PST 24 |
122078800 ps |
| T68 |
/workspace/coverage/default/1.flash_ctrl_mid_op_rst.1717961375 |
|
|
Feb 21 01:02:45 PM PST 24 |
Feb 21 01:03:59 PM PST 24 |
2564018300 ps |
| T1094 |
/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.3213681552 |
|
|
Feb 21 01:07:34 PM PST 24 |
Feb 21 01:07:48 PM PST 24 |
18105500 ps |
| T1095 |
/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.798749165 |
|
|
Feb 21 01:05:49 PM PST 24 |
Feb 21 01:08:48 PM PST 24 |
7825327800 ps |
| T201 |
/workspace/coverage/default/9.flash_ctrl_rw_derr.2573351732 |
|
|
Feb 21 01:06:09 PM PST 24 |
Feb 21 01:15:07 PM PST 24 |
22145447200 ps |
| T1096 |
/workspace/coverage/default/3.flash_ctrl_serr_address.1333216208 |
|
|
Feb 21 01:03:55 PM PST 24 |
Feb 21 01:04:57 PM PST 24 |
519717400 ps |
| T1097 |
/workspace/coverage/default/3.flash_ctrl_intr_rd.3235284925 |
|
|
Feb 21 01:04:12 PM PST 24 |
Feb 21 01:06:30 PM PST 24 |
1159355700 ps |
| T1098 |
/workspace/coverage/default/24.flash_ctrl_prog_reset.26712628 |
|
|
Feb 21 01:08:49 PM PST 24 |
Feb 21 01:09:03 PM PST 24 |
33757900 ps |
| T1099 |
/workspace/coverage/default/25.flash_ctrl_disable.248892770 |
|
|
Feb 21 01:08:45 PM PST 24 |
Feb 21 01:09:07 PM PST 24 |
20461200 ps |
| T1100 |
/workspace/coverage/default/3.flash_ctrl_smoke.140856472 |
|
|
Feb 21 01:03:49 PM PST 24 |
Feb 21 01:04:40 PM PST 24 |
135454000 ps |
| T1101 |
/workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.489022753 |
|
|
Feb 21 01:03:21 PM PST 24 |
Feb 21 01:03:44 PM PST 24 |
88365300 ps |
| T1102 |
/workspace/coverage/default/5.flash_ctrl_smoke.879029382 |
|
|
Feb 21 01:04:36 PM PST 24 |
Feb 21 01:05:29 PM PST 24 |
80527800 ps |
| T1103 |
/workspace/coverage/default/29.flash_ctrl_smoke.243092733 |
|
|
Feb 21 01:09:11 PM PST 24 |
Feb 21 01:11:16 PM PST 24 |
48118900 ps |
| T1104 |
/workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.4071130253 |
|
|
Feb 21 01:06:49 PM PST 24 |
Feb 21 01:10:28 PM PST 24 |
9163954000 ps |
| T1105 |
/workspace/coverage/default/1.flash_ctrl_ro_derr.1687220649 |
|
|
Feb 21 01:02:41 PM PST 24 |
Feb 21 01:04:58 PM PST 24 |
620674500 ps |
| T1106 |
/workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2938579134 |
|
|
Feb 21 01:08:16 PM PST 24 |
Feb 21 01:08:48 PM PST 24 |
74402600 ps |
| T327 |
/workspace/coverage/default/35.flash_ctrl_hw_sec_otp.789014925 |
|
|
Feb 21 01:09:34 PM PST 24 |
Feb 21 01:11:21 PM PST 24 |
6503936500 ps |
| T1107 |
/workspace/coverage/default/7.flash_ctrl_ro_serr.2767242920 |
|
|
Feb 21 01:05:23 PM PST 24 |
Feb 21 01:07:36 PM PST 24 |
1247877500 ps |
| T1108 |
/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.454977950 |
|
|
Feb 21 01:02:16 PM PST 24 |
Feb 21 01:04:16 PM PST 24 |
3016247500 ps |
| T1109 |
/workspace/coverage/default/28.flash_ctrl_rw_evict.4196595953 |
|
|
Feb 21 01:09:17 PM PST 24 |
Feb 21 01:09:53 PM PST 24 |
180648900 ps |
| T1110 |
/workspace/coverage/default/40.flash_ctrl_disable.2508976892 |
|
|
Feb 21 01:10:01 PM PST 24 |
Feb 21 01:10:24 PM PST 24 |
13042900 ps |
| T1111 |
/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2312171032 |
|
|
Feb 21 01:02:53 PM PST 24 |
Feb 21 01:06:51 PM PST 24 |
23981557800 ps |
| T1112 |
/workspace/coverage/default/0.flash_ctrl_serr_address.2348622682 |
|
|
Feb 21 01:02:12 PM PST 24 |
Feb 21 01:03:11 PM PST 24 |
2282209200 ps |
| T1113 |
/workspace/coverage/default/52.flash_ctrl_connect.4254183410 |
|
|
Feb 21 01:10:47 PM PST 24 |
Feb 21 01:11:04 PM PST 24 |
15541600 ps |
| T278 |
/workspace/coverage/default/3.flash_ctrl_integrity.2431596 |
|
|
Feb 21 01:03:56 PM PST 24 |
Feb 21 01:13:25 PM PST 24 |
8567086500 ps |
| T279 |
/workspace/coverage/default/0.flash_ctrl_integrity.3591656357 |
|
|
Feb 21 01:02:30 PM PST 24 |
Feb 21 01:12:59 PM PST 24 |
7677169500 ps |
| T1114 |
/workspace/coverage/default/7.flash_ctrl_hw_rma_reset.250026681 |
|
|
Feb 21 01:05:27 PM PST 24 |
Feb 21 01:16:51 PM PST 24 |
40121768700 ps |
| T1115 |
/workspace/coverage/default/44.flash_ctrl_disable.2661392858 |
|
|
Feb 21 01:10:13 PM PST 24 |
Feb 21 01:10:35 PM PST 24 |
12561600 ps |
| T1116 |
/workspace/coverage/default/19.flash_ctrl_connect.3315598439 |
|
|
Feb 21 01:08:16 PM PST 24 |
Feb 21 01:08:29 PM PST 24 |
26082300 ps |
| T1117 |
/workspace/coverage/default/10.flash_ctrl_otp_reset.3342366158 |
|
|
Feb 21 01:06:20 PM PST 24 |
Feb 21 01:08:36 PM PST 24 |
123426200 ps |
| T1118 |
/workspace/coverage/default/8.flash_ctrl_mp_regions.736693985 |
|
|
Feb 21 01:05:38 PM PST 24 |
Feb 21 01:08:31 PM PST 24 |
7452350500 ps |
| T1119 |
/workspace/coverage/default/22.flash_ctrl_smoke.1667673161 |
|
|
Feb 21 01:08:32 PM PST 24 |
Feb 21 01:10:37 PM PST 24 |
41468400 ps |
| T1120 |
/workspace/coverage/default/13.flash_ctrl_wo.2579224282 |
|
|
Feb 21 01:06:54 PM PST 24 |
Feb 21 01:09:43 PM PST 24 |
13037680200 ps |
| T1121 |
/workspace/coverage/default/26.flash_ctrl_prog_reset.47481275 |
|
|
Feb 21 01:08:59 PM PST 24 |
Feb 21 01:09:14 PM PST 24 |
32989700 ps |
| T1122 |
/workspace/coverage/default/6.flash_ctrl_error_mp.761836973 |
|
|
Feb 21 01:05:03 PM PST 24 |
Feb 21 01:42:54 PM PST 24 |
5278126200 ps |
| T1123 |
/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.1472244534 |
|
|
Feb 21 01:03:04 PM PST 24 |
Feb 21 01:17:01 PM PST 24 |
130160931400 ps |
| T222 |
/workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.3838915583 |
|
|
Feb 21 01:04:36 PM PST 24 |
Feb 21 01:04:51 PM PST 24 |
15541700 ps |
| T1124 |
/workspace/coverage/default/30.flash_ctrl_sec_info_access.4211890097 |
|
|
Feb 21 01:09:21 PM PST 24 |
Feb 21 01:10:32 PM PST 24 |
1970920600 ps |
| T1125 |
/workspace/coverage/default/40.flash_ctrl_connect.1689304290 |
|
|
Feb 21 01:10:02 PM PST 24 |
Feb 21 01:10:18 PM PST 24 |
30204200 ps |
| T1126 |
/workspace/coverage/default/12.flash_ctrl_prog_reset.3008050569 |
|
|
Feb 21 01:06:54 PM PST 24 |
Feb 21 01:07:10 PM PST 24 |
80037500 ps |
| T149 |
/workspace/coverage/default/14.flash_ctrl_hw_rma_reset.396040507 |
|
|
Feb 21 01:07:03 PM PST 24 |
Feb 21 01:19:44 PM PST 24 |
160197838200 ps |
| T1127 |
/workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1857560112 |
|
|
Feb 21 01:03:21 PM PST 24 |
Feb 21 01:03:44 PM PST 24 |
31731800 ps |
| T1128 |
/workspace/coverage/default/36.flash_ctrl_otp_reset.3429691166 |
|
|
Feb 21 01:09:35 PM PST 24 |
Feb 21 01:11:28 PM PST 24 |
73312700 ps |
| T1129 |
/workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3737440773 |
|
|
Feb 21 01:02:10 PM PST 24 |
Feb 21 01:13:57 PM PST 24 |
70143313400 ps |
| T1130 |
/workspace/coverage/default/15.flash_ctrl_phy_arb.1248865020 |
|
|
Feb 21 01:07:13 PM PST 24 |
Feb 21 01:08:22 PM PST 24 |
24634200 ps |
| T1131 |
/workspace/coverage/default/58.flash_ctrl_otp_reset.1070567453 |
|
|
Feb 21 01:10:53 PM PST 24 |
Feb 21 01:13:07 PM PST 24 |
50946300 ps |
| T1132 |
/workspace/coverage/default/11.flash_ctrl_smoke.4052056790 |
|
|
Feb 21 01:06:25 PM PST 24 |
Feb 21 01:07:39 PM PST 24 |
199621600 ps |
| T1133 |
/workspace/coverage/default/33.flash_ctrl_otp_reset.2775714314 |
|
|
Feb 21 01:09:27 PM PST 24 |
Feb 21 01:11:39 PM PST 24 |
33221500 ps |
| T1134 |
/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.1744127726 |
|
|
Feb 21 01:04:38 PM PST 24 |
Feb 21 01:05:03 PM PST 24 |
19350100 ps |
| T52 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3425189155 |
|
|
Feb 21 12:32:50 PM PST 24 |
Feb 21 12:33:09 PM PST 24 |
224183300 ps |
| T240 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.195747560 |
|
|
Feb 21 12:33:00 PM PST 24 |
Feb 21 12:33:14 PM PST 24 |
28540600 ps |
| T241 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.4064954196 |
|
|
Feb 21 12:32:52 PM PST 24 |
Feb 21 12:33:06 PM PST 24 |
18760400 ps |
| T53 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2111339618 |
|
|
Feb 21 12:32:38 PM PST 24 |
Feb 21 12:32:56 PM PST 24 |
42984600 ps |
| T54 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1148427937 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:33:10 PM PST 24 |
69521800 ps |
| T190 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3366458666 |
|
|
Feb 21 12:32:20 PM PST 24 |
Feb 21 12:32:36 PM PST 24 |
173735500 ps |
| T242 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2924252942 |
|
|
Feb 21 12:33:05 PM PST 24 |
Feb 21 12:33:24 PM PST 24 |
30537600 ps |
| T191 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1827237010 |
|
|
Feb 21 12:32:38 PM PST 24 |
Feb 21 12:45:15 PM PST 24 |
1975762900 ps |
| T355 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.406187560 |
|
|
Feb 21 12:32:58 PM PST 24 |
Feb 21 12:33:12 PM PST 24 |
26886200 ps |
| T352 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3565774165 |
|
|
Feb 21 12:32:59 PM PST 24 |
Feb 21 12:33:13 PM PST 24 |
15191200 ps |
| T217 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3375271157 |
|
|
Feb 21 12:32:39 PM PST 24 |
Feb 21 12:33:10 PM PST 24 |
146996800 ps |
| T193 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.463012597 |
|
|
Feb 21 12:32:47 PM PST 24 |
Feb 21 12:33:10 PM PST 24 |
97696700 ps |
| T216 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2745163564 |
|
|
Feb 21 12:32:48 PM PST 24 |
Feb 21 12:33:08 PM PST 24 |
67680600 ps |
| T235 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.4200749533 |
|
|
Feb 21 12:32:38 PM PST 24 |
Feb 21 12:33:31 PM PST 24 |
1264752900 ps |
| T1135 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.615806051 |
|
|
Feb 21 12:32:28 PM PST 24 |
Feb 21 12:32:42 PM PST 24 |
161637800 ps |
| T280 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2002327992 |
|
|
Feb 21 12:32:55 PM PST 24 |
Feb 21 12:33:13 PM PST 24 |
40783800 ps |
| T1136 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.4212499458 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:33 PM PST 24 |
297868800 ps |
| T1137 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1787988972 |
|
|
Feb 21 12:32:39 PM PST 24 |
Feb 21 12:32:53 PM PST 24 |
39719600 ps |
| T302 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1076618609 |
|
|
Feb 21 12:32:34 PM PST 24 |
Feb 21 12:33:34 PM PST 24 |
1550609300 ps |
| T303 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1653336498 |
|
|
Feb 21 12:33:01 PM PST 24 |
Feb 21 12:33:19 PM PST 24 |
1212982000 ps |
| T354 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.335014844 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:33:09 PM PST 24 |
44210100 ps |
| T359 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1121148359 |
|
|
Feb 21 12:32:59 PM PST 24 |
Feb 21 12:33:13 PM PST 24 |
28438700 ps |
| T1138 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2946290630 |
|
|
Feb 21 12:32:49 PM PST 24 |
Feb 21 12:33:07 PM PST 24 |
106310000 ps |
| T192 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3344078068 |
|
|
Feb 21 12:32:53 PM PST 24 |
Feb 21 12:47:45 PM PST 24 |
334457400 ps |
| T245 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.278670235 |
|
|
Feb 21 12:32:58 PM PST 24 |
Feb 21 12:33:16 PM PST 24 |
348374400 ps |
| T262 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2134064362 |
|
|
Feb 21 12:32:27 PM PST 24 |
Feb 21 12:32:41 PM PST 24 |
19082000 ps |
| T420 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2903404080 |
|
|
Feb 21 12:32:59 PM PST 24 |
Feb 21 12:33:17 PM PST 24 |
37510100 ps |
| T351 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2778885432 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:11 PM PST 24 |
28828600 ps |
| T232 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1359932538 |
|
|
Feb 21 12:32:41 PM PST 24 |
Feb 21 12:32:57 PM PST 24 |
57985500 ps |
| T258 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.66487465 |
|
|
Feb 21 12:32:58 PM PST 24 |
Feb 21 12:33:13 PM PST 24 |
48910100 ps |
| T237 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.4005149636 |
|
|
Feb 21 12:33:05 PM PST 24 |
Feb 21 12:33:26 PM PST 24 |
194711000 ps |
| T358 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.776529069 |
|
|
Feb 21 12:33:01 PM PST 24 |
Feb 21 12:33:16 PM PST 24 |
53301100 ps |
| T231 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.4091713639 |
|
|
Feb 21 12:32:56 PM PST 24 |
Feb 21 12:45:31 PM PST 24 |
368498300 ps |
| T304 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3628501061 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:14 PM PST 24 |
187828400 ps |
| T257 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1151538716 |
|
|
Feb 21 12:32:44 PM PST 24 |
Feb 21 12:39:05 PM PST 24 |
566072700 ps |
| T348 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.100442180 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:33:09 PM PST 24 |
54595900 ps |
| T259 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.88443227 |
|
|
Feb 21 12:33:05 PM PST 24 |
Feb 21 12:33:27 PM PST 24 |
41632100 ps |
| T356 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3111274731 |
|
|
Feb 21 12:33:00 PM PST 24 |
Feb 21 12:33:14 PM PST 24 |
52104600 ps |
| T305 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3070442575 |
|
|
Feb 21 12:33:08 PM PST 24 |
Feb 21 12:33:26 PM PST 24 |
72331400 ps |
| T353 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2215786678 |
|
|
Feb 21 12:33:05 PM PST 24 |
Feb 21 12:33:20 PM PST 24 |
18268800 ps |
| T236 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1332708027 |
|
|
Feb 21 12:32:56 PM PST 24 |
Feb 21 12:33:15 PM PST 24 |
50861600 ps |
| T247 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2113688589 |
|
|
Feb 21 12:32:59 PM PST 24 |
Feb 21 12:33:16 PM PST 24 |
48740900 ps |
| T260 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.289502535 |
|
|
Feb 21 12:32:52 PM PST 24 |
Feb 21 12:33:12 PM PST 24 |
841073600 ps |
| T1139 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1960208753 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:13 PM PST 24 |
23485200 ps |
| T1140 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1072186083 |
|
|
Feb 21 12:32:29 PM PST 24 |
Feb 21 12:32:43 PM PST 24 |
29921800 ps |
| T1141 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1547420657 |
|
|
Feb 21 12:33:01 PM PST 24 |
Feb 21 12:33:19 PM PST 24 |
66379900 ps |
| T1142 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1671256 |
|
|
Feb 21 12:32:51 PM PST 24 |
Feb 21 12:33:11 PM PST 24 |
166243800 ps |
| T1143 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3324541277 |
|
|
Feb 21 12:32:55 PM PST 24 |
Feb 21 12:33:12 PM PST 24 |
11910600 ps |
| T1144 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2632458812 |
|
|
Feb 21 12:32:39 PM PST 24 |
Feb 21 12:32:59 PM PST 24 |
91602700 ps |
| T1145 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2427670135 |
|
|
Feb 21 12:32:59 PM PST 24 |
Feb 21 12:33:16 PM PST 24 |
24510700 ps |
| T1146 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.812965257 |
|
|
Feb 21 12:33:04 PM PST 24 |
Feb 21 12:33:23 PM PST 24 |
180408800 ps |
| T349 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2125641773 |
|
|
Feb 21 12:33:03 PM PST 24 |
Feb 21 12:33:18 PM PST 24 |
31235200 ps |
| T350 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2246551514 |
|
|
Feb 21 12:33:03 PM PST 24 |
Feb 21 12:33:18 PM PST 24 |
45056600 ps |
| T306 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3203770123 |
|
|
Feb 21 12:32:34 PM PST 24 |
Feb 21 12:32:54 PM PST 24 |
252871700 ps |
| T1147 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1573766712 |
|
|
Feb 21 12:32:49 PM PST 24 |
Feb 21 12:33:34 PM PST 24 |
4788546700 ps |
| T1148 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2712752331 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:14 PM PST 24 |
20203200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.993465202 |
|
|
Feb 21 12:32:42 PM PST 24 |
Feb 21 12:33:00 PM PST 24 |
88331800 ps |
| T1150 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2848559151 |
|
|
Feb 21 12:32:41 PM PST 24 |
Feb 21 12:32:55 PM PST 24 |
14176700 ps |
| T1151 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2621727218 |
|
|
Feb 21 12:32:45 PM PST 24 |
Feb 21 12:32:59 PM PST 24 |
66946800 ps |
| T1152 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.81820737 |
|
|
Feb 21 12:33:04 PM PST 24 |
Feb 21 12:33:21 PM PST 24 |
48074800 ps |
| T1153 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.664940759 |
|
|
Feb 21 12:32:53 PM PST 24 |
Feb 21 12:33:07 PM PST 24 |
96085800 ps |
| T1154 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1163909921 |
|
|
Feb 21 12:33:04 PM PST 24 |
Feb 21 12:33:20 PM PST 24 |
53593600 ps |
| T1155 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3312750830 |
|
|
Feb 21 12:32:58 PM PST 24 |
Feb 21 12:33:15 PM PST 24 |
31560200 ps |
| T1156 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1787474859 |
|
|
Feb 21 12:32:43 PM PST 24 |
Feb 21 12:33:37 PM PST 24 |
853954700 ps |
| T357 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.224064936 |
|
|
Feb 21 12:32:51 PM PST 24 |
Feb 21 12:33:06 PM PST 24 |
33068400 ps |
| T1157 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2712184155 |
|
|
Feb 21 12:32:28 PM PST 24 |
Feb 21 12:32:45 PM PST 24 |
100883100 ps |
| T1158 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1418322446 |
|
|
Feb 21 12:32:53 PM PST 24 |
Feb 21 12:33:10 PM PST 24 |
45179200 ps |
| T252 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1900096756 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:45:48 PM PST 24 |
16856165200 ps |
| T313 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2050634134 |
|
|
Feb 21 12:32:45 PM PST 24 |
Feb 21 12:40:18 PM PST 24 |
428763400 ps |
| T248 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1289254855 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:15 PM PST 24 |
108918800 ps |
| T1159 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1683754848 |
|
|
Feb 21 12:33:04 PM PST 24 |
Feb 21 12:33:19 PM PST 24 |
18887800 ps |
| T1160 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.743714958 |
|
|
Feb 21 12:32:19 PM PST 24 |
Feb 21 12:33:00 PM PST 24 |
83045700 ps |
| T1161 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2062767415 |
|
|
Feb 21 12:33:09 PM PST 24 |
Feb 21 12:33:28 PM PST 24 |
31405000 ps |
| T1162 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3143072421 |
|
|
Feb 21 12:33:02 PM PST 24 |
Feb 21 12:33:17 PM PST 24 |
18122500 ps |
| T1163 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1540058705 |
|
|
Feb 21 12:33:05 PM PST 24 |
Feb 21 12:33:19 PM PST 24 |
21341400 ps |
| T1164 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3672127163 |
|
|
Feb 21 12:32:52 PM PST 24 |
Feb 21 12:33:24 PM PST 24 |
28500400 ps |
| T1165 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3947616391 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:13 PM PST 24 |
39131000 ps |
| T1166 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.889464783 |
|
|
Feb 21 12:33:03 PM PST 24 |
Feb 21 12:33:18 PM PST 24 |
43295500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3720443732 |
|
|
Feb 21 12:32:15 PM PST 24 |
Feb 21 12:32:32 PM PST 24 |
64850800 ps |
| T364 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1550885990 |
|
|
Feb 21 12:32:58 PM PST 24 |
Feb 21 12:40:30 PM PST 24 |
3100716100 ps |
| T238 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.393129450 |
|
|
Feb 21 12:32:46 PM PST 24 |
Feb 21 12:33:04 PM PST 24 |
52383700 ps |
| T307 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3152348075 |
|
|
Feb 21 12:33:05 PM PST 24 |
Feb 21 12:33:43 PM PST 24 |
257315100 ps |
| T1168 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3314356893 |
|
|
Feb 21 12:32:58 PM PST 24 |
Feb 21 12:33:14 PM PST 24 |
46832300 ps |
| T1169 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1830495412 |
|
|
Feb 21 12:32:50 PM PST 24 |
Feb 21 12:33:26 PM PST 24 |
159641600 ps |
| T1170 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.150961796 |
|
|
Feb 21 12:32:25 PM PST 24 |
Feb 21 12:32:39 PM PST 24 |
16155900 ps |
| T1171 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.727125450 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:14 PM PST 24 |
12436100 ps |
| T1172 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1458578828 |
|
|
Feb 21 12:33:00 PM PST 24 |
Feb 21 12:33:15 PM PST 24 |
18753300 ps |
| T1173 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2203370149 |
|
|
Feb 21 12:32:30 PM PST 24 |
Feb 21 12:32:44 PM PST 24 |
24285000 ps |
| T1174 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3465576278 |
|
|
Feb 21 12:33:06 PM PST 24 |
Feb 21 12:33:21 PM PST 24 |
41386000 ps |
| T239 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.863119753 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:33:14 PM PST 24 |
330212100 ps |
| T365 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.203941381 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:40:35 PM PST 24 |
2299860800 ps |
| T1175 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3561456230 |
|
|
Feb 21 12:32:51 PM PST 24 |
Feb 21 12:33:11 PM PST 24 |
119620600 ps |
| T244 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.558782 |
|
|
Feb 21 12:32:55 PM PST 24 |
Feb 21 12:33:12 PM PST 24 |
34146100 ps |
| T1176 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3934021100 |
|
|
Feb 21 12:32:32 PM PST 24 |
Feb 21 12:32:49 PM PST 24 |
52829500 ps |
| T1177 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1078858942 |
|
|
Feb 21 12:33:02 PM PST 24 |
Feb 21 12:33:17 PM PST 24 |
87308700 ps |
| T1178 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2837275092 |
|
|
Feb 21 12:32:42 PM PST 24 |
Feb 21 12:32:59 PM PST 24 |
159079200 ps |
| T1179 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3286869869 |
|
|
Feb 21 12:32:56 PM PST 24 |
Feb 21 12:33:10 PM PST 24 |
54935400 ps |
| T308 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2994177997 |
|
|
Feb 21 12:32:48 PM PST 24 |
Feb 21 12:33:09 PM PST 24 |
496144200 ps |
| T1180 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3943042940 |
|
|
Feb 21 12:32:40 PM PST 24 |
Feb 21 12:33:12 PM PST 24 |
28243900 ps |
| T309 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2369026097 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:33:13 PM PST 24 |
187210300 ps |
| T263 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.106660196 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:11 PM PST 24 |
31087800 ps |
| T1181 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3708384187 |
|
|
Feb 21 12:32:58 PM PST 24 |
Feb 21 12:33:16 PM PST 24 |
30788800 ps |
| T1182 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1826717275 |
|
|
Feb 21 12:32:50 PM PST 24 |
Feb 21 12:33:07 PM PST 24 |
12677700 ps |
| T1183 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.791523992 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:33:42 PM PST 24 |
3067491600 ps |
| T370 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.4095813525 |
|
|
Feb 21 12:33:07 PM PST 24 |
Feb 21 12:40:43 PM PST 24 |
273843100 ps |
| T310 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.864362913 |
|
|
Feb 21 12:32:56 PM PST 24 |
Feb 21 12:33:16 PM PST 24 |
214301800 ps |
| T264 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2003075479 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:11 PM PST 24 |
30531800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3522404315 |
|
|
Feb 21 12:32:36 PM PST 24 |
Feb 21 12:32:50 PM PST 24 |
48793800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2124900785 |
|
|
Feb 21 12:32:47 PM PST 24 |
Feb 21 12:33:09 PM PST 24 |
408021000 ps |
| T1186 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3394555698 |
|
|
Feb 21 12:33:11 PM PST 24 |
Feb 21 12:33:27 PM PST 24 |
82320800 ps |
| T362 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1292609725 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:48:00 PM PST 24 |
2711672900 ps |
| T311 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.156986057 |
|
|
Feb 21 12:33:03 PM PST 24 |
Feb 21 12:33:21 PM PST 24 |
389789500 ps |
| T1187 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3678767628 |
|
|
Feb 21 12:33:01 PM PST 24 |
Feb 21 12:33:37 PM PST 24 |
2066211100 ps |
| T1188 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1770054032 |
|
|
Feb 21 12:32:27 PM PST 24 |
Feb 21 12:32:41 PM PST 24 |
26897400 ps |
| T1189 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3271006686 |
|
|
Feb 21 12:32:46 PM PST 24 |
Feb 21 12:33:19 PM PST 24 |
67650600 ps |
| T249 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2612612952 |
|
|
Feb 21 12:32:37 PM PST 24 |
Feb 21 12:32:55 PM PST 24 |
237645300 ps |
| T1190 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1346996216 |
|
|
Feb 21 12:33:01 PM PST 24 |
Feb 21 12:33:20 PM PST 24 |
149058800 ps |
| T1191 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1232545046 |
|
|
Feb 21 12:32:40 PM PST 24 |
Feb 21 12:32:59 PM PST 24 |
149899500 ps |
| T1192 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.246785568 |
|
|
Feb 21 12:32:19 PM PST 24 |
Feb 21 12:32:35 PM PST 24 |
103007600 ps |
| T1193 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.4191999203 |
|
|
Feb 21 12:32:46 PM PST 24 |
Feb 21 12:33:33 PM PST 24 |
9759509600 ps |
| T1194 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2846410857 |
|
|
Feb 21 12:32:52 PM PST 24 |
Feb 21 12:33:09 PM PST 24 |
24701100 ps |
| T1195 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.980843847 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:33:11 PM PST 24 |
31691800 ps |
| T1196 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2668196084 |
|
|
Feb 21 12:33:03 PM PST 24 |
Feb 21 12:33:18 PM PST 24 |
52544600 ps |
| T1197 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2571548994 |
|
|
Feb 21 12:33:00 PM PST 24 |
Feb 21 12:33:17 PM PST 24 |
26785600 ps |
| T1198 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1793960364 |
|
|
Feb 21 12:32:58 PM PST 24 |
Feb 21 12:33:12 PM PST 24 |
55239200 ps |
| T366 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.563618265 |
|
|
Feb 21 12:32:40 PM PST 24 |
Feb 21 12:40:15 PM PST 24 |
848048000 ps |
| T1199 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3548872245 |
|
|
Feb 21 12:32:49 PM PST 24 |
Feb 21 12:33:04 PM PST 24 |
14520300 ps |
| T363 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.915679293 |
|
|
Feb 21 12:32:38 PM PST 24 |
Feb 21 12:47:30 PM PST 24 |
4510977800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.257218393 |
|
|
Feb 21 12:32:53 PM PST 24 |
Feb 21 12:33:08 PM PST 24 |
38650600 ps |
| T1201 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1582780617 |
|
|
Feb 21 12:33:05 PM PST 24 |
Feb 21 12:33:22 PM PST 24 |
18102000 ps |
| T1202 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4215600681 |
|
|
Feb 21 12:32:47 PM PST 24 |
Feb 21 12:33:25 PM PST 24 |
123598600 ps |
| T368 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1067376918 |
|
|
Feb 21 12:33:32 PM PST 24 |
Feb 21 12:48:39 PM PST 24 |
2795404900 ps |
| T367 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1773335025 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:40:33 PM PST 24 |
264709600 ps |
| T1203 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3394553303 |
|
|
Feb 21 12:33:07 PM PST 24 |
Feb 21 12:33:22 PM PST 24 |
50791400 ps |
| T256 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3534604724 |
|
|
Feb 21 12:32:43 PM PST 24 |
Feb 21 12:33:00 PM PST 24 |
53985200 ps |
| T1204 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2518272344 |
|
|
Feb 21 12:33:01 PM PST 24 |
Feb 21 12:33:16 PM PST 24 |
16891900 ps |
| T1205 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.843669125 |
|
|
Feb 21 12:32:47 PM PST 24 |
Feb 21 12:33:07 PM PST 24 |
35134100 ps |
| T1206 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2274312020 |
|
|
Feb 21 12:33:05 PM PST 24 |
Feb 21 12:33:23 PM PST 24 |
87930800 ps |
| T1207 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.441428206 |
|
|
Feb 21 12:33:01 PM PST 24 |
Feb 21 12:33:19 PM PST 24 |
22089100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2484441371 |
|
|
Feb 21 12:32:36 PM PST 24 |
Feb 21 12:32:52 PM PST 24 |
19938700 ps |
| T1209 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.794851476 |
|
|
Feb 21 12:32:25 PM PST 24 |
Feb 21 12:32:41 PM PST 24 |
35421400 ps |
| T246 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2868533920 |
|
|
Feb 21 12:32:48 PM PST 24 |
Feb 21 12:33:10 PM PST 24 |
230902600 ps |
| T1210 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.442739815 |
|
|
Feb 21 12:32:27 PM PST 24 |
Feb 21 12:32:44 PM PST 24 |
94693200 ps |
| T1211 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.337729656 |
|
|
Feb 21 12:32:51 PM PST 24 |
Feb 21 12:33:06 PM PST 24 |
53520900 ps |
| T1212 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.71016314 |
|
|
Feb 21 12:33:02 PM PST 24 |
Feb 21 12:33:16 PM PST 24 |
16810800 ps |
| T1213 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2848163214 |
|
|
Feb 21 12:32:56 PM PST 24 |
Feb 21 12:33:40 PM PST 24 |
422493700 ps |
| T1214 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3793223069 |
|
|
Feb 21 12:33:02 PM PST 24 |
Feb 21 12:33:17 PM PST 24 |
89752300 ps |
| T1215 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1674347243 |
|
|
Feb 21 12:33:05 PM PST 24 |
Feb 21 12:33:20 PM PST 24 |
224730600 ps |
| T1216 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3406346492 |
|
|
Feb 21 12:33:04 PM PST 24 |
Feb 21 12:33:20 PM PST 24 |
66625000 ps |
| T312 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3766698156 |
|
|
Feb 21 12:32:38 PM PST 24 |
Feb 21 12:33:20 PM PST 24 |
1694737700 ps |
| T254 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.476644334 |
|
|
Feb 21 12:33:01 PM PST 24 |
Feb 21 12:45:38 PM PST 24 |
3147856600 ps |
| T1217 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3172468708 |
|
|
Feb 21 12:32:50 PM PST 24 |
Feb 21 12:33:11 PM PST 24 |
73591800 ps |
| T255 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.338748141 |
|
|
Feb 21 12:32:38 PM PST 24 |
Feb 21 12:40:13 PM PST 24 |
371385400 ps |
| T1218 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1472880452 |
|
|
Feb 21 12:33:07 PM PST 24 |
Feb 21 12:33:24 PM PST 24 |
18211700 ps |
| T1219 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.499540343 |
|
|
Feb 21 12:32:27 PM PST 24 |
Feb 21 12:32:45 PM PST 24 |
51253200 ps |
| T1220 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1617148484 |
|
|
Feb 21 12:32:52 PM PST 24 |
Feb 21 12:33:11 PM PST 24 |
164885900 ps |
| T265 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1662964625 |
|
|
Feb 21 12:33:02 PM PST 24 |
Feb 21 12:33:18 PM PST 24 |
102535000 ps |
| T1221 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3659562005 |
|
|
Feb 21 12:32:49 PM PST 24 |
Feb 21 12:33:25 PM PST 24 |
174929400 ps |
| T1222 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3722731586 |
|
|
Feb 21 12:32:59 PM PST 24 |
Feb 21 12:33:17 PM PST 24 |
75091300 ps |
| T1223 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3284683667 |
|
|
Feb 21 12:32:48 PM PST 24 |
Feb 21 12:33:34 PM PST 24 |
2978159300 ps |
| T250 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1456234917 |
|
|
Feb 21 12:32:48 PM PST 24 |
Feb 21 12:33:09 PM PST 24 |
303136100 ps |
| T1224 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3434645388 |
|
|
Feb 21 12:32:58 PM PST 24 |
Feb 21 12:33:12 PM PST 24 |
16024700 ps |
| T1225 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2252975009 |
|
|
Feb 21 12:33:08 PM PST 24 |
Feb 21 12:33:23 PM PST 24 |
71721000 ps |
| T251 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.242187448 |
|
|
Feb 21 12:32:30 PM PST 24 |
Feb 21 12:32:46 PM PST 24 |
57260800 ps |
| T1226 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1569285550 |
|
|
Feb 21 12:32:48 PM PST 24 |
Feb 21 12:39:15 PM PST 24 |
2079974900 ps |
| T1227 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3657212777 |
|
|
Feb 21 12:33:03 PM PST 24 |
Feb 21 12:33:18 PM PST 24 |
25781900 ps |
| T1228 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3077760377 |
|
|
Feb 21 12:32:48 PM PST 24 |
Feb 21 12:33:08 PM PST 24 |
99546400 ps |
| T1229 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3066896666 |
|
|
Feb 21 12:32:38 PM PST 24 |
Feb 21 12:32:54 PM PST 24 |
12417400 ps |
| T1230 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2614972202 |
|
|
Feb 21 12:32:52 PM PST 24 |
Feb 21 12:33:10 PM PST 24 |
33974200 ps |
| T1231 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3177739827 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:13 PM PST 24 |
53039200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1064257632 |
|
|
Feb 21 12:32:55 PM PST 24 |
Feb 21 12:33:11 PM PST 24 |
68402900 ps |
| T1233 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3950569959 |
|
|
Feb 21 12:33:13 PM PST 24 |
Feb 21 12:33:27 PM PST 24 |
151018000 ps |
| T1234 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.808677540 |
|
|
Feb 21 12:33:04 PM PST 24 |
Feb 21 12:33:19 PM PST 24 |
43647700 ps |
| T1235 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1236301530 |
|
|
Feb 21 12:33:02 PM PST 24 |
Feb 21 12:33:17 PM PST 24 |
15902600 ps |
| T1236 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2601483333 |
|
|
Feb 21 12:32:55 PM PST 24 |
Feb 21 12:33:09 PM PST 24 |
26623700 ps |
| T1237 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1664100363 |
|
|
Feb 21 12:32:49 PM PST 24 |
Feb 21 12:33:07 PM PST 24 |
158065600 ps |
| T1238 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1291265961 |
|
|
Feb 21 12:32:48 PM PST 24 |
Feb 21 12:33:04 PM PST 24 |
13308500 ps |
| T1239 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1523015653 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:33:11 PM PST 24 |
40525000 ps |
| T1240 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4274791318 |
|
|
Feb 21 12:32:49 PM PST 24 |
Feb 21 12:33:04 PM PST 24 |
16277800 ps |
| T1241 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3091529624 |
|
|
Feb 21 12:32:54 PM PST 24 |
Feb 21 12:33:09 PM PST 24 |
66700200 ps |
| T1242 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.743591190 |
|
|
Feb 21 12:33:01 PM PST 24 |
Feb 21 12:33:20 PM PST 24 |
84316700 ps |
| T1243 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1369761665 |
|
|
Feb 21 12:32:53 PM PST 24 |
Feb 21 12:33:09 PM PST 24 |
23937900 ps |
| T1244 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3043247102 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:11 PM PST 24 |
50296600 ps |
| T1245 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1428350635 |
|
|
Feb 21 12:33:03 PM PST 24 |
Feb 21 12:45:40 PM PST 24 |
786384800 ps |
| T1246 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1863215284 |
|
|
Feb 21 12:33:03 PM PST 24 |
Feb 21 12:33:18 PM PST 24 |
60055800 ps |
| T1247 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2637576484 |
|
|
Feb 21 12:32:41 PM PST 24 |
Feb 21 12:32:57 PM PST 24 |
41297900 ps |
| T1248 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3435682862 |
|
|
Feb 21 12:32:52 PM PST 24 |
Feb 21 12:33:08 PM PST 24 |
12529000 ps |
| T1249 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2061690973 |
|
|
Feb 21 12:32:34 PM PST 24 |
Feb 21 12:32:52 PM PST 24 |
11648500 ps |
| T1250 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.36662391 |
|
|
Feb 21 12:32:58 PM PST 24 |
Feb 21 12:33:13 PM PST 24 |
30613500 ps |
| T1251 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.288008051 |
|
|
Feb 21 12:32:57 PM PST 24 |
Feb 21 12:33:15 PM PST 24 |
172528500 ps |
| T1252 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.42655947 |
|
|
Feb 21 12:32:38 PM PST 24 |
Feb 21 12:32:54 PM PST 24 |
13364400 ps |