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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.44 95.34 94.04 98.95 92.52 97.22 98.52 98.52


Total test records in report: 1274
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T369 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2205719485 Feb 21 12:32:55 PM PST 24 Feb 21 12:40:32 PM PST 24 413332900 ps
T1253 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3175841565 Feb 21 12:33:07 PM PST 24 Feb 21 12:33:21 PM PST 24 83917800 ps
T1254 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3227017163 Feb 21 12:32:52 PM PST 24 Feb 21 12:33:08 PM PST 24 67279600 ps
T1255 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2165528097 Feb 21 12:32:38 PM PST 24 Feb 21 12:32:57 PM PST 24 331543500 ps
T1256 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.816944042 Feb 21 12:32:53 PM PST 24 Feb 21 12:33:08 PM PST 24 13736300 ps
T1257 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.775537360 Feb 21 12:33:01 PM PST 24 Feb 21 12:47:50 PM PST 24 1388829900 ps
T1258 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.4253104199 Feb 21 12:33:03 PM PST 24 Feb 21 12:33:19 PM PST 24 28965900 ps
T1259 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2910327827 Feb 21 12:33:01 PM PST 24 Feb 21 12:33:16 PM PST 24 18353200 ps
T1260 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3648889282 Feb 21 12:33:03 PM PST 24 Feb 21 12:33:20 PM PST 24 112975700 ps
T1261 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1486034568 Feb 21 12:32:59 PM PST 24 Feb 21 12:33:14 PM PST 24 53367300 ps
T1262 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2678049805 Feb 21 12:32:49 PM PST 24 Feb 21 12:33:09 PM PST 24 88096100 ps
T1263 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1948795278 Feb 21 12:32:28 PM PST 24 Feb 21 12:32:51 PM PST 24 97687200 ps
T1264 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.559991097 Feb 21 12:32:59 PM PST 24 Feb 21 12:33:17 PM PST 24 121342100 ps
T1265 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3335007221 Feb 21 12:32:57 PM PST 24 Feb 21 12:33:11 PM PST 24 68263800 ps
T361 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3531196743 Feb 21 12:32:56 PM PST 24 Feb 21 12:33:13 PM PST 24 307117000 ps
T1266 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1881324301 Feb 21 12:32:54 PM PST 24 Feb 21 12:33:30 PM PST 24 511963800 ps
T1267 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3866559301 Feb 21 12:32:53 PM PST 24 Feb 21 12:33:08 PM PST 24 17647500 ps
T1268 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.403748785 Feb 21 12:32:57 PM PST 24 Feb 21 12:33:10 PM PST 24 53119500 ps
T1269 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1850959622 Feb 21 12:32:38 PM PST 24 Feb 21 12:32:54 PM PST 24 11826000 ps
T1270 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3189286639 Feb 21 12:32:58 PM PST 24 Feb 21 12:33:14 PM PST 24 47955500 ps
T1271 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1732539028 Feb 21 12:33:05 PM PST 24 Feb 21 12:33:25 PM PST 24 150939600 ps
T1272 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3478947361 Feb 21 12:32:27 PM PST 24 Feb 21 12:32:58 PM PST 24 941881900 ps
T1273 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3531412870 Feb 21 12:32:55 PM PST 24 Feb 21 12:33:09 PM PST 24 16679600 ps
T1274 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1353785115 Feb 21 12:32:56 PM PST 24 Feb 21 12:33:26 PM PST 24 65962700 ps

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.3460446125
Short name T4
Test name
Test status
Simulation time 68587357000 ps
CPU time 331.35 seconds
Started Feb 21 01:06:34 PM PST 24
Finished Feb 21 01:12:05 PM PST 24
Peak memory 273084 kb
Host smart-69bb5ff8-8fd9-46f0-a349-bcbb162b453c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460446125 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.3460446125
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1827237010
Short name T191
Test name
Test status
Simulation time 1975762900 ps
CPU time 755.74 seconds
Started Feb 21 12:32:38 PM PST 24
Finished Feb 21 12:45:15 PM PST 24
Peak memory 263528 kb
Host smart-77576cc9-3bb1-437e-9087-e21ae7df1e17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827237010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.1827237010
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.4288462780
Short name T6
Test name
Test status
Simulation time 2028792700 ps
CPU time 170.76 seconds
Started Feb 21 01:03:21 PM PST 24
Finished Feb 21 01:06:12 PM PST 24
Peak memory 291844 kb
Host smart-e0839abe-64df-4d5f-a2b2-787f2f1b624b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288462780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.4288462780
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.1038436930
Short name T31
Test name
Test status
Simulation time 98127500 ps
CPU time 132.08 seconds
Started Feb 21 01:06:51 PM PST 24
Finished Feb 21 01:09:04 PM PST 24
Peak memory 259040 kb
Host smart-a9a9272a-bad7-4a7b-b581-91f6d30c4662
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038436930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.1038436930
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.4155435623
Short name T3
Test name
Test status
Simulation time 245291936600 ps
CPU time 2504.3 seconds
Started Feb 21 01:03:04 PM PST 24
Finished Feb 21 01:44:49 PM PST 24
Peak memory 263688 kb
Host smart-265cc51d-5506-447e-97da-c07209e69c6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155435623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.4155435623
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.641017650
Short name T5
Test name
Test status
Simulation time 1270917900 ps
CPU time 4710.51 seconds
Started Feb 21 01:03:20 PM PST 24
Finished Feb 21 02:21:51 PM PST 24
Peak memory 284568 kb
Host smart-07cfa8c8-3ea3-4ff2-a58c-57c0da3e53a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641017650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.641017650
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.1887012178
Short name T40
Test name
Test status
Simulation time 4633313300 ps
CPU time 737.8 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:14:48 PM PST 24
Peak memory 339080 kb
Host smart-23cc6215-84a2-4ab9-b66e-d4962187e1f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887012178 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.1887012178
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.635177830
Short name T22
Test name
Test status
Simulation time 53945812800 ps
CPU time 496.68 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:10:30 PM PST 24
Peak memory 260368 kb
Host smart-8112dbac-84a1-4c55-82ec-5e9b836b8184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=635177830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.635177830
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.2828578433
Short name T55
Test name
Test status
Simulation time 854640900 ps
CPU time 71.17 seconds
Started Feb 21 01:04:27 PM PST 24
Finished Feb 21 01:05:39 PM PST 24
Peak memory 259860 kb
Host smart-0faf876e-c98a-4d8e-84e6-ab37e797d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828578433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.2828578433
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.463012597
Short name T193
Test name
Test status
Simulation time 97696700 ps
CPU time 18.8 seconds
Started Feb 21 12:32:47 PM PST 24
Finished Feb 21 12:33:10 PM PST 24
Peak memory 263560 kb
Host smart-7dddddef-b990-44da-a39a-41419f2e7a58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463012597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.463012597
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.2152686217
Short name T154
Test name
Test status
Simulation time 106898200 ps
CPU time 135.86 seconds
Started Feb 21 01:05:45 PM PST 24
Finished Feb 21 01:08:01 PM PST 24
Peak memory 260188 kb
Host smart-7cb8dc6e-7364-4710-a4dd-f5bacee1fe9b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152686217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.2152686217
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.2147136280
Short name T34
Test name
Test status
Simulation time 1849826500 ps
CPU time 78 seconds
Started Feb 21 01:10:13 PM PST 24
Finished Feb 21 01:11:31 PM PST 24
Peak memory 261544 kb
Host smart-7ff1aeb0-684d-48af-80cd-4e4c9ca07241
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147136280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.2147136280
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.3166745102
Short name T391
Test name
Test status
Simulation time 131725500 ps
CPU time 131.89 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:10:28 PM PST 24
Peak memory 258840 kb
Host smart-a650be07-37c9-4e08-8fc5-8af7e9b835db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166745102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.3166745102
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.3914057757
Short name T676
Test name
Test status
Simulation time 135859700 ps
CPU time 131.43 seconds
Started Feb 21 01:10:01 PM PST 24
Finished Feb 21 01:12:13 PM PST 24
Peak memory 263036 kb
Host smart-1bf8e8ff-5fdf-4de6-8ce0-4c08ec8626c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914057757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.3914057757
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.1035060468
Short name T65
Test name
Test status
Simulation time 43161800 ps
CPU time 13.35 seconds
Started Feb 21 01:06:59 PM PST 24
Finished Feb 21 01:07:13 PM PST 24
Peak memory 264392 kb
Host smart-495f7387-bec0-47a7-884e-74241e2ebf0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035060468 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.1035060468
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2778885432
Short name T351
Test name
Test status
Simulation time 28828600 ps
CPU time 13.28 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 261712 kb
Host smart-914e3b81-65f8-4680-87b5-f7ec2cd50efb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778885432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2
778885432
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3254016193
Short name T142
Test name
Test status
Simulation time 10031476200 ps
CPU time 100.72 seconds
Started Feb 21 01:06:50 PM PST 24
Finished Feb 21 01:08:32 PM PST 24
Peak memory 273156 kb
Host smart-e0c3cf26-6be7-45a9-a6b6-110cf58b989b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254016193 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.3254016193
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.1283882775
Short name T98
Test name
Test status
Simulation time 39446200 ps
CPU time 14.06 seconds
Started Feb 21 01:03:52 PM PST 24
Finished Feb 21 01:04:06 PM PST 24
Peak memory 264668 kb
Host smart-41d37390-651d-4ae7-a3e5-c6fb4beca86f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1283882775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.1283882775
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.210098281
Short name T108
Test name
Test status
Simulation time 60810400 ps
CPU time 14 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:09:48 PM PST 24
Peak memory 263544 kb
Host smart-ec838506-437c-42d9-84db-2a7e2f3c8d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210098281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.210098281
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.269886552
Short name T151
Test name
Test status
Simulation time 40752277400 ps
CPU time 793.04 seconds
Started Feb 21 01:03:04 PM PST 24
Finished Feb 21 01:16:17 PM PST 24
Peak memory 258248 kb
Host smart-5d2f365a-ecd4-47a3-bc2c-2149eae06ead
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269886552 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.269886552
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.143268130
Short name T15
Test name
Test status
Simulation time 11564288800 ps
CPU time 74.51 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:10:49 PM PST 24
Peak memory 263348 kb
Host smart-612b0a42-99c9-4f87-b9ed-1df362648f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143268130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.143268130
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.1149584164
Short name T157
Test name
Test status
Simulation time 131218700 ps
CPU time 135.95 seconds
Started Feb 21 01:08:55 PM PST 24
Finished Feb 21 01:11:11 PM PST 24
Peak memory 258660 kb
Host smart-6a505256-05c9-4889-b16c-1140e99ac2ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149584164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.1149584164
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.2807696390
Short name T36
Test name
Test status
Simulation time 201742100 ps
CPU time 22.42 seconds
Started Feb 21 01:04:27 PM PST 24
Finished Feb 21 01:04:50 PM PST 24
Peak memory 264404 kb
Host smart-1c6ba17d-049f-4c15-b947-bcc6e1e6225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807696390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.2807696390
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.3332258122
Short name T56
Test name
Test status
Simulation time 862201200 ps
CPU time 72.96 seconds
Started Feb 21 01:02:14 PM PST 24
Finished Feb 21 01:03:27 PM PST 24
Peak memory 259140 kb
Host smart-1d7b2242-d0fe-4f0a-8f9c-ec451b0ca474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332258122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.3332258122
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.4074429969
Short name T162
Test name
Test status
Simulation time 365911285700 ps
CPU time 2102.29 seconds
Started Feb 21 01:02:38 PM PST 24
Finished Feb 21 01:37:41 PM PST 24
Peak memory 264492 kb
Host smart-8221e423-b9db-45a4-a26d-7e6b3b6c2988
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074429969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.4074429969
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3885107477
Short name T78
Test name
Test status
Simulation time 89267649800 ps
CPU time 346.96 seconds
Started Feb 21 01:04:45 PM PST 24
Finished Feb 21 01:10:33 PM PST 24
Peak memory 264416 kb
Host smart-f2a858cc-039b-4fca-b133-7f9b065c282a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388
5107477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3885107477
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.1910148352
Short name T75
Test name
Test status
Simulation time 372575041600 ps
CPU time 2803.47 seconds
Started Feb 21 01:02:45 PM PST 24
Finished Feb 21 01:49:29 PM PST 24
Peak memory 264328 kb
Host smart-9731ad8f-35cb-415c-bcad-a0bfc896fe30
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910148352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.1910148352
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2134064362
Short name T262
Test name
Test status
Simulation time 19082000 ps
CPU time 13.77 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:32:41 PM PST 24
Peak memory 263448 kb
Host smart-0b6f5621-0c05-4b38-99d3-3ec1055a4fa4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134064362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.2134064362
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.1364072361
Short name T48
Test name
Test status
Simulation time 39040261400 ps
CPU time 556.33 seconds
Started Feb 21 01:06:13 PM PST 24
Finished Feb 21 01:15:30 PM PST 24
Peak memory 313752 kb
Host smart-5d8642b2-e438-41b4-9a19-00f987ff8048
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364072361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s
err.1364072361
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.4120250589
Short name T119
Test name
Test status
Simulation time 448879000 ps
CPU time 34.34 seconds
Started Feb 21 01:05:22 PM PST 24
Finished Feb 21 01:05:57 PM PST 24
Peak memory 277272 kb
Host smart-3b5beb21-b0d6-4108-a8bb-ebd2a9c028ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120250589 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.4120250589
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.2102731647
Short name T89
Test name
Test status
Simulation time 45233400 ps
CPU time 13.4 seconds
Started Feb 21 01:06:47 PM PST 24
Finished Feb 21 01:07:02 PM PST 24
Peak memory 264388 kb
Host smart-efbf46f1-85cb-4c7e-adc8-1857a79284f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102731647 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.2102731647
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2868533920
Short name T246
Test name
Test status
Simulation time 230902600 ps
CPU time 19.06 seconds
Started Feb 21 12:32:48 PM PST 24
Finished Feb 21 12:33:10 PM PST 24
Peak memory 263512 kb
Host smart-20276f9c-65b3-4545-ab3c-57045752e006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868533920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
2868533920
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.4091713639
Short name T231
Test name
Test status
Simulation time 368498300 ps
CPU time 754.11 seconds
Started Feb 21 12:32:56 PM PST 24
Finished Feb 21 12:45:31 PM PST 24
Peak memory 260064 kb
Host smart-22d0216e-c604-4885-bd91-9fb43e795884
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091713639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.4091713639
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.195747560
Short name T240
Test name
Test status
Simulation time 28540600 ps
CPU time 13.46 seconds
Started Feb 21 12:33:00 PM PST 24
Finished Feb 21 12:33:14 PM PST 24
Peak memory 260188 kb
Host smart-b1d111a9-87f3-474c-b052-81863f2399bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195747560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.195747560
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1038252154
Short name T57
Test name
Test status
Simulation time 17936560800 ps
CPU time 207.76 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:05:58 PM PST 24
Peak memory 289068 kb
Host smart-6e5a4ff0-e733-4f7d-89c6-4bf36a5dfe3c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038252154 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.1038252154
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.884427036
Short name T727
Test name
Test status
Simulation time 10012049900 ps
CPU time 101.28 seconds
Started Feb 21 01:03:04 PM PST 24
Finished Feb 21 01:04:46 PM PST 24
Peak memory 297588 kb
Host smart-2895ff0b-f110-45d5-89d1-04147004ad74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884427036 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.884427036
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.2121258807
Short name T60
Test name
Test status
Simulation time 3877877000 ps
CPU time 60.44 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:03:13 PM PST 24
Peak memory 259732 kb
Host smart-17d01f22-330a-42f2-b0d0-3712ac343108
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121258807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.2121258807
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.2469340973
Short name T215
Test name
Test status
Simulation time 996830300 ps
CPU time 151.76 seconds
Started Feb 21 01:09:47 PM PST 24
Finished Feb 21 01:12:20 PM PST 24
Peak memory 289192 kb
Host smart-9064cbd7-2c42-454f-9b7f-d20a72fd99ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469340973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.2469340973
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.837447276
Short name T10
Test name
Test status
Simulation time 84814400 ps
CPU time 14.44 seconds
Started Feb 21 01:03:53 PM PST 24
Finished Feb 21 01:04:08 PM PST 24
Peak memory 264428 kb
Host smart-028d80b2-b621-49f0-8ae0-82ab7233cda3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837447276 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.837447276
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.1740107197
Short name T168
Test name
Test status
Simulation time 20864900 ps
CPU time 22 seconds
Started Feb 21 01:07:00 PM PST 24
Finished Feb 21 01:07:24 PM PST 24
Peak memory 272856 kb
Host smart-b19eb3c4-aeb4-4026-8861-ebf9ecd6e70f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740107197 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.1740107197
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.1722123837
Short name T332
Test name
Test status
Simulation time 276951900 ps
CPU time 33.73 seconds
Started Feb 21 01:05:58 PM PST 24
Finished Feb 21 01:06:32 PM PST 24
Peak memory 277060 kb
Host smart-714c2a4f-c772-4704-952f-65ae5cf6e285
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722123837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.1722123837
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3168064998
Short name T69
Test name
Test status
Simulation time 897917200 ps
CPU time 17.02 seconds
Started Feb 21 01:03:03 PM PST 24
Finished Feb 21 01:03:21 PM PST 24
Peak memory 264676 kb
Host smart-2c2bf88c-934f-4a12-b9dd-ca06c1c0fdb3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168064998 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3168064998
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.1046712342
Short name T275
Test name
Test status
Simulation time 14680877300 ps
CPU time 533.77 seconds
Started Feb 21 01:02:54 PM PST 24
Finished Feb 21 01:11:48 PM PST 24
Peak memory 321316 kb
Host smart-86bbe9ce-f6c0-4928-b615-d2cdcd1f58e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046712342 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.1046712342
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.476644334
Short name T254
Test name
Test status
Simulation time 3147856600 ps
CPU time 755.54 seconds
Started Feb 21 12:33:01 PM PST 24
Finished Feb 21 12:45:38 PM PST 24
Peak memory 260832 kb
Host smart-0e426fa0-49d3-43de-9bb7-0c9eded95f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476644334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl
_tl_intg_err.476644334
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.3628430411
Short name T101
Test name
Test status
Simulation time 32223900 ps
CPU time 30.7 seconds
Started Feb 21 01:02:31 PM PST 24
Finished Feb 21 01:03:02 PM PST 24
Peak memory 273876 kb
Host smart-40f31b81-c6a7-4534-8415-6b4cf63d9f3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628430411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.3628430411
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.687128497
Short name T203
Test name
Test status
Simulation time 43336600 ps
CPU time 14.13 seconds
Started Feb 21 01:04:16 PM PST 24
Finished Feb 21 01:04:31 PM PST 24
Peak memory 264040 kb
Host smart-731f9ddc-ee2b-40c2-ae47-72bbbddc5971
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687128497 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.687128497
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1076618609
Short name T302
Test name
Test status
Simulation time 1550609300 ps
CPU time 58.54 seconds
Started Feb 21 12:32:34 PM PST 24
Finished Feb 21 12:33:34 PM PST 24
Peak memory 259568 kb
Host smart-79cdb967-c675-4082-b1ba-1e5f149adbbd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076618609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.1076618609
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.4006370870
Short name T336
Test name
Test status
Simulation time 30504500 ps
CPU time 28.46 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:10:02 PM PST 24
Peak memory 273800 kb
Host smart-b2b9b814-f253-4519-a3f9-1bde3371cec4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006370870 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.4006370870
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.690333345
Short name T1001
Test name
Test status
Simulation time 55912100 ps
CPU time 13.56 seconds
Started Feb 21 01:07:38 PM PST 24
Finished Feb 21 01:07:52 PM PST 24
Peak memory 264404 kb
Host smart-4f56a745-cf53-4e35-b48b-8d57e54847f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690333345 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.690333345
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.2036493255
Short name T32
Test name
Test status
Simulation time 1151622000 ps
CPU time 1825.79 seconds
Started Feb 21 01:03:05 PM PST 24
Finished Feb 21 01:33:31 PM PST 24
Peak memory 264088 kb
Host smart-93d08f90-5e10-4b58-98b8-0e00056f9457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036493255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.2036493255
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.4005149636
Short name T237
Test name
Test status
Simulation time 194711000 ps
CPU time 19.06 seconds
Started Feb 21 12:33:05 PM PST 24
Finished Feb 21 12:33:26 PM PST 24
Peak memory 263468 kb
Host smart-e780b6d6-11ad-4903-99ab-c5eaaf359551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005149636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
4005149636
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2003075479
Short name T264
Test name
Test status
Simulation time 30531800 ps
CPU time 13.37 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 263148 kb
Host smart-75f3e701-2cd0-42df-90e4-577574768d4f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003075479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.2003075479
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1153354290
Short name T173
Test name
Test status
Simulation time 10012659600 ps
CPU time 113.06 seconds
Started Feb 21 01:04:17 PM PST 24
Finished Feb 21 01:06:11 PM PST 24
Peak memory 318428 kb
Host smart-0953aac9-522d-4183-90f6-a540f9d998e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153354290 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1153354290
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2867335777
Short name T848
Test name
Test status
Simulation time 19315600 ps
CPU time 13.33 seconds
Started Feb 21 01:03:05 PM PST 24
Finished Feb 21 01:03:18 PM PST 24
Peak memory 263656 kb
Host smart-c1b5a717-4c72-4e89-bcec-cc46c3b49be0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867335777 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2867335777
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3522404315
Short name T1184
Test name
Test status
Simulation time 48793800 ps
CPU time 13.28 seconds
Started Feb 21 12:32:36 PM PST 24
Finished Feb 21 12:32:50 PM PST 24
Peak memory 261832 kb
Host smart-f1f8ae17-0211-4f3f-a61e-e4eca41e0b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522404315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3
522404315
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.2842714821
Short name T143
Test name
Test status
Simulation time 15649500 ps
CPU time 13.31 seconds
Started Feb 21 01:07:34 PM PST 24
Finished Feb 21 01:07:48 PM PST 24
Peak memory 264336 kb
Host smart-d495b0ef-813b-400c-906e-94478b292756
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842714821 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.2842714821
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.2901990721
Short name T197
Test name
Test status
Simulation time 20296160800 ps
CPU time 4734.56 seconds
Started Feb 21 01:02:56 PM PST 24
Finished Feb 21 02:21:52 PM PST 24
Peak memory 285204 kb
Host smart-1e9253ec-384b-4b5d-8e03-77cc03bac1b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901990721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.2901990721
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.2441645417
Short name T153
Test name
Test status
Simulation time 150397700 ps
CPU time 115.2 seconds
Started Feb 21 01:09:45 PM PST 24
Finished Feb 21 01:11:40 PM PST 24
Peak memory 258788 kb
Host smart-9eba5436-9535-4d27-ad8b-4da47cfff7b0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441645417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.2441645417
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.3100809475
Short name T91
Test name
Test status
Simulation time 39609500 ps
CPU time 13.34 seconds
Started Feb 21 01:09:24 PM PST 24
Finished Feb 21 01:09:39 PM PST 24
Peak memory 274052 kb
Host smart-30e59eb2-d666-4d8f-b5d0-6f722059bb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100809475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.3100809475
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.2375025532
Short name T211
Test name
Test status
Simulation time 44208000 ps
CPU time 13.65 seconds
Started Feb 21 01:03:03 PM PST 24
Finished Feb 21 01:03:17 PM PST 24
Peak memory 263796 kb
Host smart-b6bd1288-6ef5-4927-91f6-d66024800e2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375025532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.2375025532
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.1938244965
Short name T26
Test name
Test status
Simulation time 22585700 ps
CPU time 13.4 seconds
Started Feb 21 01:02:56 PM PST 24
Finished Feb 21 01:03:10 PM PST 24
Peak memory 264440 kb
Host smart-68890991-de77-4649-90d0-466b34926ea6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938244965 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.1938244965
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.2975836578
Short name T147
Test name
Test status
Simulation time 50124690100 ps
CPU time 733.91 seconds
Started Feb 21 01:07:58 PM PST 24
Finished Feb 21 01:20:13 PM PST 24
Peak memory 262308 kb
Host smart-d561fdfd-d420-4196-8cae-eaf563f59b7d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975836578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.2975836578
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.823439033
Short name T396
Test name
Test status
Simulation time 1786461300 ps
CPU time 76.24 seconds
Started Feb 21 01:08:43 PM PST 24
Finished Feb 21 01:10:00 PM PST 24
Peak memory 263460 kb
Host smart-3f8f3a1e-f18c-4388-a201-269325e8b8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823439033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.823439033
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.3445206798
Short name T70
Test name
Test status
Simulation time 29208144000 ps
CPU time 337 seconds
Started Feb 21 01:05:02 PM PST 24
Finished Feb 21 01:10:40 PM PST 24
Peak memory 273936 kb
Host smart-3d64e02d-b494-4a8c-8497-bf5e4aa50c0c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445206798 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.3445206798
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.2184056206
Short name T42
Test name
Test status
Simulation time 409809500 ps
CPU time 29.21 seconds
Started Feb 21 01:02:47 PM PST 24
Finished Feb 21 01:03:19 PM PST 24
Peak memory 264388 kb
Host smart-b0b301dd-3039-408e-81c6-5fd4ccde0e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184056206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.2184056206
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.3954755590
Short name T450
Test name
Test status
Simulation time 102721300 ps
CPU time 31.33 seconds
Started Feb 21 01:06:54 PM PST 24
Finished Feb 21 01:07:26 PM PST 24
Peak memory 265628 kb
Host smart-a5f5454a-24ad-4cfb-9681-588f1235422c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954755590 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.3954755590
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.717656570
Short name T624
Test name
Test status
Simulation time 388159600 ps
CPU time 896.33 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:17:08 PM PST 24
Peak memory 264464 kb
Host smart-7a4bd1d8-58f6-41d3-a682-87dc6b03ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717656570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.717656570
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.915679293
Short name T363
Test name
Test status
Simulation time 4510977800 ps
CPU time 892.03 seconds
Started Feb 21 12:32:38 PM PST 24
Finished Feb 21 12:47:30 PM PST 24
Peak memory 263696 kb
Host smart-2fd1221f-3093-48c3-ab4b-c6da8f9b7a4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915679293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
tl_intg_err.915679293
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1900096756
Short name T252
Test name
Test status
Simulation time 16856165200 ps
CPU time 773.35 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:45:48 PM PST 24
Peak memory 263500 kb
Host smart-6f3b26b5-a9bd-4da8-9682-b689d5d35d57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900096756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.1900096756
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.333222600
Short name T409
Test name
Test status
Simulation time 8545072200 ps
CPU time 77.37 seconds
Started Feb 21 01:06:33 PM PST 24
Finished Feb 21 01:07:50 PM PST 24
Peak memory 258792 kb
Host smart-5efb45ec-120e-47e0-805d-7d5bffc8b67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333222600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.333222600
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.2635872335
Short name T558
Test name
Test status
Simulation time 4051367700 ps
CPU time 163.33 seconds
Started Feb 21 01:09:32 PM PST 24
Finished Feb 21 01:12:16 PM PST 24
Peak memory 293204 kb
Host smart-a36a5b72-1127-438d-9119-2a9c9f53fdf0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635872335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.2635872335
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.866423767
Short name T405
Test name
Test status
Simulation time 2272804500 ps
CPU time 75.78 seconds
Started Feb 21 01:10:10 PM PST 24
Finished Feb 21 01:11:28 PM PST 24
Peak memory 258788 kb
Host smart-ec787730-e6e0-45dd-a9d8-0183ce7ce192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866423767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.866423767
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.1774024402
Short name T790
Test name
Test status
Simulation time 15302000 ps
CPU time 13.47 seconds
Started Feb 21 01:05:00 PM PST 24
Finished Feb 21 01:05:16 PM PST 24
Peak memory 264324 kb
Host smart-617b9c8f-be77-4c76-963c-bae8396885a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774024402 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.1774024402
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.439796670
Short name T226
Test name
Test status
Simulation time 31131900 ps
CPU time 21.74 seconds
Started Feb 21 01:09:57 PM PST 24
Finished Feb 21 01:10:19 PM PST 24
Peak memory 279868 kb
Host smart-58325190-4780-432c-ae2d-324c5f0faa46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439796670 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.439796670
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.3334161282
Short name T67
Test name
Test status
Simulation time 305182500 ps
CPU time 106.17 seconds
Started Feb 21 01:04:25 PM PST 24
Finished Feb 21 01:06:12 PM PST 24
Peak memory 273888 kb
Host smart-dda72188-5ef3-4cdc-83b7-a41772bafb4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334161282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.3334161282
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1332708027
Short name T236
Test name
Test status
Simulation time 50861600 ps
CPU time 17.92 seconds
Started Feb 21 12:32:56 PM PST 24
Finished Feb 21 12:33:15 PM PST 24
Peak memory 263440 kb
Host smart-efb2382c-8f3a-4f88-9756-c60a77b65e65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332708027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
1332708027
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.3299596026
Short name T286
Test name
Test status
Simulation time 225909700 ps
CPU time 70.11 seconds
Started Feb 21 01:02:31 PM PST 24
Finished Feb 21 01:03:42 PM PST 24
Peak memory 264464 kb
Host smart-896941d1-5958-4ea5-aed8-cac87fc91199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3299596026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3299596026
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.3103347729
Short name T93
Test name
Test status
Simulation time 15006800 ps
CPU time 13.94 seconds
Started Feb 21 01:03:05 PM PST 24
Finished Feb 21 01:03:19 PM PST 24
Peak memory 277736 kb
Host smart-c040f782-3cea-48b9-9e25-bbed3b35b0a5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3103347729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.3103347729
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.4064954196
Short name T241
Test name
Test status
Simulation time 18760400 ps
CPU time 13.46 seconds
Started Feb 21 12:32:52 PM PST 24
Finished Feb 21 12:33:06 PM PST 24
Peak memory 262188 kb
Host smart-3c3a7d62-ab0b-4952-a115-318ad0a9d905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064954196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
4064954196
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2205719485
Short name T369
Test name
Test status
Simulation time 413332900 ps
CPU time 456.4 seconds
Started Feb 21 12:32:55 PM PST 24
Finished Feb 21 12:40:32 PM PST 24
Peak memory 259996 kb
Host smart-d639e348-24a9-4a98-9b44-c39ec482efb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205719485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.2205719485
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.3787203909
Short name T372
Test name
Test status
Simulation time 20410500 ps
CPU time 20.46 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:02:50 PM PST 24
Peak memory 272768 kb
Host smart-ddbee88e-4594-4337-925d-c05836722cb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787203909 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.3787203909
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.2697067895
Short name T375
Test name
Test status
Simulation time 57861700 ps
CPU time 20.54 seconds
Started Feb 21 01:02:56 PM PST 24
Finished Feb 21 01:03:17 PM PST 24
Peak memory 272796 kb
Host smart-b2c9df08-47a3-4810-bb51-f5ca8643bd6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697067895 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.2697067895
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.536942459
Short name T267
Test name
Test status
Simulation time 150014900 ps
CPU time 31.36 seconds
Started Feb 21 01:06:47 PM PST 24
Finished Feb 21 01:07:20 PM PST 24
Peak memory 276208 kb
Host smart-b683c409-4d59-4f05-9624-6726fbf8a528
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536942459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_rw_evict.536942459
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.992115677
Short name T411
Test name
Test status
Simulation time 31522070600 ps
CPU time 74.25 seconds
Started Feb 21 01:06:52 PM PST 24
Finished Feb 21 01:08:06 PM PST 24
Peak memory 262788 kb
Host smart-b57bf0f6-5773-4ded-954b-34cd4e61dd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992115677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.992115677
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.2029247773
Short name T843
Test name
Test status
Simulation time 10697350700 ps
CPU time 91.7 seconds
Started Feb 21 01:06:54 PM PST 24
Finished Feb 21 01:08:26 PM PST 24
Peak memory 259564 kb
Host smart-b544ab55-2bb6-46c8-86cb-9e915900a095
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029247773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.2
029247773
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2930504031
Short name T330
Test name
Test status
Simulation time 32413900 ps
CPU time 30.86 seconds
Started Feb 21 01:08:00 PM PST 24
Finished Feb 21 01:08:32 PM PST 24
Peak memory 272800 kb
Host smart-018620c3-3333-48a6-8dd4-db491e5acd99
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930504031 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.2930504031
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.766209731
Short name T393
Test name
Test status
Simulation time 10866000 ps
CPU time 21.93 seconds
Started Feb 21 01:08:13 PM PST 24
Finished Feb 21 01:08:35 PM PST 24
Peak memory 272896 kb
Host smart-2932b2a0-50bc-44c2-a94a-209cc8c26bf3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766209731 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.766209731
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.1412932547
Short name T681
Test name
Test status
Simulation time 12783200 ps
CPU time 22.09 seconds
Started Feb 21 01:08:30 PM PST 24
Finished Feb 21 01:08:53 PM PST 24
Peak memory 279980 kb
Host smart-1617e763-9158-4be1-9574-ee39f98f5627
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412932547 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.1412932547
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.4201779585
Short name T416
Test name
Test status
Simulation time 4921612900 ps
CPU time 106.72 seconds
Started Feb 21 01:04:11 PM PST 24
Finished Feb 21 01:05:58 PM PST 24
Peak memory 264432 kb
Host smart-42d1b180-66e3-429e-9401-889817bed6c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201779585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.4201779585
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.4150984412
Short name T395
Test name
Test status
Simulation time 1591679100 ps
CPU time 68.65 seconds
Started Feb 21 01:09:32 PM PST 24
Finished Feb 21 01:10:41 PM PST 24
Peak memory 264304 kb
Host smart-bf5a403b-7745-4664-ba45-c704187d952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150984412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.4150984412
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.3155619103
Short name T408
Test name
Test status
Simulation time 669109600 ps
CPU time 62.99 seconds
Started Feb 21 01:10:12 PM PST 24
Finished Feb 21 01:11:16 PM PST 24
Peak memory 258856 kb
Host smart-d03c2d9e-ff1a-4aa3-9028-91e6171ea8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155619103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3155619103
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.3693253339
Short name T398
Test name
Test status
Simulation time 2324803900 ps
CPU time 58.56 seconds
Started Feb 21 01:10:45 PM PST 24
Finished Feb 21 01:11:44 PM PST 24
Peak memory 258268 kb
Host smart-f8e9f578-8b4c-462e-a5b4-e62f87899d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693253339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.3693253339
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.4185122613
Short name T460
Test name
Test status
Simulation time 604581800 ps
CPU time 122.5 seconds
Started Feb 21 01:04:46 PM PST 24
Finished Feb 21 01:06:49 PM PST 24
Peak memory 281084 kb
Host smart-befabcb5-a786-498a-8aa9-74b6afff0bb7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185122613 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.4185122613
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.985374232
Short name T9
Test name
Test status
Simulation time 44237100 ps
CPU time 14.57 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:02:44 PM PST 24
Peak memory 264432 kb
Host smart-1f69f416-3c04-4c9a-9930-02043d349fb7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985374232 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.985374232
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.3890720181
Short name T1004
Test name
Test status
Simulation time 3632016600 ps
CPU time 682.96 seconds
Started Feb 21 01:03:19 PM PST 24
Finished Feb 21 01:14:43 PM PST 24
Peak memory 334416 kb
Host smart-4692c30b-db09-47f8-a59f-3b63dab0b882
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890720181 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.3890720181
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.3365645793
Short name T1
Test name
Test status
Simulation time 1427415900 ps
CPU time 173.76 seconds
Started Feb 21 01:09:19 PM PST 24
Finished Feb 21 01:12:13 PM PST 24
Peak memory 292636 kb
Host smart-9b577d20-f275-4bb7-9744-6d64bda3ce15
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365645793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.3365645793
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3375271157
Short name T217
Test name
Test status
Simulation time 146996800 ps
CPU time 31.08 seconds
Started Feb 21 12:32:39 PM PST 24
Finished Feb 21 12:33:10 PM PST 24
Peak memory 259732 kb
Host smart-2df4fdf4-45fc-4313-a4b0-54afae9a1b26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375271157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.3375271157
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2111339618
Short name T53
Test name
Test status
Simulation time 42984600 ps
CPU time 16.85 seconds
Started Feb 21 12:32:38 PM PST 24
Finished Feb 21 12:32:56 PM PST 24
Peak memory 259676 kb
Host smart-3e54aebd-a523-43b6-aeba-cbfbf039dbd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111339618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.2111339618
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.338748141
Short name T255
Test name
Test status
Simulation time 371385400 ps
CPU time 454.89 seconds
Started Feb 21 12:32:38 PM PST 24
Finished Feb 21 12:40:13 PM PST 24
Peak memory 263516 kb
Host smart-ae9adc2a-aa67-4509-80f9-3cae841da63e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338748141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
tl_intg_err.338748141
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.1104461707
Short name T30
Test name
Test status
Simulation time 14157500 ps
CPU time 13.6 seconds
Started Feb 21 01:02:33 PM PST 24
Finished Feb 21 01:02:47 PM PST 24
Peak memory 264548 kb
Host smart-5e46649d-0aa3-4183-876b-3f14ae15d825
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104461707 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.1104461707
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.2299041904
Short name T230
Test name
Test status
Simulation time 3070283300 ps
CPU time 2096.06 seconds
Started Feb 21 01:02:16 PM PST 24
Finished Feb 21 01:37:13 PM PST 24
Peak memory 264108 kb
Host smart-df73efec-606f-4a7f-b792-a09499faa0ec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299041904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.2299041904
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.2738491724
Short name T899
Test name
Test status
Simulation time 578231300 ps
CPU time 36.04 seconds
Started Feb 21 01:02:30 PM PST 24
Finished Feb 21 01:03:07 PM PST 24
Peak memory 274744 kb
Host smart-56b4a975-11ed-4da9-bdd0-a38c424ea461
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738491724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.2738491724
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.3585491977
Short name T199
Test name
Test status
Simulation time 483483605200 ps
CPU time 2008.98 seconds
Started Feb 21 01:03:50 PM PST 24
Finished Feb 21 01:37:20 PM PST 24
Peak memory 264388 kb
Host smart-e27b4232-da29-4356-a06b-c4fb6ab97658
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585491977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.3585491977
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.3210305171
Short name T182
Test name
Test status
Simulation time 68438500 ps
CPU time 110.48 seconds
Started Feb 21 01:10:47 PM PST 24
Finished Feb 21 01:12:38 PM PST 24
Peak memory 262760 kb
Host smart-f33b0219-3b27-419c-92ca-48c7d427bba7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210305171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.3210305171
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.4200749533
Short name T235
Test name
Test status
Simulation time 1264752900 ps
CPU time 53.05 seconds
Started Feb 21 12:32:38 PM PST 24
Finished Feb 21 12:33:31 PM PST 24
Peak memory 259640 kb
Host smart-4dcff239-af54-4e38-a999-3d7f6aec62bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200749533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.4200749533
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.499540343
Short name T1219
Test name
Test status
Simulation time 51253200 ps
CPU time 17.23 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:32:45 PM PST 24
Peak memory 278400 kb
Host smart-06a93f76-1046-4e6d-b790-140f68586f6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499540343 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.499540343
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1770054032
Short name T1188
Test name
Test status
Simulation time 26897400 ps
CPU time 13.54 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:32:41 PM PST 24
Peak memory 261832 kb
Host smart-89c9576f-73bf-46ce-8d1a-e3729fe73c57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770054032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.1
770054032
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2203370149
Short name T1173
Test name
Test status
Simulation time 24285000 ps
CPU time 13.38 seconds
Started Feb 21 12:32:30 PM PST 24
Finished Feb 21 12:32:44 PM PST 24
Peak memory 260940 kb
Host smart-edf6fe31-b49d-40f5-b499-cd555b8b8e13
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203370149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.2203370149
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.442739815
Short name T1210
Test name
Test status
Simulation time 94693200 ps
CPU time 16.92 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:32:44 PM PST 24
Peak memory 259736 kb
Host smart-5a76deb2-6d4d-489c-a0dd-d4ebdf195316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442739815 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.442739815
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3720443732
Short name T1167
Test name
Test status
Simulation time 64850800 ps
CPU time 16.3 seconds
Started Feb 21 12:32:15 PM PST 24
Finished Feb 21 12:32:32 PM PST 24
Peak memory 259576 kb
Host smart-0715549d-94a6-4131-9c53-0968ddd24ed4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720443732 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.3720443732
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.42655947
Short name T1252
Test name
Test status
Simulation time 13364400 ps
CPU time 15.69 seconds
Started Feb 21 12:32:38 PM PST 24
Finished Feb 21 12:32:54 PM PST 24
Peak memory 259504 kb
Host smart-e1f1ca2a-739b-4d09-b857-d53688925a49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655947 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.42655947
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1359932538
Short name T232
Test name
Test status
Simulation time 57985500 ps
CPU time 16.05 seconds
Started Feb 21 12:32:41 PM PST 24
Finished Feb 21 12:32:57 PM PST 24
Peak memory 263484 kb
Host smart-3c963cfe-8995-4131-a189-d6d10432b254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359932538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1
359932538
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3478947361
Short name T1272
Test name
Test status
Simulation time 941881900 ps
CPU time 30.29 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:32:58 PM PST 24
Peak memory 259716 kb
Host smart-f9741f15-1b38-4f99-a7be-f466594f1295
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478947361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.3478947361
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.4191999203
Short name T1193
Test name
Test status
Simulation time 9759509600 ps
CPU time 44.36 seconds
Started Feb 21 12:32:46 PM PST 24
Finished Feb 21 12:33:33 PM PST 24
Peak memory 259752 kb
Host smart-86d61ae0-8a87-4b15-be4f-f6ed321b6eb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191999203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.4191999203
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.743714958
Short name T1160
Test name
Test status
Simulation time 83045700 ps
CPU time 38.91 seconds
Started Feb 21 12:32:19 PM PST 24
Finished Feb 21 12:33:00 PM PST 24
Peak memory 259712 kb
Host smart-9a529918-8048-43be-81d8-ea99f9c71e21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743714958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_hw_reset.743714958
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3366458666
Short name T190
Test name
Test status
Simulation time 173735500 ps
CPU time 14.78 seconds
Started Feb 21 12:32:20 PM PST 24
Finished Feb 21 12:32:36 PM PST 24
Peak memory 276564 kb
Host smart-a4c4430f-e044-4054-8364-272bcc752c59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366458666 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3366458666
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.246785568
Short name T1192
Test name
Test status
Simulation time 103007600 ps
CPU time 14.64 seconds
Started Feb 21 12:32:19 PM PST 24
Finished Feb 21 12:32:35 PM PST 24
Peak memory 259896 kb
Host smart-a71f19fa-68cb-4de7-ad06-17ededc7f2e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246785568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_csr_rw.246785568
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1072186083
Short name T1140
Test name
Test status
Simulation time 29921800 ps
CPU time 13.53 seconds
Started Feb 21 12:32:29 PM PST 24
Finished Feb 21 12:32:43 PM PST 24
Peak memory 263148 kb
Host smart-7c9f7e41-888a-4648-b932-dbc6dacda674
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072186083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.1072186083
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.150961796
Short name T1170
Test name
Test status
Simulation time 16155900 ps
CPU time 13.29 seconds
Started Feb 21 12:32:25 PM PST 24
Finished Feb 21 12:32:39 PM PST 24
Peak memory 260908 kb
Host smart-e1759ebe-c9e7-416a-ab84-cd16583f0d87
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150961796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem
_walk.150961796
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1948795278
Short name T1263
Test name
Test status
Simulation time 97687200 ps
CPU time 17.72 seconds
Started Feb 21 12:32:28 PM PST 24
Finished Feb 21 12:32:51 PM PST 24
Peak memory 259768 kb
Host smart-69a7a8bc-1905-4cf4-8a1f-af25dd5ce4df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948795278 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.1948795278
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.794851476
Short name T1209
Test name
Test status
Simulation time 35421400 ps
CPU time 15.84 seconds
Started Feb 21 12:32:25 PM PST 24
Finished Feb 21 12:32:41 PM PST 24
Peak memory 259720 kb
Host smart-6550ed0a-2668-4cf2-ab78-efcddc4a272b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794851476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.794851476
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2637576484
Short name T1247
Test name
Test status
Simulation time 41297900 ps
CPU time 15.57 seconds
Started Feb 21 12:32:41 PM PST 24
Finished Feb 21 12:32:57 PM PST 24
Peak memory 259588 kb
Host smart-032cce19-d57d-49f3-8b6f-cbd3b088dd46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637576484 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.2637576484
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3934021100
Short name T1176
Test name
Test status
Simulation time 52829500 ps
CPU time 15.97 seconds
Started Feb 21 12:32:32 PM PST 24
Finished Feb 21 12:32:49 PM PST 24
Peak memory 263496 kb
Host smart-76fe9cd5-af20-4a8b-89cd-b76445433721
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934021100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3
934021100
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3177739827
Short name T1231
Test name
Test status
Simulation time 53039200 ps
CPU time 15.55 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 276784 kb
Host smart-6762a1d2-0202-4009-96be-e61f467c19a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177739827 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3177739827
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2837275092
Short name T1178
Test name
Test status
Simulation time 159079200 ps
CPU time 16.61 seconds
Started Feb 21 12:32:42 PM PST 24
Finished Feb 21 12:32:59 PM PST 24
Peak memory 259892 kb
Host smart-3e95a3de-a015-41bc-8baa-b825d737c9bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837275092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.2837275092
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3091529624
Short name T1241
Test name
Test status
Simulation time 66700200 ps
CPU time 13.36 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 261956 kb
Host smart-9fe3a8a1-b1d6-4319-8cb1-9243f76c65a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091529624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
3091529624
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.4212499458
Short name T1136
Test name
Test status
Simulation time 297868800 ps
CPU time 35.48 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:33 PM PST 24
Peak memory 260120 kb
Host smart-021a35c5-64d8-4671-908f-186001d923a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212499458 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.4212499458
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1664100363
Short name T1237
Test name
Test status
Simulation time 158065600 ps
CPU time 15.84 seconds
Started Feb 21 12:32:49 PM PST 24
Finished Feb 21 12:33:07 PM PST 24
Peak memory 259660 kb
Host smart-3ab85e3d-b6a3-4400-9d96-db9aea864730
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664100363 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.1664100363
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1826717275
Short name T1182
Test name
Test status
Simulation time 12677700 ps
CPU time 15.45 seconds
Started Feb 21 12:32:50 PM PST 24
Finished Feb 21 12:33:07 PM PST 24
Peak memory 259608 kb
Host smart-762b0f4e-6448-4890-8b1b-fe1b71dbeda5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826717275 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.1826717275
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.203941381
Short name T365
Test name
Test status
Simulation time 2299860800 ps
CPU time 459 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:40:35 PM PST 24
Peak memory 263492 kb
Host smart-5d930468-103f-43b4-b505-89a9d81e699b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203941381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl
_tl_intg_err.203941381
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.66487465
Short name T258
Test name
Test status
Simulation time 48910100 ps
CPU time 14.52 seconds
Started Feb 21 12:32:58 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 261536 kb
Host smart-4400310a-2fa5-4153-ba18-fe93414c9219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66487465 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.66487465
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.288008051
Short name T1251
Test name
Test status
Simulation time 172528500 ps
CPU time 17.25 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:15 PM PST 24
Peak memory 259736 kb
Host smart-1c6cc752-1dcb-4158-9325-42ddbb3e2a5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288008051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.flash_ctrl_csr_rw.288008051
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.337729656
Short name T1211
Test name
Test status
Simulation time 53520900 ps
CPU time 13.58 seconds
Started Feb 21 12:32:51 PM PST 24
Finished Feb 21 12:33:06 PM PST 24
Peak memory 261816 kb
Host smart-0b5d4e1e-6999-47b9-bb43-8c3bee3ea36f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337729656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.337729656
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3561456230
Short name T1175
Test name
Test status
Simulation time 119620600 ps
CPU time 18.93 seconds
Started Feb 21 12:32:51 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 259816 kb
Host smart-86c31364-d327-458a-a0cf-55580737368e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561456230 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.3561456230
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.441428206
Short name T1207
Test name
Test status
Simulation time 22089100 ps
CPU time 15.46 seconds
Started Feb 21 12:33:01 PM PST 24
Finished Feb 21 12:33:19 PM PST 24
Peak memory 259932 kb
Host smart-f6600f08-aacd-4819-9910-7be56efcdeec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441428206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.441428206
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2427670135
Short name T1145
Test name
Test status
Simulation time 24510700 ps
CPU time 15.7 seconds
Started Feb 21 12:32:59 PM PST 24
Finished Feb 21 12:33:16 PM PST 24
Peak memory 259568 kb
Host smart-9adbf769-6638-44b8-94d9-876b96271edb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427670135 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2427670135
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3077760377
Short name T1228
Test name
Test status
Simulation time 99546400 ps
CPU time 16.68 seconds
Started Feb 21 12:32:48 PM PST 24
Finished Feb 21 12:33:08 PM PST 24
Peak memory 263840 kb
Host smart-11dece0f-c3f3-49c6-971c-fc7d36fab717
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077760377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
3077760377
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2369026097
Short name T309
Test name
Test status
Simulation time 187210300 ps
CPU time 18.81 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 276872 kb
Host smart-9a1bb2b1-3b55-4e8e-8ecb-7b77740cf15f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369026097 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2369026097
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.4253104199
Short name T1258
Test name
Test status
Simulation time 28965900 ps
CPU time 14.69 seconds
Started Feb 21 12:33:03 PM PST 24
Finished Feb 21 12:33:19 PM PST 24
Peak memory 259656 kb
Host smart-c05f7f54-cb88-4271-a25f-f06b68b818dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253104199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.4253104199
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2124900785
Short name T1185
Test name
Test status
Simulation time 408021000 ps
CPU time 18.08 seconds
Started Feb 21 12:32:47 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 259816 kb
Host smart-22d3c264-b936-46c6-96ca-ea14be844fb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124900785 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.2124900785
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1418322446
Short name T1158
Test name
Test status
Simulation time 45179200 ps
CPU time 15.72 seconds
Started Feb 21 12:32:53 PM PST 24
Finished Feb 21 12:33:10 PM PST 24
Peak memory 259756 kb
Host smart-30bdeacf-9e42-4691-8b8a-46e50fb224c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418322446 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1418322446
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2274312020
Short name T1206
Test name
Test status
Simulation time 87930800 ps
CPU time 15.61 seconds
Started Feb 21 12:33:05 PM PST 24
Finished Feb 21 12:33:23 PM PST 24
Peak memory 259612 kb
Host smart-1bb9bd6f-1e4e-4758-9736-9c40cbee3ec8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274312020 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.2274312020
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3312750830
Short name T1155
Test name
Test status
Simulation time 31560200 ps
CPU time 16.37 seconds
Started Feb 21 12:32:58 PM PST 24
Finished Feb 21 12:33:15 PM PST 24
Peak memory 263468 kb
Host smart-92adf4e2-e0c3-4151-bef1-baa13779be48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312750830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
3312750830
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1773335025
Short name T367
Test name
Test status
Simulation time 264709600 ps
CPU time 457.15 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:40:33 PM PST 24
Peak memory 263564 kb
Host smart-404e1dff-fa6c-409e-91c2-ce67267c75a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773335025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.1773335025
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.278670235
Short name T245
Test name
Test status
Simulation time 348374400 ps
CPU time 18.1 seconds
Started Feb 21 12:32:58 PM PST 24
Finished Feb 21 12:33:16 PM PST 24
Peak memory 270716 kb
Host smart-f81d2329-e4fe-4ac8-9870-78b285600ab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278670235 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.278670235
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2903404080
Short name T420
Test name
Test status
Simulation time 37510100 ps
CPU time 16.92 seconds
Started Feb 21 12:32:59 PM PST 24
Finished Feb 21 12:33:17 PM PST 24
Peak memory 259724 kb
Host smart-8ab4d681-1ecd-481c-92c2-0e3404bc4ee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903404080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.2903404080
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1540058705
Short name T1163
Test name
Test status
Simulation time 21341400 ps
CPU time 13.32 seconds
Started Feb 21 12:33:05 PM PST 24
Finished Feb 21 12:33:19 PM PST 24
Peak memory 262040 kb
Host smart-e1601a9c-c378-4b66-bf80-6a935b46c5bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540058705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
1540058705
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1353785115
Short name T1274
Test name
Test status
Simulation time 65962700 ps
CPU time 29.13 seconds
Started Feb 21 12:32:56 PM PST 24
Finished Feb 21 12:33:26 PM PST 24
Peak memory 259560 kb
Host smart-235c2b28-6e0e-4a27-8bb5-fa2e833ec3b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353785115 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1353785115
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2846410857
Short name T1194
Test name
Test status
Simulation time 24701100 ps
CPU time 15.56 seconds
Started Feb 21 12:32:52 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 259576 kb
Host smart-f4da4318-d5b3-4607-8e4e-cdb077beb5eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846410857 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.2846410857
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1582780617
Short name T1201
Test name
Test status
Simulation time 18102000 ps
CPU time 15.58 seconds
Started Feb 21 12:33:05 PM PST 24
Finished Feb 21 12:33:22 PM PST 24
Peak memory 259548 kb
Host smart-712b3e9e-5276-4af0-828e-099056d6612c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582780617 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.1582780617
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.559991097
Short name T1264
Test name
Test status
Simulation time 121342100 ps
CPU time 16.83 seconds
Started Feb 21 12:32:59 PM PST 24
Finished Feb 21 12:33:17 PM PST 24
Peak memory 270680 kb
Host smart-a4280437-8865-4e9c-8688-cfa5a5ce8a50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559991097 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.559991097
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.81820737
Short name T1152
Test name
Test status
Simulation time 48074800 ps
CPU time 14.58 seconds
Started Feb 21 12:33:04 PM PST 24
Finished Feb 21 12:33:21 PM PST 24
Peak memory 259708 kb
Host smart-732ed1c6-78d4-423a-be1c-9491348f8ca5
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81820737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 14.flash_ctrl_csr_rw.81820737
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3866559301
Short name T1267
Test name
Test status
Simulation time 17647500 ps
CPU time 13.5 seconds
Started Feb 21 12:32:53 PM PST 24
Finished Feb 21 12:33:08 PM PST 24
Peak memory 262428 kb
Host smart-7224a75a-5e18-4db4-8fae-6c665b87c129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866559301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
3866559301
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1732539028
Short name T1271
Test name
Test status
Simulation time 150939600 ps
CPU time 18.06 seconds
Started Feb 21 12:33:05 PM PST 24
Finished Feb 21 12:33:25 PM PST 24
Peak memory 259928 kb
Host smart-49fd0390-5880-4451-8b59-74703c071089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732539028 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.1732539028
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3314356893
Short name T1168
Test name
Test status
Simulation time 46832300 ps
CPU time 15.75 seconds
Started Feb 21 12:32:58 PM PST 24
Finished Feb 21 12:33:14 PM PST 24
Peak memory 259596 kb
Host smart-5e9e7842-276e-4ab2-8b09-636a0fc5d52e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314356893 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.3314356893
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.816944042
Short name T1256
Test name
Test status
Simulation time 13736300 ps
CPU time 13.23 seconds
Started Feb 21 12:32:53 PM PST 24
Finished Feb 21 12:33:08 PM PST 24
Peak memory 259652 kb
Host smart-8a9913e2-bafc-4cf9-845b-c17a5a2cada6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816944042 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.816944042
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1428350635
Short name T1245
Test name
Test status
Simulation time 786384800 ps
CPU time 755.15 seconds
Started Feb 21 12:33:03 PM PST 24
Finished Feb 21 12:45:40 PM PST 24
Peak memory 262148 kb
Host smart-1359fa0d-7a26-4a84-9473-2cd56aa6935b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428350635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.1428350635
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3531196743
Short name T361
Test name
Test status
Simulation time 307117000 ps
CPU time 16.28 seconds
Started Feb 21 12:32:56 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 277108 kb
Host smart-82797220-872b-4b91-ad54-14d3e17b9b0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531196743 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3531196743
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1547420657
Short name T1141
Test name
Test status
Simulation time 66379900 ps
CPU time 16.11 seconds
Started Feb 21 12:33:01 PM PST 24
Finished Feb 21 12:33:19 PM PST 24
Peak memory 259664 kb
Host smart-84123c8d-44d4-4187-a73e-f5431a1a8a93
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547420657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.1547420657
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3152348075
Short name T307
Test name
Test status
Simulation time 257315100 ps
CPU time 36.19 seconds
Started Feb 21 12:33:05 PM PST 24
Finished Feb 21 12:33:43 PM PST 24
Peak memory 263596 kb
Host smart-4474ab5c-4911-4852-bdba-c6abaf74d632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152348075 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.3152348075
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3394553303
Short name T1203
Test name
Test status
Simulation time 50791400 ps
CPU time 13.78 seconds
Started Feb 21 12:33:07 PM PST 24
Finished Feb 21 12:33:22 PM PST 24
Peak memory 259612 kb
Host smart-db6900bd-0ec2-4252-ba25-abd56ae15dc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394553303 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.3394553303
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1472880452
Short name T1218
Test name
Test status
Simulation time 18211700 ps
CPU time 15.85 seconds
Started Feb 21 12:33:07 PM PST 24
Finished Feb 21 12:33:24 PM PST 24
Peak memory 259620 kb
Host smart-3b1adc84-9f9a-4caf-8e5b-ca336f970472
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472880452 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.1472880452
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1064257632
Short name T1232
Test name
Test status
Simulation time 68402900 ps
CPU time 15.38 seconds
Started Feb 21 12:32:55 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 263560 kb
Host smart-4f767f42-b328-4fd3-a644-bf755f9c16e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064257632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
1064257632
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.775537360
Short name T1257
Test name
Test status
Simulation time 1388829900 ps
CPU time 887.5 seconds
Started Feb 21 12:33:01 PM PST 24
Finished Feb 21 12:47:50 PM PST 24
Peak memory 263540 kb
Host smart-ea372c96-344a-4051-a239-1b966c1eaf90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775537360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_tl_intg_err.775537360
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.864362913
Short name T310
Test name
Test status
Simulation time 214301800 ps
CPU time 18.94 seconds
Started Feb 21 12:32:56 PM PST 24
Finished Feb 21 12:33:16 PM PST 24
Peak memory 271744 kb
Host smart-d05a2f69-2608-4484-bcb0-98fffcef51ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864362913 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.864362913
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.257218393
Short name T1200
Test name
Test status
Simulation time 38650600 ps
CPU time 13.92 seconds
Started Feb 21 12:32:53 PM PST 24
Finished Feb 21 12:33:08 PM PST 24
Peak memory 259756 kb
Host smart-9c894312-408e-4f73-b479-7f1a9e64b50a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257218393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.flash_ctrl_csr_rw.257218393
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.776529069
Short name T358
Test name
Test status
Simulation time 53301100 ps
CPU time 13.5 seconds
Started Feb 21 12:33:01 PM PST 24
Finished Feb 21 12:33:16 PM PST 24
Peak memory 261756 kb
Host smart-75c2e484-9e7b-400c-a232-8e2887f0828e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776529069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.776529069
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.156986057
Short name T311
Test name
Test status
Simulation time 389789500 ps
CPU time 15.78 seconds
Started Feb 21 12:33:03 PM PST 24
Finished Feb 21 12:33:21 PM PST 24
Peak memory 261624 kb
Host smart-9f1fdf75-8524-438a-9225-708a14427a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156986057 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.156986057
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.727125450
Short name T1171
Test name
Test status
Simulation time 12436100 ps
CPU time 15.79 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:14 PM PST 24
Peak memory 259676 kb
Host smart-bbe14001-0125-4d0a-ab78-00a2beba49d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727125450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.727125450
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2910327827
Short name T1259
Test name
Test status
Simulation time 18353200 ps
CPU time 13.04 seconds
Started Feb 21 12:33:01 PM PST 24
Finished Feb 21 12:33:16 PM PST 24
Peak memory 259632 kb
Host smart-2ecdcbb6-02bc-4425-93b0-d1893c0e415a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910327827 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2910327827
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3648889282
Short name T1260
Test name
Test status
Simulation time 112975700 ps
CPU time 15.53 seconds
Started Feb 21 12:33:03 PM PST 24
Finished Feb 21 12:33:20 PM PST 24
Peak memory 263484 kb
Host smart-7469931e-7ead-4352-99ad-af85d672c3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648889282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
3648889282
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3344078068
Short name T192
Test name
Test status
Simulation time 334457400 ps
CPU time 891.01 seconds
Started Feb 21 12:32:53 PM PST 24
Finished Feb 21 12:47:45 PM PST 24
Peak memory 263528 kb
Host smart-b2a3a538-693e-4ab3-b669-c150b355f3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344078068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.3344078068
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2994177997
Short name T308
Test name
Test status
Simulation time 496144200 ps
CPU time 17.61 seconds
Started Feb 21 12:32:48 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 269784 kb
Host smart-8844b13e-e38a-47b7-9566-35d818155982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994177997 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.2994177997
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1653336498
Short name T303
Test name
Test status
Simulation time 1212982000 ps
CPU time 17.29 seconds
Started Feb 21 12:33:01 PM PST 24
Finished Feb 21 12:33:19 PM PST 24
Peak memory 259748 kb
Host smart-22ce15eb-0ae6-4760-9442-1b39ab908813
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653336498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.1653336498
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3565774165
Short name T352
Test name
Test status
Simulation time 15191200 ps
CPU time 13.36 seconds
Started Feb 21 12:32:59 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 260220 kb
Host smart-d0548559-0c99-4b02-ad1d-6da05c8b67db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565774165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
3565774165
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3678767628
Short name T1187
Test name
Test status
Simulation time 2066211100 ps
CPU time 34.71 seconds
Started Feb 21 12:33:01 PM PST 24
Finished Feb 21 12:33:37 PM PST 24
Peak memory 259812 kb
Host smart-3160148b-b09d-4524-9e1a-32147ca0fb4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678767628 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.3678767628
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.980843847
Short name T1195
Test name
Test status
Simulation time 31691800 ps
CPU time 15.41 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 259584 kb
Host smart-749acb8f-bed4-449b-8873-34185effd8d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980843847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.980843847
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3947616391
Short name T1165
Test name
Test status
Simulation time 39131000 ps
CPU time 15.33 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 259684 kb
Host smart-864faa9c-373a-4f09-8662-49cfede9b27c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947616391 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.3947616391
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2745163564
Short name T216
Test name
Test status
Simulation time 67680600 ps
CPU time 18.53 seconds
Started Feb 21 12:32:48 PM PST 24
Finished Feb 21 12:33:08 PM PST 24
Peak memory 263640 kb
Host smart-a9c93a8a-1632-4e26-bb19-cb5a10427af1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745163564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
2745163564
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1550885990
Short name T364
Test name
Test status
Simulation time 3100716100 ps
CPU time 451.22 seconds
Started Feb 21 12:32:58 PM PST 24
Finished Feb 21 12:40:30 PM PST 24
Peak memory 263512 kb
Host smart-4559e3b8-4c64-40de-b4cf-5f2b9b26f7c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550885990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.1550885990
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1617148484
Short name T1220
Test name
Test status
Simulation time 164885900 ps
CPU time 18.5 seconds
Started Feb 21 12:32:52 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 271692 kb
Host smart-9a2e167f-68a0-49cc-ad26-0cacd9535ec8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617148484 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1617148484
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3070442575
Short name T305
Test name
Test status
Simulation time 72331400 ps
CPU time 17.23 seconds
Started Feb 21 12:33:08 PM PST 24
Finished Feb 21 12:33:26 PM PST 24
Peak memory 259648 kb
Host smart-bd664721-50fc-4f12-b61b-9f775f2d5fc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070442575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.3070442575
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3111274731
Short name T356
Test name
Test status
Simulation time 52104600 ps
CPU time 13.45 seconds
Started Feb 21 12:33:00 PM PST 24
Finished Feb 21 12:33:14 PM PST 24
Peak memory 260204 kb
Host smart-3670e352-5167-4611-ade8-9a0a0d54b117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111274731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3111274731
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.743591190
Short name T1242
Test name
Test status
Simulation time 84316700 ps
CPU time 17.88 seconds
Started Feb 21 12:33:01 PM PST 24
Finished Feb 21 12:33:20 PM PST 24
Peak memory 259708 kb
Host smart-b80342ec-775a-46e9-8ff7-844e6207e2ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743591190 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.743591190
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1523015653
Short name T1239
Test name
Test status
Simulation time 40525000 ps
CPU time 15.39 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 259700 kb
Host smart-ba49c5d1-72c1-4128-9833-6f5ca0ac0100
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523015653 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1523015653
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3465576278
Short name T1174
Test name
Test status
Simulation time 41386000 ps
CPU time 13.14 seconds
Started Feb 21 12:33:06 PM PST 24
Finished Feb 21 12:33:21 PM PST 24
Peak memory 259708 kb
Host smart-d68ab96c-dfe1-4df5-80e9-634f449fd7ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465576278 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.3465576278
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2113688589
Short name T247
Test name
Test status
Simulation time 48740900 ps
CPU time 15.47 seconds
Started Feb 21 12:32:59 PM PST 24
Finished Feb 21 12:33:16 PM PST 24
Peak memory 263448 kb
Host smart-15afb7d8-44e8-4654-a342-7ac8ad1f5509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113688589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
2113688589
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1067376918
Short name T368
Test name
Test status
Simulation time 2795404900 ps
CPU time 906.67 seconds
Started Feb 21 12:33:32 PM PST 24
Finished Feb 21 12:48:39 PM PST 24
Peak memory 263596 kb
Host smart-05ec21cf-00fa-4742-94d9-ec561c6a39d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067376918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.1067376918
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.812965257
Short name T1146
Test name
Test status
Simulation time 180408800 ps
CPU time 17.64 seconds
Started Feb 21 12:33:04 PM PST 24
Finished Feb 21 12:33:23 PM PST 24
Peak memory 275412 kb
Host smart-2ad0bd59-6626-4242-8150-5e67b42345fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812965257 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.812965257
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3227017163
Short name T1254
Test name
Test status
Simulation time 67279600 ps
CPU time 14.81 seconds
Started Feb 21 12:32:52 PM PST 24
Finished Feb 21 12:33:08 PM PST 24
Peak memory 259648 kb
Host smart-172e8fb1-821d-4d3f-8cb1-9d161e7b4ff6
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227017163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.3227017163
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2252975009
Short name T1225
Test name
Test status
Simulation time 71721000 ps
CPU time 13.51 seconds
Started Feb 21 12:33:08 PM PST 24
Finished Feb 21 12:33:23 PM PST 24
Peak memory 261304 kb
Host smart-aeb5e12e-c5c4-4002-b84a-666e0433fd04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252975009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
2252975009
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1346996216
Short name T1190
Test name
Test status
Simulation time 149058800 ps
CPU time 17.82 seconds
Started Feb 21 12:33:01 PM PST 24
Finished Feb 21 12:33:20 PM PST 24
Peak memory 259760 kb
Host smart-312149ca-9313-42e6-b99c-d2c5ef6193ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346996216 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.1346996216
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3189286639
Short name T1270
Test name
Test status
Simulation time 47955500 ps
CPU time 15.41 seconds
Started Feb 21 12:32:58 PM PST 24
Finished Feb 21 12:33:14 PM PST 24
Peak memory 259572 kb
Host smart-24d55449-0c0f-4b97-a835-a68acb5c01d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189286639 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3189286639
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3394555698
Short name T1186
Test name
Test status
Simulation time 82320800 ps
CPU time 15.62 seconds
Started Feb 21 12:33:11 PM PST 24
Finished Feb 21 12:33:27 PM PST 24
Peak memory 259716 kb
Host smart-31e14514-1135-497d-ab14-a38efd887264
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394555698 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.3394555698
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.4095813525
Short name T370
Test name
Test status
Simulation time 273843100 ps
CPU time 454.48 seconds
Started Feb 21 12:33:07 PM PST 24
Finished Feb 21 12:40:43 PM PST 24
Peak memory 263500 kb
Host smart-d36af65a-6def-4301-b17e-56977c39fc7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095813525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.4095813525
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3766698156
Short name T312
Test name
Test status
Simulation time 1694737700 ps
CPU time 40.8 seconds
Started Feb 21 12:32:38 PM PST 24
Finished Feb 21 12:33:20 PM PST 24
Peak memory 259724 kb
Host smart-fcc8e154-fffb-4c0e-8a25-c2943ec3d673
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766698156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.3766698156
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1573766712
Short name T1147
Test name
Test status
Simulation time 4788546700 ps
CPU time 42.89 seconds
Started Feb 21 12:32:49 PM PST 24
Finished Feb 21 12:33:34 PM PST 24
Peak memory 259776 kb
Host smart-39127084-a8a2-4e53-a7ad-6062b08298ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573766712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.1573766712
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3943042940
Short name T1180
Test name
Test status
Simulation time 28243900 ps
CPU time 30.99 seconds
Started Feb 21 12:32:40 PM PST 24
Finished Feb 21 12:33:12 PM PST 24
Peak memory 259716 kb
Host smart-2c35b092-4091-488c-bc36-b35e1ba0836d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943042940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.3943042940
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1232545046
Short name T1191
Test name
Test status
Simulation time 149899500 ps
CPU time 18.94 seconds
Started Feb 21 12:32:40 PM PST 24
Finished Feb 21 12:32:59 PM PST 24
Peak memory 277948 kb
Host smart-778e3c02-44ca-466b-a979-e6da969a4f5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232545046 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.1232545046
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3203770123
Short name T306
Test name
Test status
Simulation time 252871700 ps
CPU time 17.99 seconds
Started Feb 21 12:32:34 PM PST 24
Finished Feb 21 12:32:54 PM PST 24
Peak memory 259660 kb
Host smart-c54d3305-fd1c-4222-bef3-09c273a8ecbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203770123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.3203770123
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.335014844
Short name T354
Test name
Test status
Simulation time 44210100 ps
CPU time 13.05 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 260176 kb
Host smart-b5ab9f09-28dd-4c03-b90a-b3e35872e2bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335014844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.335014844
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.615806051
Short name T1135
Test name
Test status
Simulation time 161637800 ps
CPU time 13.23 seconds
Started Feb 21 12:32:28 PM PST 24
Finished Feb 21 12:32:42 PM PST 24
Peak memory 259216 kb
Host smart-6f3aeaf8-b528-42a2-b3a5-b9eea5f5628c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615806051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem
_walk.615806051
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2712184155
Short name T1157
Test name
Test status
Simulation time 100883100 ps
CPU time 15.65 seconds
Started Feb 21 12:32:28 PM PST 24
Finished Feb 21 12:32:45 PM PST 24
Peak memory 262356 kb
Host smart-29de9c7e-95f4-4515-95f2-9b3ed3948d3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712184155 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.2712184155
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2484441371
Short name T1208
Test name
Test status
Simulation time 19938700 ps
CPU time 15.61 seconds
Started Feb 21 12:32:36 PM PST 24
Finished Feb 21 12:32:52 PM PST 24
Peak memory 259692 kb
Host smart-adbfec94-3956-4d35-89fb-f08169cbdd57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484441371 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2484441371
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1850959622
Short name T1269
Test name
Test status
Simulation time 11826000 ps
CPU time 15.53 seconds
Started Feb 21 12:32:38 PM PST 24
Finished Feb 21 12:32:54 PM PST 24
Peak memory 259668 kb
Host smart-6d262e2c-6e7b-4fee-83b9-516fd8ac5141
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850959622 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.1850959622
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2612612952
Short name T249
Test name
Test status
Simulation time 237645300 ps
CPU time 17.06 seconds
Started Feb 21 12:32:37 PM PST 24
Finished Feb 21 12:32:55 PM PST 24
Peak memory 263548 kb
Host smart-004fd1d5-ddb5-42bc-9677-5a38cb75902e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612612952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.2
612612952
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2215786678
Short name T353
Test name
Test status
Simulation time 18268800 ps
CPU time 13.58 seconds
Started Feb 21 12:33:05 PM PST 24
Finished Feb 21 12:33:20 PM PST 24
Peak memory 261924 kb
Host smart-2cbf3056-109f-4160-8fda-97515b998183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215786678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
2215786678
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.71016314
Short name T1212
Test name
Test status
Simulation time 16810800 ps
CPU time 13.45 seconds
Started Feb 21 12:33:02 PM PST 24
Finished Feb 21 12:33:16 PM PST 24
Peak memory 261424 kb
Host smart-45ecd845-3372-47fe-9f1b-d02abfa338de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71016314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.71016314
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1683754848
Short name T1159
Test name
Test status
Simulation time 18887800 ps
CPU time 13.5 seconds
Started Feb 21 12:33:04 PM PST 24
Finished Feb 21 12:33:19 PM PST 24
Peak memory 260220 kb
Host smart-3a27b7da-4145-45c3-974a-ab145fe54266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683754848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
1683754848
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.889464783
Short name T1166
Test name
Test status
Simulation time 43295500 ps
CPU time 13.37 seconds
Started Feb 21 12:33:03 PM PST 24
Finished Feb 21 12:33:18 PM PST 24
Peak memory 260552 kb
Host smart-6e6a937e-7465-4fe1-820a-db7ec673832e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889464783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.889464783
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1793960364
Short name T1198
Test name
Test status
Simulation time 55239200 ps
CPU time 13.46 seconds
Started Feb 21 12:32:58 PM PST 24
Finished Feb 21 12:33:12 PM PST 24
Peak memory 262020 kb
Host smart-32362e56-0e68-44fb-9031-6a4e9e163145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793960364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
1793960364
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1674347243
Short name T1215
Test name
Test status
Simulation time 224730600 ps
CPU time 13.52 seconds
Started Feb 21 12:33:05 PM PST 24
Finished Feb 21 12:33:20 PM PST 24
Peak memory 261796 kb
Host smart-099741bd-b085-4604-96ac-79e683c5e6a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674347243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
1674347243
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.406187560
Short name T355
Test name
Test status
Simulation time 26886200 ps
CPU time 13.39 seconds
Started Feb 21 12:32:58 PM PST 24
Finished Feb 21 12:33:12 PM PST 24
Peak memory 260220 kb
Host smart-1cfdac48-5ab6-4185-a66b-977378024cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406187560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.406187560
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1486034568
Short name T1261
Test name
Test status
Simulation time 53367300 ps
CPU time 13.52 seconds
Started Feb 21 12:32:59 PM PST 24
Finished Feb 21 12:33:14 PM PST 24
Peak memory 262200 kb
Host smart-70a2a015-a7d6-4379-befa-1ed10a9191a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486034568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
1486034568
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3793223069
Short name T1214
Test name
Test status
Simulation time 89752300 ps
CPU time 13.36 seconds
Started Feb 21 12:33:02 PM PST 24
Finished Feb 21 12:33:17 PM PST 24
Peak memory 260320 kb
Host smart-fb305fa9-1818-4821-9e9c-ab104207dcf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793223069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
3793223069
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3335007221
Short name T1265
Test name
Test status
Simulation time 68263800 ps
CPU time 13.33 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 261804 kb
Host smart-0702c00b-7e2a-4404-aee1-8b6a0e90f2f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335007221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
3335007221
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2848163214
Short name T1213
Test name
Test status
Simulation time 422493700 ps
CPU time 32.83 seconds
Started Feb 21 12:32:56 PM PST 24
Finished Feb 21 12:33:40 PM PST 24
Peak memory 259728 kb
Host smart-5cb174d5-b3d0-4e35-ae3d-20d70f960224
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848163214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.2848163214
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.791523992
Short name T1183
Test name
Test status
Simulation time 3067491600 ps
CPU time 46.92 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:33:42 PM PST 24
Peak memory 259756 kb
Host smart-acca634b-ede5-4ce8-a2ca-e1fd9de55569
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791523992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_bit_bash.791523992
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3271006686
Short name T1189
Test name
Test status
Simulation time 67650600 ps
CPU time 30.23 seconds
Started Feb 21 12:32:46 PM PST 24
Finished Feb 21 12:33:19 PM PST 24
Peak memory 259648 kb
Host smart-f878970d-3c70-41ab-97dd-c63d5f8edca9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271006686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3271006686
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1671256
Short name T1142
Test name
Test status
Simulation time 166243800 ps
CPU time 18.49 seconds
Started Feb 21 12:32:51 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 271776 kb
Host smart-82dbe668-78bf-4513-aa46-1d584cadb2a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671256 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1671256
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1148427937
Short name T54
Test name
Test status
Simulation time 69521800 ps
CPU time 14.89 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:33:10 PM PST 24
Peak memory 259736 kb
Host smart-6d9680d9-23a5-4c69-8bfc-8605c94751d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148427937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.1148427937
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3286869869
Short name T1179
Test name
Test status
Simulation time 54935400 ps
CPU time 13.55 seconds
Started Feb 21 12:32:56 PM PST 24
Finished Feb 21 12:33:10 PM PST 24
Peak memory 261856 kb
Host smart-efcd6d7e-455c-4148-a66f-8ca8b25509e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286869869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.3
286869869
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.106660196
Short name T263
Test name
Test status
Simulation time 31087800 ps
CPU time 13.63 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 260316 kb
Host smart-b03980a2-d7b5-4676-ac17-9573829d2bcd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106660196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_mem_partial_access.106660196
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1787988972
Short name T1137
Test name
Test status
Simulation time 39719600 ps
CPU time 13.27 seconds
Started Feb 21 12:32:39 PM PST 24
Finished Feb 21 12:32:53 PM PST 24
Peak memory 260112 kb
Host smart-3606d8a6-ca04-4056-8766-e2cee6ea2c7f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787988972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.1787988972
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4215600681
Short name T1202
Test name
Test status
Simulation time 123598600 ps
CPU time 34.15 seconds
Started Feb 21 12:32:47 PM PST 24
Finished Feb 21 12:33:25 PM PST 24
Peak memory 261360 kb
Host smart-3c35867d-6631-4b7d-b5a1-f18f3e2018d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215600681 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.4215600681
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2571548994
Short name T1197
Test name
Test status
Simulation time 26785600 ps
CPU time 15.51 seconds
Started Feb 21 12:33:00 PM PST 24
Finished Feb 21 12:33:17 PM PST 24
Peak memory 259616 kb
Host smart-da082c16-e172-4358-b4dc-ebb324812d2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571548994 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.2571548994
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1291265961
Short name T1238
Test name
Test status
Simulation time 13308500 ps
CPU time 13.17 seconds
Started Feb 21 12:32:48 PM PST 24
Finished Feb 21 12:33:04 PM PST 24
Peak memory 259664 kb
Host smart-3b18589c-8306-4563-8203-e2f6366867b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291265961 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.1291265961
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.242187448
Short name T251
Test name
Test status
Simulation time 57260800 ps
CPU time 16 seconds
Started Feb 21 12:32:30 PM PST 24
Finished Feb 21 12:32:46 PM PST 24
Peak memory 263472 kb
Host smart-8bfea3fc-3896-4510-9804-7b90c6c149a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242187448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.242187448
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.563618265
Short name T366
Test name
Test status
Simulation time 848048000 ps
CPU time 454.19 seconds
Started Feb 21 12:32:40 PM PST 24
Finished Feb 21 12:40:15 PM PST 24
Peak memory 262180 kb
Host smart-b606e8c8-e49b-431f-9574-45a727d3d3c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563618265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_
tl_intg_err.563618265
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1236301530
Short name T1235
Test name
Test status
Simulation time 15902600 ps
CPU time 13.48 seconds
Started Feb 21 12:33:02 PM PST 24
Finished Feb 21 12:33:17 PM PST 24
Peak memory 261808 kb
Host smart-89617add-70a6-4314-bf6b-c794279e2a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236301530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
1236301530
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3434645388
Short name T1224
Test name
Test status
Simulation time 16024700 ps
CPU time 13.37 seconds
Started Feb 21 12:32:58 PM PST 24
Finished Feb 21 12:33:12 PM PST 24
Peak memory 261784 kb
Host smart-c37e00d5-bd44-472e-b048-662fdb12945c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434645388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
3434645388
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3143072421
Short name T1162
Test name
Test status
Simulation time 18122500 ps
CPU time 13.45 seconds
Started Feb 21 12:33:02 PM PST 24
Finished Feb 21 12:33:17 PM PST 24
Peak memory 261840 kb
Host smart-ad9afa3e-746d-40aa-8eb5-6e08405540be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143072421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
3143072421
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2601483333
Short name T1236
Test name
Test status
Simulation time 26623700 ps
CPU time 13.4 seconds
Started Feb 21 12:32:55 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 261848 kb
Host smart-119b6945-f343-40d1-a0a1-5c5359145db2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601483333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
2601483333
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1121148359
Short name T359
Test name
Test status
Simulation time 28438700 ps
CPU time 13.28 seconds
Started Feb 21 12:32:59 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 262096 kb
Host smart-a54897cb-cf62-4219-b832-9b5a20ec114f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121148359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
1121148359
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2125641773
Short name T349
Test name
Test status
Simulation time 31235200 ps
CPU time 13.37 seconds
Started Feb 21 12:33:03 PM PST 24
Finished Feb 21 12:33:18 PM PST 24
Peak memory 261828 kb
Host smart-6a241da5-e4c2-4f77-9eec-01e97207c37e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125641773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
2125641773
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2668196084
Short name T1196
Test name
Test status
Simulation time 52544600 ps
CPU time 13.58 seconds
Started Feb 21 12:33:03 PM PST 24
Finished Feb 21 12:33:18 PM PST 24
Peak memory 262140 kb
Host smart-a06f25fe-91fe-4045-aa3c-70a2bc312ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668196084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
2668196084
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.808677540
Short name T1234
Test name
Test status
Simulation time 43647700 ps
CPU time 13.39 seconds
Started Feb 21 12:33:04 PM PST 24
Finished Feb 21 12:33:19 PM PST 24
Peak memory 260172 kb
Host smart-63b14bc7-1b1e-4afe-b128-7f8a82dcaf1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808677540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.808677540
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3406346492
Short name T1216
Test name
Test status
Simulation time 66625000 ps
CPU time 13.78 seconds
Started Feb 21 12:33:04 PM PST 24
Finished Feb 21 12:33:20 PM PST 24
Peak memory 261908 kb
Host smart-d44c50b9-3adb-4d36-97fc-92ddb35047db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406346492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
3406346492
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2246551514
Short name T350
Test name
Test status
Simulation time 45056600 ps
CPU time 13.6 seconds
Started Feb 21 12:33:03 PM PST 24
Finished Feb 21 12:33:18 PM PST 24
Peak memory 260912 kb
Host smart-a4b7b8c5-ec0d-4d70-8100-70057adb0538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246551514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
2246551514
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1787474859
Short name T1156
Test name
Test status
Simulation time 853954700 ps
CPU time 53.43 seconds
Started Feb 21 12:32:43 PM PST 24
Finished Feb 21 12:33:37 PM PST 24
Peak memory 260020 kb
Host smart-85a298c8-6ed8-44fe-940d-a99d06df37c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787474859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.1787474859
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3284683667
Short name T1223
Test name
Test status
Simulation time 2978159300 ps
CPU time 43.53 seconds
Started Feb 21 12:32:48 PM PST 24
Finished Feb 21 12:33:34 PM PST 24
Peak memory 259472 kb
Host smart-aabd7c8a-e434-46ce-b075-0093331d66d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284683667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.3284683667
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3672127163
Short name T1164
Test name
Test status
Simulation time 28500400 ps
CPU time 30.03 seconds
Started Feb 21 12:32:52 PM PST 24
Finished Feb 21 12:33:24 PM PST 24
Peak memory 259784 kb
Host smart-6ccb0fdb-204a-4f34-a2ff-42e691d0511d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672127163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.3672127163
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1289254855
Short name T248
Test name
Test status
Simulation time 108918800 ps
CPU time 16.84 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:15 PM PST 24
Peak memory 269748 kb
Host smart-5f13cad5-de08-4f29-93ad-99ed4ead94a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289254855 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1289254855
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2614972202
Short name T1230
Test name
Test status
Simulation time 33974200 ps
CPU time 16.25 seconds
Started Feb 21 12:32:52 PM PST 24
Finished Feb 21 12:33:10 PM PST 24
Peak memory 259788 kb
Host smart-416302d7-e9a1-4568-8add-dc73be7c2e89
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614972202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.2614972202
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3548872245
Short name T1199
Test name
Test status
Simulation time 14520300 ps
CPU time 13.22 seconds
Started Feb 21 12:32:49 PM PST 24
Finished Feb 21 12:33:04 PM PST 24
Peak memory 260340 kb
Host smart-34e4cb57-1ff3-409d-a091-1c93923dc2b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548872245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.3
548872245
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1662964625
Short name T265
Test name
Test status
Simulation time 102535000 ps
CPU time 13.5 seconds
Started Feb 21 12:33:02 PM PST 24
Finished Feb 21 12:33:18 PM PST 24
Peak memory 260408 kb
Host smart-97c09321-fd3b-47c6-973e-321ff5e1ad0b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662964625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.1662964625
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2848559151
Short name T1150
Test name
Test status
Simulation time 14176700 ps
CPU time 13.44 seconds
Started Feb 21 12:32:41 PM PST 24
Finished Feb 21 12:32:55 PM PST 24
Peak memory 261864 kb
Host smart-15de810d-df2d-409f-bdb2-6658a5100aa6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848559151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.2848559151
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3425189155
Short name T52
Test name
Test status
Simulation time 224183300 ps
CPU time 17.01 seconds
Started Feb 21 12:32:50 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 259848 kb
Host smart-4556822a-61c5-4197-bb5c-23a30deba6ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425189155 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.3425189155
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3435682862
Short name T1248
Test name
Test status
Simulation time 12529000 ps
CPU time 15.54 seconds
Started Feb 21 12:32:52 PM PST 24
Finished Feb 21 12:33:08 PM PST 24
Peak memory 259692 kb
Host smart-ffe4e8be-838f-40fc-9d84-44e6eab7605a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435682862 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.3435682862
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1960208753
Short name T1139
Test name
Test status
Simulation time 23485200 ps
CPU time 15.31 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 259804 kb
Host smart-43647c81-fc86-46cf-ac4f-7826185943c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960208753 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.1960208753
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2678049805
Short name T1262
Test name
Test status
Simulation time 88096100 ps
CPU time 18.45 seconds
Started Feb 21 12:32:49 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 260984 kb
Host smart-10d115f8-73fd-4dff-9e7d-35bcf3ecd097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678049805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2
678049805
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2050634134
Short name T313
Test name
Test status
Simulation time 428763400 ps
CPU time 452.37 seconds
Started Feb 21 12:32:45 PM PST 24
Finished Feb 21 12:40:18 PM PST 24
Peak memory 263508 kb
Host smart-ad9d0e6a-6c09-4700-9926-dc20bbbb8295
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050634134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.2050634134
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2518272344
Short name T1204
Test name
Test status
Simulation time 16891900 ps
CPU time 13.47 seconds
Started Feb 21 12:33:01 PM PST 24
Finished Feb 21 12:33:16 PM PST 24
Peak memory 262120 kb
Host smart-26fcf9fd-bc9a-4838-b2d2-e47f5516bfa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518272344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
2518272344
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2924252942
Short name T242
Test name
Test status
Simulation time 30537600 ps
CPU time 13.47 seconds
Started Feb 21 12:33:05 PM PST 24
Finished Feb 21 12:33:24 PM PST 24
Peak memory 261772 kb
Host smart-8c895b74-31dd-4af7-8011-da523e16ce30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924252942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
2924252942
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3043247102
Short name T1244
Test name
Test status
Simulation time 50296600 ps
CPU time 13.25 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 261952 kb
Host smart-c96d6689-38fb-48cc-9011-9473f35a0a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043247102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
3043247102
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3531412870
Short name T1273
Test name
Test status
Simulation time 16679600 ps
CPU time 13.32 seconds
Started Feb 21 12:32:55 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 260260 kb
Host smart-42edee03-189b-40bc-a8f8-5d86bca88575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531412870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
3531412870
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1163909921
Short name T1154
Test name
Test status
Simulation time 53593600 ps
CPU time 13.59 seconds
Started Feb 21 12:33:04 PM PST 24
Finished Feb 21 12:33:20 PM PST 24
Peak memory 261868 kb
Host smart-3b612534-008b-40ea-9658-2672e6e068a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163909921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
1163909921
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1458578828
Short name T1172
Test name
Test status
Simulation time 18753300 ps
CPU time 13.29 seconds
Started Feb 21 12:33:00 PM PST 24
Finished Feb 21 12:33:15 PM PST 24
Peak memory 262120 kb
Host smart-642f4d4a-a406-4da3-84cf-4275b8ca4179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458578828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
1458578828
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1863215284
Short name T1246
Test name
Test status
Simulation time 60055800 ps
CPU time 13.8 seconds
Started Feb 21 12:33:03 PM PST 24
Finished Feb 21 12:33:18 PM PST 24
Peak memory 260164 kb
Host smart-ce364232-9a29-4316-a797-a9c6980a7dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863215284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
1863215284
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.36662391
Short name T1250
Test name
Test status
Simulation time 30613500 ps
CPU time 13.45 seconds
Started Feb 21 12:32:58 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 262088 kb
Host smart-7f95a5df-ca56-4609-9396-8456d1c5dcec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36662391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.36662391
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3657212777
Short name T1227
Test name
Test status
Simulation time 25781900 ps
CPU time 13.3 seconds
Started Feb 21 12:33:03 PM PST 24
Finished Feb 21 12:33:18 PM PST 24
Peak memory 262108 kb
Host smart-fbb0b654-aa36-4679-80ea-f5eaa71d4b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657212777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
3657212777
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3175841565
Short name T1253
Test name
Test status
Simulation time 83917800 ps
CPU time 13.23 seconds
Started Feb 21 12:33:07 PM PST 24
Finished Feb 21 12:33:21 PM PST 24
Peak memory 261808 kb
Host smart-ed1ad386-367a-4afd-a8b9-869e93416e1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175841565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
3175841565
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.88443227
Short name T259
Test name
Test status
Simulation time 41632100 ps
CPU time 19.6 seconds
Started Feb 21 12:33:05 PM PST 24
Finished Feb 21 12:33:27 PM PST 24
Peak memory 271396 kb
Host smart-329fcd29-8378-4000-bd6c-0aeb32b2c998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88443227 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.88443227
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3628501061
Short name T304
Test name
Test status
Simulation time 187828400 ps
CPU time 16.29 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:14 PM PST 24
Peak memory 259736 kb
Host smart-9dcc456c-9e44-4c03-8cf4-096e5565f791
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628501061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.3628501061
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1078858942
Short name T1177
Test name
Test status
Simulation time 87308700 ps
CPU time 13.33 seconds
Started Feb 21 12:33:02 PM PST 24
Finished Feb 21 12:33:17 PM PST 24
Peak memory 261888 kb
Host smart-74363ae5-db5d-43c3-b7d5-8eaecf752a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078858942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.1
078858942
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1830495412
Short name T1169
Test name
Test status
Simulation time 159641600 ps
CPU time 34.58 seconds
Started Feb 21 12:32:50 PM PST 24
Finished Feb 21 12:33:26 PM PST 24
Peak memory 259756 kb
Host smart-ac3520ff-c04d-405d-a8cb-8e314646e6d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830495412 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1830495412
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2946290630
Short name T1138
Test name
Test status
Simulation time 106310000 ps
CPU time 15.58 seconds
Started Feb 21 12:32:49 PM PST 24
Finished Feb 21 12:33:07 PM PST 24
Peak memory 259680 kb
Host smart-a62c445a-9e46-4655-ad89-80736971c6a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946290630 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.2946290630
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3324541277
Short name T1143
Test name
Test status
Simulation time 11910600 ps
CPU time 15.59 seconds
Started Feb 21 12:32:55 PM PST 24
Finished Feb 21 12:33:12 PM PST 24
Peak memory 259652 kb
Host smart-5d255cb1-dbc2-4ae2-ae18-d2cf35207947
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324541277 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.3324541277
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.863119753
Short name T239
Test name
Test status
Simulation time 330212100 ps
CPU time 18.28 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:33:14 PM PST 24
Peak memory 263428 kb
Host smart-c8f6ba0a-9308-475c-9843-b7b2986fe4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863119753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.863119753
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2062767415
Short name T1161
Test name
Test status
Simulation time 31405000 ps
CPU time 18.04 seconds
Started Feb 21 12:33:09 PM PST 24
Finished Feb 21 12:33:28 PM PST 24
Peak memory 270904 kb
Host smart-b0e2a9ad-5830-4776-b781-80ed272a477d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062767415 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.2062767415
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3722731586
Short name T1222
Test name
Test status
Simulation time 75091300 ps
CPU time 17.46 seconds
Started Feb 21 12:32:59 PM PST 24
Finished Feb 21 12:33:17 PM PST 24
Peak memory 259868 kb
Host smart-7fa18832-de22-455b-b74b-1eb662431fa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722731586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.3722731586
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3659562005
Short name T1221
Test name
Test status
Simulation time 174929400 ps
CPU time 33.55 seconds
Started Feb 21 12:32:49 PM PST 24
Finished Feb 21 12:33:25 PM PST 24
Peak memory 259780 kb
Host smart-c350b3df-bbf6-4666-8006-6b6eafb2ce54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659562005 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.3659562005
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2712752331
Short name T1148
Test name
Test status
Simulation time 20203200 ps
CPU time 15.95 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:14 PM PST 24
Peak memory 259704 kb
Host smart-2f1536e6-5be7-449d-9737-551f9e9b63f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712752331 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.2712752331
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2061690973
Short name T1249
Test name
Test status
Simulation time 11648500 ps
CPU time 15.97 seconds
Started Feb 21 12:32:34 PM PST 24
Finished Feb 21 12:32:52 PM PST 24
Peak memory 259592 kb
Host smart-d449d003-f6b5-497d-9970-9c3cd47b6ee1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061690973 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.2061690973
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1456234917
Short name T250
Test name
Test status
Simulation time 303136100 ps
CPU time 18.36 seconds
Started Feb 21 12:32:48 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 263456 kb
Host smart-3f7020c7-9073-4798-8d2d-5d1c49a8978a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456234917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1
456234917
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1292609725
Short name T362
Test name
Test status
Simulation time 2711672900 ps
CPU time 901.89 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:48:00 PM PST 24
Peak memory 263512 kb
Host smart-1f34b3fb-78dc-423b-81bf-275c01ea80b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292609725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.1292609725
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.289502535
Short name T260
Test name
Test status
Simulation time 841073600 ps
CPU time 19.44 seconds
Started Feb 21 12:32:52 PM PST 24
Finished Feb 21 12:33:12 PM PST 24
Peak memory 271800 kb
Host smart-3bf9a936-04ec-4f0a-98a6-71a2361f0bd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289502535 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.289502535
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2002327992
Short name T280
Test name
Test status
Simulation time 40783800 ps
CPU time 16.48 seconds
Started Feb 21 12:32:55 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 259668 kb
Host smart-c1ea2509-57ff-41f8-9ade-da2539b6bf2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002327992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.2002327992
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.224064936
Short name T357
Test name
Test status
Simulation time 33068400 ps
CPU time 13.66 seconds
Started Feb 21 12:32:51 PM PST 24
Finished Feb 21 12:33:06 PM PST 24
Peak memory 260216 kb
Host smart-767cdb7e-08f8-4366-af69-37ea8be7101e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224064936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.224064936
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2165528097
Short name T1255
Test name
Test status
Simulation time 331543500 ps
CPU time 18.14 seconds
Started Feb 21 12:32:38 PM PST 24
Finished Feb 21 12:32:57 PM PST 24
Peak memory 259912 kb
Host smart-b30c6372-5b96-45f0-a7fa-e6b01f5fc71c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165528097 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.2165528097
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3950569959
Short name T1233
Test name
Test status
Simulation time 151018000 ps
CPU time 13.46 seconds
Started Feb 21 12:33:13 PM PST 24
Finished Feb 21 12:33:27 PM PST 24
Peak memory 259692 kb
Host smart-81bf2e91-93d8-4ec3-ab54-550639d3edba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950569959 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.3950569959
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4274791318
Short name T1240
Test name
Test status
Simulation time 16277800 ps
CPU time 13.07 seconds
Started Feb 21 12:32:49 PM PST 24
Finished Feb 21 12:33:04 PM PST 24
Peak memory 259760 kb
Host smart-58e4aa61-5ba9-47dc-9cca-03738fba32eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274791318 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.4274791318
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.393129450
Short name T238
Test name
Test status
Simulation time 52383700 ps
CPU time 18.31 seconds
Started Feb 21 12:32:46 PM PST 24
Finished Feb 21 12:33:04 PM PST 24
Peak memory 260624 kb
Host smart-ed7f503c-cc6a-433d-b3d9-c56a5074f566
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393129450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.393129450
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1569285550
Short name T1226
Test name
Test status
Simulation time 2079974900 ps
CPU time 384.18 seconds
Started Feb 21 12:32:48 PM PST 24
Finished Feb 21 12:39:15 PM PST 24
Peak memory 263356 kb
Host smart-2964bc8a-947b-42ab-98af-499aa9a4cf0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569285550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.1569285550
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2632458812
Short name T1144
Test name
Test status
Simulation time 91602700 ps
CPU time 20.08 seconds
Started Feb 21 12:32:39 PM PST 24
Finished Feb 21 12:32:59 PM PST 24
Peak memory 271708 kb
Host smart-88461373-f1d0-4891-9853-9c7d46bd2c85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632458812 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2632458812
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.843669125
Short name T1205
Test name
Test status
Simulation time 35134100 ps
CPU time 17.32 seconds
Started Feb 21 12:32:47 PM PST 24
Finished Feb 21 12:33:07 PM PST 24
Peak memory 259800 kb
Host smart-b3db1c75-24e8-4388-9a11-7257cc5ff2ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843669125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_csr_rw.843669125
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.100442180
Short name T348
Test name
Test status
Simulation time 54595900 ps
CPU time 13.29 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 262028 kb
Host smart-b018338d-87bf-4d9d-bd11-0249afb03d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100442180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.100442180
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1881324301
Short name T1266
Test name
Test status
Simulation time 511963800 ps
CPU time 34.75 seconds
Started Feb 21 12:32:54 PM PST 24
Finished Feb 21 12:33:30 PM PST 24
Peak memory 261280 kb
Host smart-80318c10-990b-4819-823f-000a1e607ce4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881324301 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.1881324301
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1369761665
Short name T1243
Test name
Test status
Simulation time 23937900 ps
CPU time 15.55 seconds
Started Feb 21 12:32:53 PM PST 24
Finished Feb 21 12:33:09 PM PST 24
Peak memory 259588 kb
Host smart-aebd84e8-8e91-47d4-a4a5-845b3bd1158c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369761665 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.1369761665
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2621727218
Short name T1151
Test name
Test status
Simulation time 66946800 ps
CPU time 13.72 seconds
Started Feb 21 12:32:45 PM PST 24
Finished Feb 21 12:32:59 PM PST 24
Peak memory 259688 kb
Host smart-115d6143-ac3d-4e59-a2c7-4c23d35a70be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621727218 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.2621727218
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.558782
Short name T244
Test name
Test status
Simulation time 34146100 ps
CPU time 16.19 seconds
Started Feb 21 12:32:55 PM PST 24
Finished Feb 21 12:33:12 PM PST 24
Peak memory 263568 kb
Host smart-5b85cd13-f76c-4301-b7fa-4cfd7cfa2877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.558782
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3172468708
Short name T1217
Test name
Test status
Simulation time 73591800 ps
CPU time 18.97 seconds
Started Feb 21 12:32:50 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 271784 kb
Host smart-9197e089-9b7c-4eff-b6e8-8d1904892c7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172468708 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.3172468708
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3708384187
Short name T1181
Test name
Test status
Simulation time 30788800 ps
CPU time 16.9 seconds
Started Feb 21 12:32:58 PM PST 24
Finished Feb 21 12:33:16 PM PST 24
Peak memory 259732 kb
Host smart-8dfb560d-301d-4597-8b92-770ad07613cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708384187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.3708384187
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.403748785
Short name T1268
Test name
Test status
Simulation time 53119500 ps
CPU time 13.1 seconds
Started Feb 21 12:32:57 PM PST 24
Finished Feb 21 12:33:10 PM PST 24
Peak memory 262076 kb
Host smart-a99e5d9d-262a-4458-a8e0-a5f428ef41ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403748785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.403748785
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.993465202
Short name T1149
Test name
Test status
Simulation time 88331800 ps
CPU time 17.72 seconds
Started Feb 21 12:32:42 PM PST 24
Finished Feb 21 12:33:00 PM PST 24
Peak memory 259900 kb
Host smart-ed3d90c0-567b-4d4c-a0eb-2884e8613da5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993465202 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.993465202
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3066896666
Short name T1229
Test name
Test status
Simulation time 12417400 ps
CPU time 15.39 seconds
Started Feb 21 12:32:38 PM PST 24
Finished Feb 21 12:32:54 PM PST 24
Peak memory 259672 kb
Host smart-1c33a93a-9886-4255-aed0-fe9a6252da2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066896666 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.3066896666
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.664940759
Short name T1153
Test name
Test status
Simulation time 96085800 ps
CPU time 13.06 seconds
Started Feb 21 12:32:53 PM PST 24
Finished Feb 21 12:33:07 PM PST 24
Peak memory 259648 kb
Host smart-8db81af9-a707-4dde-b6ed-f314a4c2fad0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664940759 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.664940759
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3534604724
Short name T256
Test name
Test status
Simulation time 53985200 ps
CPU time 16.09 seconds
Started Feb 21 12:32:43 PM PST 24
Finished Feb 21 12:33:00 PM PST 24
Peak memory 263884 kb
Host smart-72978e61-8dd9-4f64-84e3-d1facb6103d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534604724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.3
534604724
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1151538716
Short name T257
Test name
Test status
Simulation time 566072700 ps
CPU time 380.7 seconds
Started Feb 21 12:32:44 PM PST 24
Finished Feb 21 12:39:05 PM PST 24
Peak memory 259924 kb
Host smart-6f505d6b-37ba-49e2-a635-71a103561925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151538716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.1151538716
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.4259329002
Short name T748
Test name
Test status
Simulation time 64811300 ps
CPU time 13.83 seconds
Started Feb 21 01:02:33 PM PST 24
Finished Feb 21 01:02:47 PM PST 24
Peak memory 264460 kb
Host smart-9712d0a7-b950-473c-82b5-145dbfdf550a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259329002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.4
259329002
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.3928881441
Short name T234
Test name
Test status
Simulation time 22538000 ps
CPU time 13.9 seconds
Started Feb 21 01:02:32 PM PST 24
Finished Feb 21 01:02:47 PM PST 24
Peak memory 264424 kb
Host smart-fed6f4dd-043d-406f-a1f3-58085de15eca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928881441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.3928881441
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.2265763559
Short name T668
Test name
Test status
Simulation time 55132900 ps
CPU time 13.56 seconds
Started Feb 21 01:02:30 PM PST 24
Finished Feb 21 01:02:44 PM PST 24
Peak memory 274192 kb
Host smart-d55f6822-0818-44ac-86f0-e4d10d75a24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265763559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2265763559
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.4064176344
Short name T481
Test name
Test status
Simulation time 151673300 ps
CPU time 102.69 seconds
Started Feb 21 01:02:28 PM PST 24
Finished Feb 21 01:04:11 PM PST 24
Peak memory 270852 kb
Host smart-1bd74f98-da1d-4ef1-872d-75da50d2fac5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064176344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.4064176344
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.2273661154
Short name T1048
Test name
Test status
Simulation time 458728000 ps
CPU time 2961.28 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:51:34 PM PST 24
Peak memory 263476 kb
Host smart-1f1955f9-12d7-4a6f-be22-f4459e1f8254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273661154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.2273661154
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.109344493
Short name T850
Test name
Test status
Simulation time 244608600 ps
CPU time 21.73 seconds
Started Feb 21 01:02:11 PM PST 24
Finished Feb 21 01:02:33 PM PST 24
Peak memory 264432 kb
Host smart-177c9af2-ed50-4a02-8878-d4c5fda38c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109344493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.109344493
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.1677378960
Short name T123
Test name
Test status
Simulation time 237940121600 ps
CPU time 2743 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:47:55 PM PST 24
Peak memory 261560 kb
Host smart-41ae1be6-2864-4f85-b951-ea0edb9e1623
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677378960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.1677378960
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1164246438
Short name T1006
Test name
Test status
Simulation time 301021477100 ps
CPU time 2908.05 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:50:41 PM PST 24
Peak memory 264504 kb
Host smart-fdfb5d40-5697-4f84-8a11-78cca257cd3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164246438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.1164246438
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.773376249
Short name T885
Test name
Test status
Simulation time 62674600 ps
CPU time 110.19 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:04:02 PM PST 24
Peak memory 261444 kb
Host smart-dd6105c9-be4b-4d78-944e-91dd11cfaa14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=773376249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.773376249
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1817742611
Short name T150
Test name
Test status
Simulation time 10012075000 ps
CPU time 302.94 seconds
Started Feb 21 01:02:28 PM PST 24
Finished Feb 21 01:07:32 PM PST 24
Peak memory 306004 kb
Host smart-e6725430-3f8c-4164-b073-4c9a0b55da66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817742611 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.1817742611
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.47172067
Short name T1075
Test name
Test status
Simulation time 45493500 ps
CPU time 13.45 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:02:43 PM PST 24
Peak memory 264424 kb
Host smart-b8a6ed40-5ceb-4596-9885-25cbe45aac4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47172067 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.47172067
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.941865770
Short name T195
Test name
Test status
Simulation time 334117703500 ps
CPU time 1617.72 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:29:10 PM PST 24
Peak memory 262196 kb
Host smart-630a5409-00d1-4914-82a3-98a264e2e257
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941865770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_hw_rma.941865770
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3737440773
Short name T1129
Test name
Test status
Simulation time 70143313400 ps
CPU time 707.48 seconds
Started Feb 21 01:02:10 PM PST 24
Finished Feb 21 01:13:57 PM PST 24
Peak memory 258080 kb
Host smart-3bf64ed8-1570-47e4-862e-e79343448103
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737440773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.3737440773
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.3944388906
Short name T518
Test name
Test status
Simulation time 6538163100 ps
CPU time 108.37 seconds
Started Feb 21 01:02:10 PM PST 24
Finished Feb 21 01:03:59 PM PST 24
Peak memory 261528 kb
Host smart-93bf723a-b194-4aaf-a8ed-d0a37219d8b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944388906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.3944388906
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.3591656357
Short name T279
Test name
Test status
Simulation time 7677169500 ps
CPU time 627.93 seconds
Started Feb 21 01:02:30 PM PST 24
Finished Feb 21 01:12:59 PM PST 24
Peak memory 334808 kb
Host smart-bb21106e-7ff1-4db0-9a8d-9c18f367da8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591656357 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.3591656357
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.1566096586
Short name T877
Test name
Test status
Simulation time 21151491600 ps
CPU time 159.61 seconds
Started Feb 21 01:02:31 PM PST 24
Finished Feb 21 01:05:12 PM PST 24
Peak memory 292712 kb
Host smart-be44daf1-9e29-4fea-9bde-8b415696d7c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566096586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.1566096586
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.89873012
Short name T109
Test name
Test status
Simulation time 8091840200 ps
CPU time 105.37 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:04:15 PM PST 24
Peak memory 264380 kb
Host smart-7d41318d-663f-4da1-9b52-31272f787b53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89873012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U
VM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.flash_ctrl_intr_wr.89873012
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.3026425189
Short name T2
Test name
Test status
Simulation time 84894256600 ps
CPU time 344.48 seconds
Started Feb 21 01:02:30 PM PST 24
Finished Feb 21 01:08:15 PM PST 24
Peak memory 264412 kb
Host smart-00254e71-cb12-421a-90d4-03e4d1a93536
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302
6425189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.3026425189
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1888003427
Short name T462
Test name
Test status
Simulation time 45675800 ps
CPU time 13.72 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:02:43 PM PST 24
Peak memory 264388 kb
Host smart-9176aba8-3ceb-4a7f-bd5b-717da494bee8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888003427 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1888003427
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.3333084624
Short name T682
Test name
Test status
Simulation time 4699899400 ps
CPU time 133.75 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:04:26 PM PST 24
Peak memory 264472 kb
Host smart-0d521170-fb7b-44fa-9f29-7c192f39d693
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333084624 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.3333084624
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.167085761
Short name T925
Test name
Test status
Simulation time 39543800 ps
CPU time 115.5 seconds
Started Feb 21 01:02:17 PM PST 24
Finished Feb 21 01:04:13 PM PST 24
Peak memory 259132 kb
Host smart-6093ee2d-c704-4bd3-9f13-c1aacb41f91b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167085761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp
_reset.167085761
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.2995680487
Short name T868
Test name
Test status
Simulation time 6717135400 ps
CPU time 174.9 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:05:25 PM PST 24
Peak memory 293364 kb
Host smart-324bb37f-9da6-4cf1-b1a4-6cf1ac519381
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995680487 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.2995680487
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.120010259
Short name T64
Test name
Test status
Simulation time 30722600 ps
CPU time 15.17 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:02:46 PM PST 24
Peak memory 263564 kb
Host smart-04f08bbd-71ec-4131-93b0-aa432720547c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=120010259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.120010259
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.2458905190
Short name T20
Test name
Test status
Simulation time 2855119600 ps
CPU time 204.11 seconds
Started Feb 21 01:02:13 PM PST 24
Finished Feb 21 01:05:37 PM PST 24
Peak memory 260956 kb
Host smart-c38ad31c-885a-4d3e-9dfb-b74d7390a12d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2458905190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.2458905190
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.2423498719
Short name T77
Test name
Test status
Simulation time 716180200 ps
CPU time 65.98 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:03:36 PM PST 24
Peak memory 264736 kb
Host smart-2fb3f4be-03a5-4fdd-a98e-1d423f29e6a0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423498719 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.2423498719
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.1815626264
Short name T221
Test name
Test status
Simulation time 15321600 ps
CPU time 13.7 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:02:43 PM PST 24
Peak memory 264676 kb
Host smart-62039f71-4c49-4d5b-b242-4ea51286bb55
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815626264 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.1815626264
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.114962782
Short name T314
Test name
Test status
Simulation time 19528700 ps
CPU time 13.57 seconds
Started Feb 21 01:02:32 PM PST 24
Finished Feb 21 01:02:46 PM PST 24
Peak memory 264436 kb
Host smart-f56d2cbf-8eb2-4e09-8c99-dd12f93d868d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114962782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_rese
t.114962782
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.3318222608
Short name T1068
Test name
Test status
Simulation time 396842800 ps
CPU time 1131.77 seconds
Started Feb 21 01:02:18 PM PST 24
Finished Feb 21 01:21:10 PM PST 24
Peak memory 286800 kb
Host smart-40382aad-89dc-44b1-bdcc-25e1fccaca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318222608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3318222608
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.454977950
Short name T1108
Test name
Test status
Simulation time 3016247500 ps
CPU time 120.35 seconds
Started Feb 21 01:02:16 PM PST 24
Finished Feb 21 01:04:16 PM PST 24
Peak memory 264464 kb
Host smart-2f2f3e49-dbe6-45ca-ba4d-e4de27a8cdb7
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=454977950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.454977950
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.1524051030
Short name T943
Test name
Test status
Simulation time 392914500 ps
CPU time 31.01 seconds
Started Feb 21 01:02:30 PM PST 24
Finished Feb 21 01:03:02 PM PST 24
Peak memory 278408 kb
Host smart-a238aacd-e079-4b38-bb34-989fcdbb28c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524051030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.1524051030
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.240418576
Short name T609
Test name
Test status
Simulation time 123563100 ps
CPU time 45.38 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:03:15 PM PST 24
Peak memory 272804 kb
Host smart-7ce35ac8-9768-4d65-9452-23b7e4e4c6a9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240418576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_rd_ooo.240418576
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.953851894
Short name T1032
Test name
Test status
Simulation time 159213900 ps
CPU time 35.11 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:03:06 PM PST 24
Peak memory 273788 kb
Host smart-4193eb36-0e9c-4b48-bf96-3a78d07f9e62
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953851894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_re_evict.953851894
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.355067641
Short name T503
Test name
Test status
Simulation time 17064300 ps
CPU time 13.69 seconds
Started Feb 21 01:02:14 PM PST 24
Finished Feb 21 01:02:28 PM PST 24
Peak memory 263300 kb
Host smart-53949eb7-2b2b-44ea-9a00-b63b662261d6
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=355067641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.
355067641
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.1839756075
Short name T632
Test name
Test status
Simulation time 35071500 ps
CPU time 22.66 seconds
Started Feb 21 01:02:13 PM PST 24
Finished Feb 21 01:02:36 PM PST 24
Peak memory 264636 kb
Host smart-1c183e98-b573-4e0e-a862-616600665a5c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839756075 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.1839756075
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.3004542320
Short name T894
Test name
Test status
Simulation time 29510200 ps
CPU time 22.82 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:02:36 PM PST 24
Peak memory 264644 kb
Host smart-df4dbba0-e48b-4bbd-a61d-69fa66cb7a43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004542320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.3004542320
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.2478458655
Short name T152
Test name
Test status
Simulation time 40973701800 ps
CPU time 778.33 seconds
Started Feb 21 01:02:31 PM PST 24
Finished Feb 21 01:15:30 PM PST 24
Peak memory 258280 kb
Host smart-db801a4a-a169-4822-b4b3-3300455885dc
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478458655 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2478458655
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.686111072
Short name T272
Test name
Test status
Simulation time 739255800 ps
CPU time 84.24 seconds
Started Feb 21 01:02:09 PM PST 24
Finished Feb 21 01:03:34 PM PST 24
Peak memory 280020 kb
Host smart-aa20a187-6c5a-45db-ab39-0c203c779dd1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686111072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_ro.686111072
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.640475269
Short name T634
Test name
Test status
Simulation time 685202800 ps
CPU time 131.9 seconds
Started Feb 21 01:02:13 PM PST 24
Finished Feb 21 01:04:25 PM PST 24
Peak memory 281172 kb
Host smart-5ee312f5-b986-400a-82bd-5ed0d9d4a44c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
640475269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.640475269
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.3246985041
Short name T492
Test name
Test status
Simulation time 2061011100 ps
CPU time 110.48 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:04:03 PM PST 24
Peak memory 281008 kb
Host smart-1e308191-f8b1-4c35-992b-1a072938d493
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246985041 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.3246985041
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.3267439240
Short name T522
Test name
Test status
Simulation time 12929365100 ps
CPU time 442.43 seconds
Started Feb 21 01:02:13 PM PST 24
Finished Feb 21 01:09:36 PM PST 24
Peak memory 313628 kb
Host smart-e733baf2-4a44-420e-95ef-1b0f8e745706
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267439240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_rw.3267439240
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.2663571825
Short name T437
Test name
Test status
Simulation time 32307500 ps
CPU time 31.1 seconds
Started Feb 21 01:02:33 PM PST 24
Finished Feb 21 01:03:05 PM PST 24
Peak memory 272828 kb
Host smart-2906b556-c9bd-4b3f-9e0c-fc27070170d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663571825 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.2663571825
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.3539885618
Short name T759
Test name
Test status
Simulation time 5705927600 ps
CPU time 544.96 seconds
Started Feb 21 01:02:09 PM PST 24
Finished Feb 21 01:11:14 PM PST 24
Peak memory 311072 kb
Host smart-4f1e6f48-1d4e-4acc-bfcb-437847c1222a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539885618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s
err.3539885618
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.3407496624
Short name T12
Test name
Test status
Simulation time 10529117800 ps
CPU time 4782.12 seconds
Started Feb 21 01:02:33 PM PST 24
Finished Feb 21 02:22:16 PM PST 24
Peak memory 281928 kb
Host smart-cf959680-1083-44a8-bfdc-41a830c87e9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407496624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.3407496624
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.1350095181
Short name T833
Test name
Test status
Simulation time 4319747800 ps
CPU time 57.28 seconds
Started Feb 21 01:02:32 PM PST 24
Finished Feb 21 01:03:30 PM PST 24
Peak memory 262788 kb
Host smart-3f0c0c73-f9d4-432d-8397-20771db49f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350095181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.1350095181
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.2348622682
Short name T1112
Test name
Test status
Simulation time 2282209200 ps
CPU time 58.67 seconds
Started Feb 21 01:02:12 PM PST 24
Finished Feb 21 01:03:11 PM PST 24
Peak memory 264796 kb
Host smart-6144e1af-3f8f-4ac7-ace5-bdafe614135e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348622682 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.2348622682
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.3356114578
Short name T523
Test name
Test status
Simulation time 898259200 ps
CPU time 91.02 seconds
Started Feb 21 01:02:13 PM PST 24
Finished Feb 21 01:03:44 PM PST 24
Peak memory 264620 kb
Host smart-3086ad0e-95ce-444b-a5b1-1f6d90f138b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356114578 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.3356114578
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.2744860372
Short name T135
Test name
Test status
Simulation time 108995100 ps
CPU time 122.31 seconds
Started Feb 21 01:01:57 PM PST 24
Finished Feb 21 01:03:59 PM PST 24
Peak memory 274728 kb
Host smart-bcf22884-55a7-4236-b63e-2bc4d037a50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744860372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2744860372
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.2634694622
Short name T514
Test name
Test status
Simulation time 14628900 ps
CPU time 25.99 seconds
Started Feb 21 01:01:55 PM PST 24
Finished Feb 21 01:02:22 PM PST 24
Peak memory 258212 kb
Host smart-2cbaf740-3806-4728-a799-c2a8e9dd4f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634694622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.2634694622
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.2838768235
Short name T614
Test name
Test status
Simulation time 166796500 ps
CPU time 506.81 seconds
Started Feb 21 01:02:31 PM PST 24
Finished Feb 21 01:10:59 PM PST 24
Peak memory 281096 kb
Host smart-625aed53-c930-435a-80cd-cc546ccf6174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838768235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.2838768235
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.906736085
Short name T966
Test name
Test status
Simulation time 170468300 ps
CPU time 27.16 seconds
Started Feb 21 01:02:09 PM PST 24
Finished Feb 21 01:02:37 PM PST 24
Peak memory 258148 kb
Host smart-562994ea-8550-4b71-b9af-6b1b1463de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906736085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.906736085
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.64035768
Short name T117
Test name
Test status
Simulation time 3923778300 ps
CPU time 138.97 seconds
Started Feb 21 01:02:15 PM PST 24
Finished Feb 21 01:04:35 PM PST 24
Peak memory 264464 kb
Host smart-767d144a-8098-4b45-ab13-748a191c7924
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64035768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.flash_ctrl_wo.64035768
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.3798010284
Short name T743
Test name
Test status
Simulation time 138371700 ps
CPU time 17.5 seconds
Started Feb 21 01:02:10 PM PST 24
Finished Feb 21 01:02:28 PM PST 24
Peak memory 263716 kb
Host smart-f5f764b8-8283-4c0e-98fa-945d83174c16
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3798010284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.3798010284
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.558110347
Short name T126
Test name
Test status
Simulation time 308440200 ps
CPU time 14.65 seconds
Started Feb 21 01:03:08 PM PST 24
Finished Feb 21 01:03:23 PM PST 24
Peak memory 263532 kb
Host smart-f8184729-67e6-4f3f-a717-cec5b9737490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558110347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.558110347
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.1787286900
Short name T451
Test name
Test status
Simulation time 43209800 ps
CPU time 13.44 seconds
Started Feb 21 01:02:52 PM PST 24
Finished Feb 21 01:03:06 PM PST 24
Peak memory 283244 kb
Host smart-c24daa8d-0daf-42e3-aaf4-0c4bed9431f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787286900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.1787286900
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.3655233353
Short name T289
Test name
Test status
Simulation time 329767000 ps
CPU time 102.86 seconds
Started Feb 21 01:02:40 PM PST 24
Finished Feb 21 01:04:23 PM PST 24
Peak memory 270772 kb
Host smart-0130f0eb-dafb-43e3-9f3f-bf011dac4806
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655233353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.3655233353
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.2667872118
Short name T796
Test name
Test status
Simulation time 4340243500 ps
CPU time 420.26 seconds
Started Feb 21 01:02:41 PM PST 24
Finished Feb 21 01:09:42 PM PST 24
Peak memory 262088 kb
Host smart-ba68527a-c819-4a67-a663-e39f38396bd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667872118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.2667872118
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.2287636397
Short name T488
Test name
Test status
Simulation time 112678566700 ps
CPU time 2592.79 seconds
Started Feb 21 01:02:45 PM PST 24
Finished Feb 21 01:45:59 PM PST 24
Peak memory 264368 kb
Host smart-95793fc1-1810-452f-b6dd-59875e45ee5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287636397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.2287636397
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.4157600771
Short name T184
Test name
Test status
Simulation time 740415400 ps
CPU time 1990.06 seconds
Started Feb 21 01:02:41 PM PST 24
Finished Feb 21 01:35:52 PM PST 24
Peak memory 264432 kb
Host smart-632c5c6e-b496-49e3-847e-acc164e3c0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157600771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.4157600771
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.2183443383
Short name T565
Test name
Test status
Simulation time 346774600 ps
CPU time 835.93 seconds
Started Feb 21 01:02:39 PM PST 24
Finished Feb 21 01:16:36 PM PST 24
Peak memory 264484 kb
Host smart-402a9104-caa6-4d5a-906a-1039cb5d9814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183443383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2183443383
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.1415282300
Short name T186
Test name
Test status
Simulation time 292259200 ps
CPU time 37.41 seconds
Started Feb 21 01:02:52 PM PST 24
Finished Feb 21 01:03:30 PM PST 24
Peak memory 271972 kb
Host smart-ed2d9100-d07e-4260-9f9c-4d9075699cc0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415282300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.1415282300
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.3920179953
Short name T99
Test name
Test status
Simulation time 83749321200 ps
CPU time 1647.22 seconds
Started Feb 21 01:02:42 PM PST 24
Finished Feb 21 01:30:09 PM PST 24
Peak memory 262860 kb
Host smart-95329c36-cfa9-4389-bd29-4caf99d3e530
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920179953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.3920179953
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2035496118
Short name T716
Test name
Test status
Simulation time 40129389100 ps
CPU time 768.08 seconds
Started Feb 21 01:02:41 PM PST 24
Finished Feb 21 01:15:29 PM PST 24
Peak memory 261736 kb
Host smart-38115d1c-1d69-492d-942c-c27ee08241c7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035496118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.2035496118
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.3731974090
Short name T424
Test name
Test status
Simulation time 4491321400 ps
CPU time 41.03 seconds
Started Feb 21 01:02:40 PM PST 24
Finished Feb 21 01:03:21 PM PST 24
Peak memory 261512 kb
Host smart-11f01ba1-5f3b-455a-92fc-dba2af0b8ef3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731974090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.3731974090
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.2999464047
Short name T502
Test name
Test status
Simulation time 1308489000 ps
CPU time 153.34 seconds
Started Feb 21 01:02:50 PM PST 24
Finished Feb 21 01:05:24 PM PST 24
Peak memory 293252 kb
Host smart-0ea7096e-065b-45be-bf66-645bb51fff78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999464047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.2999464047
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2312171032
Short name T1111
Test name
Test status
Simulation time 23981557800 ps
CPU time 236.84 seconds
Started Feb 21 01:02:53 PM PST 24
Finished Feb 21 01:06:51 PM PST 24
Peak memory 283728 kb
Host smart-85fc026e-8690-4ccb-b9d3-738e8bb3700f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312171032 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.2312171032
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.1841416292
Short name T757
Test name
Test status
Simulation time 24242788200 ps
CPU time 110.9 seconds
Started Feb 21 01:02:51 PM PST 24
Finished Feb 21 01:04:42 PM PST 24
Peak memory 264472 kb
Host smart-23b63da4-d90e-443f-8c07-f9cb0bb8cd4d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841416292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.1841416292
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1382815164
Short name T1091
Test name
Test status
Simulation time 196216869400 ps
CPU time 537.42 seconds
Started Feb 21 01:02:52 PM PST 24
Finished Feb 21 01:11:50 PM PST 24
Peak memory 264340 kb
Host smart-6296a457-a68b-487c-85ce-4df4235fa3f9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138
2815164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.1382815164
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.2512696657
Short name T859
Test name
Test status
Simulation time 8281250000 ps
CPU time 69.76 seconds
Started Feb 21 01:02:41 PM PST 24
Finished Feb 21 01:03:51 PM PST 24
Peak memory 259756 kb
Host smart-e12a46ab-281a-4882-ad4b-ce49d0505358
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512696657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.2512696657
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.2033135452
Short name T684
Test name
Test status
Simulation time 24870600 ps
CPU time 13.75 seconds
Started Feb 21 01:03:05 PM PST 24
Finished Feb 21 01:03:19 PM PST 24
Peak memory 264460 kb
Host smart-5f70fbf2-a1a5-4f49-b581-4d412dcb6489
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033135452 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.2033135452
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.1717961375
Short name T68
Test name
Test status
Simulation time 2564018300 ps
CPU time 73.36 seconds
Started Feb 21 01:02:45 PM PST 24
Finished Feb 21 01:03:59 PM PST 24
Peak memory 258952 kb
Host smart-5a5501fa-9d2d-4884-8ece-d4bd7adc67b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717961375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1717961375
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.3673166011
Short name T59
Test name
Test status
Simulation time 38463625300 ps
CPU time 226.8 seconds
Started Feb 21 01:02:41 PM PST 24
Finished Feb 21 01:06:28 PM PST 24
Peak memory 272660 kb
Host smart-1ef1eb90-cc58-4ce9-8571-0597d10224b9
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673166011 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.3673166011
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.3647368144
Short name T494
Test name
Test status
Simulation time 38699200 ps
CPU time 134.51 seconds
Started Feb 21 01:02:40 PM PST 24
Finished Feb 21 01:04:55 PM PST 24
Peak memory 259132 kb
Host smart-adc653a5-f1a7-40df-8c2e-b0a53fbc7c58
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647368144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.3647368144
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.1797256963
Short name T27
Test name
Test status
Simulation time 3514663800 ps
CPU time 148.94 seconds
Started Feb 21 01:02:43 PM PST 24
Finished Feb 21 01:05:12 PM PST 24
Peak memory 280984 kb
Host smart-6c81f4ee-bf82-4561-89d0-6abb2aa283c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797256963 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.1797256963
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.1679767360
Short name T851
Test name
Test status
Simulation time 1114879500 ps
CPU time 384.99 seconds
Started Feb 21 01:02:29 PM PST 24
Finished Feb 21 01:08:56 PM PST 24
Peak memory 261672 kb
Host smart-b99e0095-0223-4e24-a31f-7b6c6816a2b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679767360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.1679767360
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3337889265
Short name T220
Test name
Test status
Simulation time 16822700 ps
CPU time 13.75 seconds
Started Feb 21 01:03:02 PM PST 24
Finished Feb 21 01:03:17 PM PST 24
Peak memory 264664 kb
Host smart-fda9522c-d98d-4b70-bab3-1a67db860499
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337889265 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3337889265
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.2019124468
Short name T880
Test name
Test status
Simulation time 30926200 ps
CPU time 13.52 seconds
Started Feb 21 01:02:55 PM PST 24
Finished Feb 21 01:03:10 PM PST 24
Peak memory 264344 kb
Host smart-d2f9a101-c082-43db-9ef7-39d3c5ebe7b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019124468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.2019124468
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.2259782968
Short name T106
Test name
Test status
Simulation time 14373738800 ps
CPU time 610.44 seconds
Started Feb 21 01:02:30 PM PST 24
Finished Feb 21 01:12:41 PM PST 24
Peak memory 281456 kb
Host smart-51eb16d8-0a95-40ae-8adb-98b11e451b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259782968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2259782968
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.4139741027
Short name T1044
Test name
Test status
Simulation time 1472393200 ps
CPU time 112.8 seconds
Started Feb 21 01:02:31 PM PST 24
Finished Feb 21 01:04:25 PM PST 24
Peak memory 263936 kb
Host smart-2d214f41-5c17-4364-bdaf-7c549000af6b
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4139741027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.4139741027
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.3246398741
Short name T471
Test name
Test status
Simulation time 110268000 ps
CPU time 31.85 seconds
Started Feb 21 01:02:53 PM PST 24
Finished Feb 21 01:03:25 PM PST 24
Peak memory 272776 kb
Host smart-fa72fefb-3bbe-4f01-970a-db3b57f26376
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246398741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.3246398741
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.2048129354
Short name T549
Test name
Test status
Simulation time 142225500 ps
CPU time 37.99 seconds
Started Feb 21 01:02:53 PM PST 24
Finished Feb 21 01:03:31 PM PST 24
Peak memory 265624 kb
Host smart-c629151b-7076-44a5-b8a8-16a72c5a42ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048129354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.2048129354
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.1454099053
Short name T575
Test name
Test status
Simulation time 100771500 ps
CPU time 22.7 seconds
Started Feb 21 01:02:41 PM PST 24
Finished Feb 21 01:03:04 PM PST 24
Peak memory 263880 kb
Host smart-5cd42a82-63f4-4b0a-8dea-69ccbe27fb30
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454099053 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.1454099053
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.2176444464
Short name T807
Test name
Test status
Simulation time 95790600 ps
CPU time 22.77 seconds
Started Feb 21 01:02:47 PM PST 24
Finished Feb 21 01:03:11 PM PST 24
Peak memory 264496 kb
Host smart-727e5d98-a46e-4029-afca-51109fc382e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176444464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.2176444464
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.3800389988
Short name T133
Test name
Test status
Simulation time 1645110700 ps
CPU time 103.22 seconds
Started Feb 21 01:02:42 PM PST 24
Finished Feb 21 01:04:25 PM PST 24
Peak memory 280904 kb
Host smart-dc8213ee-2b28-4b32-8214-e1b00c1c3171
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800389988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_ro.3800389988
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.1687220649
Short name T1105
Test name
Test status
Simulation time 620674500 ps
CPU time 136.39 seconds
Started Feb 21 01:02:41 PM PST 24
Finished Feb 21 01:04:58 PM PST 24
Peak memory 280960 kb
Host smart-90f62b09-e50f-444a-b581-9402e202c7cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1687220649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1687220649
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2714950437
Short name T968
Test name
Test status
Simulation time 1387065900 ps
CPU time 131.92 seconds
Started Feb 21 01:02:41 PM PST 24
Finished Feb 21 01:04:53 PM PST 24
Peak memory 293344 kb
Host smart-5b8adf62-fcbd-4c94-bcea-58c9437e8773
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714950437 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2714950437
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.1386189719
Short name T588
Test name
Test status
Simulation time 20161825600 ps
CPU time 566.63 seconds
Started Feb 21 01:02:41 PM PST 24
Finished Feb 21 01:12:08 PM PST 24
Peak memory 313636 kb
Host smart-3e5562d7-e372-449b-b43a-86ab5c37c602
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386189719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw.1386189719
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.2750614982
Short name T213
Test name
Test status
Simulation time 3010955700 ps
CPU time 602.53 seconds
Started Feb 21 01:02:40 PM PST 24
Finished Feb 21 01:12:43 PM PST 24
Peak memory 319284 kb
Host smart-31367fea-6aeb-4a60-9ca9-0b41d9c070e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750614982 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_rw_derr.2750614982
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.3410958401
Short name T486
Test name
Test status
Simulation time 117888100 ps
CPU time 32.98 seconds
Started Feb 21 01:02:53 PM PST 24
Finished Feb 21 01:03:27 PM PST 24
Peak memory 271668 kb
Host smart-3b342264-a454-46d3-8382-7bce4849ba04
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410958401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.3410958401
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.1124482506
Short name T997
Test name
Test status
Simulation time 29729100 ps
CPU time 30.47 seconds
Started Feb 21 01:02:54 PM PST 24
Finished Feb 21 01:03:25 PM PST 24
Peak memory 273828 kb
Host smart-de81a703-a200-442b-8daa-e5cae8b7483f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124482506 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.1124482506
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.2155716655
Short name T87
Test name
Test status
Simulation time 10870929300 ps
CPU time 808.05 seconds
Started Feb 21 01:02:38 PM PST 24
Finished Feb 21 01:16:06 PM PST 24
Peak memory 319252 kb
Host smart-45088514-cdb5-4441-a136-ec065d2ce5d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155716655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.2155716655
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.1981017031
Short name T652
Test name
Test status
Simulation time 1367619000 ps
CPU time 62.38 seconds
Started Feb 21 01:02:53 PM PST 24
Finished Feb 21 01:03:55 PM PST 24
Peak memory 263492 kb
Host smart-afc199af-c8eb-48f1-80f1-763a5c1cad57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981017031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1981017031
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.1356940895
Short name T449
Test name
Test status
Simulation time 2307694700 ps
CPU time 68.57 seconds
Started Feb 21 01:02:40 PM PST 24
Finished Feb 21 01:03:49 PM PST 24
Peak memory 264528 kb
Host smart-fd66cf7d-4aaf-4e79-a265-a4f9d37de655
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356940895 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.1356940895
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.1499922069
Short name T916
Test name
Test status
Simulation time 734205300 ps
CPU time 80.4 seconds
Started Feb 21 01:02:39 PM PST 24
Finished Feb 21 01:04:00 PM PST 24
Peak memory 272808 kb
Host smart-0230152f-0781-4dd5-950f-ec3eb90e6514
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499922069 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.1499922069
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.2385100441
Short name T989
Test name
Test status
Simulation time 76213900 ps
CPU time 98.87 seconds
Started Feb 21 01:02:30 PM PST 24
Finished Feb 21 01:04:09 PM PST 24
Peak memory 275584 kb
Host smart-cdf29266-36d1-4fa0-8dc6-71f31d523d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385100441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.2385100441
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.723024625
Short name T498
Test name
Test status
Simulation time 52030000 ps
CPU time 24 seconds
Started Feb 21 01:02:27 PM PST 24
Finished Feb 21 01:02:51 PM PST 24
Peak memory 258236 kb
Host smart-df419e1d-b732-4fce-b5aa-1b002fcf617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723024625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.723024625
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.2757907801
Short name T17
Test name
Test status
Simulation time 418876000 ps
CPU time 786.8 seconds
Started Feb 21 01:02:51 PM PST 24
Finished Feb 21 01:15:59 PM PST 24
Peak memory 289048 kb
Host smart-7950cef4-de7f-447b-b0f9-8a77acc14ec7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757907801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.2757907801
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.2377824173
Short name T423
Test name
Test status
Simulation time 87088800 ps
CPU time 23.91 seconds
Started Feb 21 01:02:31 PM PST 24
Finished Feb 21 01:02:56 PM PST 24
Peak memory 258044 kb
Host smart-83589dd9-0795-418d-8390-3e3607dec09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377824173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2377824173
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.2334286488
Short name T1031
Test name
Test status
Simulation time 8716487400 ps
CPU time 152.7 seconds
Started Feb 21 01:02:41 PM PST 24
Finished Feb 21 01:05:14 PM PST 24
Peak memory 264384 kb
Host smart-b8fdafae-c133-4ac4-be61-45c24ecea214
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334286488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_wo.2334286488
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.2862099334
Short name T8
Test name
Test status
Simulation time 81363000 ps
CPU time 14.62 seconds
Started Feb 21 01:02:53 PM PST 24
Finished Feb 21 01:03:08 PM PST 24
Peak memory 264396 kb
Host smart-01f38f8e-5cae-4f0d-97c5-0cfbebf5f731
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862099334 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2862099334
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.1264087705
Short name T728
Test name
Test status
Simulation time 21685700 ps
CPU time 13.63 seconds
Started Feb 21 01:06:34 PM PST 24
Finished Feb 21 01:06:48 PM PST 24
Peak memory 264400 kb
Host smart-b416e702-7698-42dc-afd6-942ffce8a67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264087705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
1264087705
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.308619635
Short name T724
Test name
Test status
Simulation time 27252500 ps
CPU time 15.86 seconds
Started Feb 21 01:06:33 PM PST 24
Finished Feb 21 01:06:49 PM PST 24
Peak memory 273812 kb
Host smart-9dff372d-ce34-48d6-a163-4c32567f2402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308619635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.308619635
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.925834290
Short name T665
Test name
Test status
Simulation time 29771800 ps
CPU time 21.89 seconds
Started Feb 21 01:06:33 PM PST 24
Finished Feb 21 01:06:56 PM PST 24
Peak memory 272908 kb
Host smart-172ce7cf-41e0-47f1-9589-55f59bce6ab6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925834290 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.925834290
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2607962049
Short name T730
Test name
Test status
Simulation time 10012266900 ps
CPU time 128.12 seconds
Started Feb 21 01:06:26 PM PST 24
Finished Feb 21 01:08:35 PM PST 24
Peak memory 359952 kb
Host smart-c64deb62-bb0e-47f3-9fbc-235bf489408f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607962049 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2607962049
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.3745196294
Short name T592
Test name
Test status
Simulation time 47772900 ps
CPU time 13.61 seconds
Started Feb 21 01:06:52 PM PST 24
Finished Feb 21 01:07:06 PM PST 24
Peak memory 263808 kb
Host smart-31d39985-d6a2-46ff-ae1d-dcb0379e6507
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745196294 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.3745196294
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.653874945
Short name T1017
Test name
Test status
Simulation time 40125276400 ps
CPU time 681.11 seconds
Started Feb 21 01:06:20 PM PST 24
Finished Feb 21 01:17:42 PM PST 24
Peak memory 262376 kb
Host smart-4735d14f-efda-451f-a339-5b4be782193c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653874945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.flash_ctrl_hw_rma_reset.653874945
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.3259789173
Short name T733
Test name
Test status
Simulation time 4300464100 ps
CPU time 72.51 seconds
Started Feb 21 01:06:20 PM PST 24
Finished Feb 21 01:07:33 PM PST 24
Peak memory 258312 kb
Host smart-224d723f-a20d-4cf3-b312-761649c02920
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259789173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.3259789173
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.662505427
Short name T454
Test name
Test status
Simulation time 3485031100 ps
CPU time 154.17 seconds
Started Feb 21 01:06:18 PM PST 24
Finished Feb 21 01:08:52 PM PST 24
Peak memory 293168 kb
Host smart-e86c72ef-0614-4229-8c6e-d52be6627964
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662505427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flas
h_ctrl_intr_rd.662505427
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3183133141
Short name T519
Test name
Test status
Simulation time 18056520800 ps
CPU time 220.53 seconds
Started Feb 21 01:06:27 PM PST 24
Finished Feb 21 01:10:08 PM PST 24
Peak memory 284044 kb
Host smart-ae4c8ce0-d729-4cd3-a65f-32bf0c387b0e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183133141 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.3183133141
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.2394855989
Short name T1020
Test name
Test status
Simulation time 12599809200 ps
CPU time 71.67 seconds
Started Feb 21 01:06:19 PM PST 24
Finished Feb 21 01:07:31 PM PST 24
Peak memory 259068 kb
Host smart-1cf72662-2020-4a27-900d-97cd4d62f6f5
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394855989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.2
394855989
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.2445772230
Short name T384
Test name
Test status
Simulation time 5433325500 ps
CPU time 161.47 seconds
Started Feb 21 01:06:18 PM PST 24
Finished Feb 21 01:09:00 PM PST 24
Peak memory 260520 kb
Host smart-bbab69ae-57b7-4b70-8c7b-696ac96aaef1
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445772230 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.2445772230
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.3342366158
Short name T1117
Test name
Test status
Simulation time 123426200 ps
CPU time 135.5 seconds
Started Feb 21 01:06:20 PM PST 24
Finished Feb 21 01:08:36 PM PST 24
Peak memory 258852 kb
Host smart-68ef58ae-37be-4131-b4fc-e230a30ed454
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342366158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.3342366158
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.190297014
Short name T441
Test name
Test status
Simulation time 53125600 ps
CPU time 194.73 seconds
Started Feb 21 01:06:20 PM PST 24
Finished Feb 21 01:09:35 PM PST 24
Peak memory 261432 kb
Host smart-b61f3e69-0a5b-4a75-9d03-d4e4c893842b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=190297014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.190297014
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.2943481733
Short name T910
Test name
Test status
Simulation time 18179900 ps
CPU time 13.46 seconds
Started Feb 21 01:06:33 PM PST 24
Finished Feb 21 01:06:46 PM PST 24
Peak memory 264456 kb
Host smart-19375ea0-73ce-4f03-9061-d9a99e065df2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943481733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.2943481733
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.1124889194
Short name T128
Test name
Test status
Simulation time 52153300 ps
CPU time 206.86 seconds
Started Feb 21 01:06:21 PM PST 24
Finished Feb 21 01:09:48 PM PST 24
Peak memory 280776 kb
Host smart-3fa1851b-2b1a-41d4-8b68-55993a55b71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124889194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1124889194
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.2464803677
Short name T832
Test name
Test status
Simulation time 984601000 ps
CPU time 39.24 seconds
Started Feb 21 01:06:41 PM PST 24
Finished Feb 21 01:07:20 PM PST 24
Peak memory 271748 kb
Host smart-08b97360-3a8f-4458-9e38-3d99400c4da6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464803677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.2464803677
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.2353469780
Short name T483
Test name
Test status
Simulation time 752015000 ps
CPU time 99.09 seconds
Started Feb 21 01:06:18 PM PST 24
Finished Feb 21 01:07:57 PM PST 24
Peak memory 281000 kb
Host smart-62072648-48e5-49ee-8a23-5f2f6550f8af
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353469780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_ro.2353469780
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.2685513760
Short name T861
Test name
Test status
Simulation time 11812400000 ps
CPU time 434.22 seconds
Started Feb 21 01:06:13 PM PST 24
Finished Feb 21 01:13:28 PM PST 24
Peak memory 312524 kb
Host smart-3ead5afd-66e3-4988-a031-ebce7452ca99
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685513760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw.2685513760
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.732483050
Short name T440
Test name
Test status
Simulation time 107996200 ps
CPU time 29.24 seconds
Started Feb 21 01:06:36 PM PST 24
Finished Feb 21 01:07:06 PM PST 24
Peak memory 273024 kb
Host smart-4b652563-013c-4477-8e16-558f75e0037c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732483050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_rw_evict.732483050
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.3451288179
Short name T896
Test name
Test status
Simulation time 32891600 ps
CPU time 30.95 seconds
Started Feb 21 01:06:32 PM PST 24
Finished Feb 21 01:07:03 PM PST 24
Peak memory 265620 kb
Host smart-85cb7534-c8fe-434d-bf01-c5e3d877a48b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451288179 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.3451288179
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.427408026
Short name T870
Test name
Test status
Simulation time 23704800 ps
CPU time 49.6 seconds
Started Feb 21 01:06:12 PM PST 24
Finished Feb 21 01:07:02 PM PST 24
Peak memory 269492 kb
Host smart-463ad746-8070-4be1-b29a-c09b13a7c108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427408026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.427408026
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.1544350215
Short name T61
Test name
Test status
Simulation time 3056715500 ps
CPU time 138.42 seconds
Started Feb 21 01:06:18 PM PST 24
Finished Feb 21 01:08:37 PM PST 24
Peak memory 264452 kb
Host smart-cb35d794-12a3-4493-97a4-07416b1eafb4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544350215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.flash_ctrl_wo.1544350215
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.1671857501
Short name T328
Test name
Test status
Simulation time 122758400 ps
CPU time 13.86 seconds
Started Feb 21 01:06:53 PM PST 24
Finished Feb 21 01:07:07 PM PST 24
Peak memory 264188 kb
Host smart-bea00373-cc4b-4152-ad6f-1f7ea02839ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671857501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
1671857501
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.2779305326
Short name T436
Test name
Test status
Simulation time 15827800 ps
CPU time 15.58 seconds
Started Feb 21 01:06:32 PM PST 24
Finished Feb 21 01:06:48 PM PST 24
Peak memory 274784 kb
Host smart-c5e6cb28-30eb-4743-9704-a6d17fa1876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779305326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.2779305326
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.1996614190
Short name T170
Test name
Test status
Simulation time 10893100 ps
CPU time 20.78 seconds
Started Feb 21 01:06:47 PM PST 24
Finished Feb 21 01:07:09 PM PST 24
Peak memory 272868 kb
Host smart-82374df7-06c2-49ac-b43b-27818ecf1037
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996614190 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.1996614190
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.4034266030
Short name T297
Test name
Test status
Simulation time 10031713400 ps
CPU time 95.94 seconds
Started Feb 21 01:06:49 PM PST 24
Finished Feb 21 01:08:26 PM PST 24
Peak memory 274116 kb
Host smart-d7763d82-31ed-4f91-ac91-526de4f8cd30
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034266030 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.4034266030
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.2770677193
Short name T602
Test name
Test status
Simulation time 15445500 ps
CPU time 13.62 seconds
Started Feb 21 01:06:48 PM PST 24
Finished Feb 21 01:07:03 PM PST 24
Peak memory 264392 kb
Host smart-ceeb8ac1-7af1-442e-a5de-f42eafda4880
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770677193 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.2770677193
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.977662136
Short name T174
Test name
Test status
Simulation time 190199574400 ps
CPU time 762.3 seconds
Started Feb 21 01:06:49 PM PST 24
Finished Feb 21 01:19:32 PM PST 24
Peak memory 262972 kb
Host smart-9dfb6b7d-bc05-462c-a317-32d6fde32ec6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977662136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.flash_ctrl_hw_rma_reset.977662136
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.1281848935
Short name T46
Test name
Test status
Simulation time 4701565000 ps
CPU time 54.91 seconds
Started Feb 21 01:06:29 PM PST 24
Finished Feb 21 01:07:24 PM PST 24
Peak memory 258352 kb
Host smart-5d429ddd-f261-465c-9051-d3a809773819
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281848935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.1281848935
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.3480291742
Short name T879
Test name
Test status
Simulation time 1334452200 ps
CPU time 164.44 seconds
Started Feb 21 01:06:28 PM PST 24
Finished Feb 21 01:09:13 PM PST 24
Peak memory 290260 kb
Host smart-20e7aa0f-0c4a-4133-8269-be904fd148c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480291742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.3480291742
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2960099634
Short name T500
Test name
Test status
Simulation time 31651807800 ps
CPU time 195.48 seconds
Started Feb 21 01:06:47 PM PST 24
Finished Feb 21 01:10:04 PM PST 24
Peak memory 290460 kb
Host smart-a64303ba-3c45-4461-af52-2ea1990c7d9d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960099634 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.2960099634
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.3008374353
Short name T1050
Test name
Test status
Simulation time 1009687400 ps
CPU time 75.17 seconds
Started Feb 21 01:06:30 PM PST 24
Finished Feb 21 01:07:46 PM PST 24
Peak memory 259800 kb
Host smart-1074355d-05d2-4296-a39e-60d0f242aab3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008374353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.3
008374353
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.2700997780
Short name T136
Test name
Test status
Simulation time 15546600 ps
CPU time 13.41 seconds
Started Feb 21 01:06:33 PM PST 24
Finished Feb 21 01:06:47 PM PST 24
Peak memory 264448 kb
Host smart-5767c961-574d-41fb-84b0-da75edddaa5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700997780 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.2700997780
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.3507225292
Short name T1002
Test name
Test status
Simulation time 12457909500 ps
CPU time 940.93 seconds
Started Feb 21 01:06:31 PM PST 24
Finished Feb 21 01:22:12 PM PST 24
Peak memory 272848 kb
Host smart-82889e80-76d4-41d9-b8b8-689edda8bf20
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507225292 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.3507225292
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.3412466935
Short name T485
Test name
Test status
Simulation time 79030300 ps
CPU time 135.72 seconds
Started Feb 21 01:06:25 PM PST 24
Finished Feb 21 01:08:42 PM PST 24
Peak memory 259184 kb
Host smart-d5008674-63a7-4c8b-8c7e-860270bbd37c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412466935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.3412466935
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.780260781
Short name T88
Test name
Test status
Simulation time 704999700 ps
CPU time 250.16 seconds
Started Feb 21 01:06:37 PM PST 24
Finished Feb 21 01:10:48 PM PST 24
Peak memory 264508 kb
Host smart-b3cb4b30-bfc2-4b7e-869a-4776f280fbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=780260781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.780260781
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.3439788438
Short name T465
Test name
Test status
Simulation time 82254200 ps
CPU time 13.96 seconds
Started Feb 21 01:06:32 PM PST 24
Finished Feb 21 01:06:46 PM PST 24
Peak memory 264432 kb
Host smart-eeb94f21-7642-4478-9ad2-f74871c535e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439788438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.3439788438
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.2926590538
Short name T751
Test name
Test status
Simulation time 269285900 ps
CPU time 519.19 seconds
Started Feb 21 01:06:40 PM PST 24
Finished Feb 21 01:15:20 PM PST 24
Peak memory 281232 kb
Host smart-c884dac1-37fe-4b21-b8a7-eee21b01d170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926590538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.2926590538
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.3245128187
Short name T531
Test name
Test status
Simulation time 76012900 ps
CPU time 32.72 seconds
Started Feb 21 01:06:40 PM PST 24
Finished Feb 21 01:07:13 PM PST 24
Peak memory 271664 kb
Host smart-6a87d76a-95e8-4f35-ac8e-5d1d9869cd05
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245128187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.3245128187
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.2153013997
Short name T18
Test name
Test status
Simulation time 483042100 ps
CPU time 108.01 seconds
Started Feb 21 01:06:32 PM PST 24
Finished Feb 21 01:08:21 PM PST 24
Peak memory 280960 kb
Host smart-b3953aaf-e700-46a0-bef9-6e13be152ea6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153013997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_ro.2153013997
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.1992109297
Short name T472
Test name
Test status
Simulation time 3468713200 ps
CPU time 490.06 seconds
Started Feb 21 01:06:37 PM PST 24
Finished Feb 21 01:14:48 PM PST 24
Peak memory 311996 kb
Host smart-9edfdfaf-456a-43cd-bdc5-41b85a653bb8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992109297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_rw.1992109297
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.3268606534
Short name T617
Test name
Test status
Simulation time 159229700 ps
CPU time 35.98 seconds
Started Feb 21 01:06:48 PM PST 24
Finished Feb 21 01:07:24 PM PST 24
Peak memory 276640 kb
Host smart-724e1f84-7b71-4b37-aad3-fadfe59de1e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268606534 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.3268606534
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.3449607120
Short name T407
Test name
Test status
Simulation time 14977774900 ps
CPU time 68.01 seconds
Started Feb 21 01:06:32 PM PST 24
Finished Feb 21 01:07:40 PM PST 24
Peak memory 263340 kb
Host smart-7b775e4f-42c0-4c84-858b-d5837970bf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449607120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.3449607120
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.4052056790
Short name T1132
Test name
Test status
Simulation time 199621600 ps
CPU time 73.08 seconds
Started Feb 21 01:06:25 PM PST 24
Finished Feb 21 01:07:39 PM PST 24
Peak memory 273856 kb
Host smart-f4863f52-d846-473d-bcaa-1887351dcc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052056790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.4052056790
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.3508052513
Short name T793
Test name
Test status
Simulation time 10875254100 ps
CPU time 238.44 seconds
Started Feb 21 01:06:34 PM PST 24
Finished Feb 21 01:10:33 PM PST 24
Peak memory 263764 kb
Host smart-4e824ec1-0953-4cf9-94a7-ee1af87634dd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508052513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.flash_ctrl_wo.3508052513
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.1928211206
Short name T508
Test name
Test status
Simulation time 67779900 ps
CPU time 13.57 seconds
Started Feb 21 01:06:51 PM PST 24
Finished Feb 21 01:07:05 PM PST 24
Peak memory 264152 kb
Host smart-b9f125bf-6841-4036-9030-076030c29e78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928211206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
1928211206
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.1732423613
Short name T422
Test name
Test status
Simulation time 15031500 ps
CPU time 15.77 seconds
Started Feb 21 01:06:50 PM PST 24
Finished Feb 21 01:07:08 PM PST 24
Peak memory 273776 kb
Host smart-3980ea67-69f4-4c5d-bf88-3b0115c5c3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732423613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.1732423613
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.1673921468
Short name T739
Test name
Test status
Simulation time 10525700 ps
CPU time 22.51 seconds
Started Feb 21 01:06:48 PM PST 24
Finished Feb 21 01:07:11 PM PST 24
Peak memory 272788 kb
Host smart-8229472b-607b-462f-a2b4-153d88a89642
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673921468 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.1673921468
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.2290087557
Short name T908
Test name
Test status
Simulation time 25993200 ps
CPU time 13.29 seconds
Started Feb 21 01:06:51 PM PST 24
Finished Feb 21 01:07:05 PM PST 24
Peak memory 263540 kb
Host smart-2e6f3f5b-8dc8-4330-9600-3eda3230a6cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290087557 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.2290087557
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.3513234211
Short name T177
Test name
Test status
Simulation time 90142881500 ps
CPU time 830.64 seconds
Started Feb 21 01:06:48 PM PST 24
Finished Feb 21 01:20:39 PM PST 24
Peak memory 262224 kb
Host smart-ff5a6d16-866d-4b45-b7f7-25502e798aaf
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513234211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.3513234211
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.1019597958
Short name T597
Test name
Test status
Simulation time 1090102600 ps
CPU time 103.9 seconds
Started Feb 21 01:06:48 PM PST 24
Finished Feb 21 01:08:32 PM PST 24
Peak memory 258196 kb
Host smart-a4eb871a-b074-443f-9bfb-00219b27e0c2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019597958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.1019597958
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.4069554612
Short name T224
Test name
Test status
Simulation time 4535058100 ps
CPU time 185.09 seconds
Started Feb 21 01:06:54 PM PST 24
Finished Feb 21 01:10:00 PM PST 24
Peak memory 293208 kb
Host smart-cf8e6f2d-fea3-40cd-bba9-dd1eac4202e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069554612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.4069554612
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.4071130253
Short name T1104
Test name
Test status
Simulation time 9163954000 ps
CPU time 218.26 seconds
Started Feb 21 01:06:49 PM PST 24
Finished Feb 21 01:10:28 PM PST 24
Peak memory 291552 kb
Host smart-3a331f72-b55d-417f-a481-1a163ed9ef42
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071130253 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.4071130253
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.2397615553
Short name T840
Test name
Test status
Simulation time 8040849200 ps
CPU time 93.84 seconds
Started Feb 21 01:06:34 PM PST 24
Finished Feb 21 01:08:09 PM PST 24
Peak memory 259688 kb
Host smart-85fbffc5-32bf-4ddd-9e65-3e3f6e386a12
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397615553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.2
397615553
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.260866456
Short name T298
Test name
Test status
Simulation time 20080400 ps
CPU time 13.47 seconds
Started Feb 21 01:06:50 PM PST 24
Finished Feb 21 01:07:05 PM PST 24
Peak memory 264412 kb
Host smart-cbadd177-8847-4c68-9665-a43a7e6ddb13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260866456 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.260866456
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.818111620
Short name T784
Test name
Test status
Simulation time 140338200 ps
CPU time 109.81 seconds
Started Feb 21 01:06:34 PM PST 24
Finished Feb 21 01:08:25 PM PST 24
Peak memory 263060 kb
Host smart-55d4f585-d16e-402a-a386-f8b9a57871d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818111620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ot
p_reset.818111620
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.2494822162
Short name T23
Test name
Test status
Simulation time 698561000 ps
CPU time 241.5 seconds
Started Feb 21 01:06:34 PM PST 24
Finished Feb 21 01:10:36 PM PST 24
Peak memory 260644 kb
Host smart-a2b12352-3a03-48b6-82dd-4fc3b22e53c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2494822162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.2494822162
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3008050569
Short name T1126
Test name
Test status
Simulation time 80037500 ps
CPU time 14.86 seconds
Started Feb 21 01:06:54 PM PST 24
Finished Feb 21 01:07:10 PM PST 24
Peak memory 264256 kb
Host smart-c45fae0a-db2f-4763-8eb1-9fb97969d47d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008050569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.3008050569
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.1835848958
Short name T447
Test name
Test status
Simulation time 640019300 ps
CPU time 490.05 seconds
Started Feb 21 01:06:33 PM PST 24
Finished Feb 21 01:14:43 PM PST 24
Peak memory 281220 kb
Host smart-f46a29d1-2eee-49a4-a758-0971cc9b7dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835848958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.1835848958
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.51775995
Short name T975
Test name
Test status
Simulation time 128596500 ps
CPU time 38.57 seconds
Started Feb 21 01:06:49 PM PST 24
Finished Feb 21 01:07:28 PM PST 24
Peak memory 272780 kb
Host smart-d169a6e8-eae4-4778-a04c-74c170c39def
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51775995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flas
h_ctrl_re_evict.51775995
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.4235429434
Short name T1013
Test name
Test status
Simulation time 493572900 ps
CPU time 104.46 seconds
Started Feb 21 01:06:47 PM PST 24
Finished Feb 21 01:08:33 PM PST 24
Peak memory 280540 kb
Host smart-6d35b4d5-5145-4af3-abc8-e8e48c15b6d7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235429434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_ro.4235429434
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.378568670
Short name T574
Test name
Test status
Simulation time 18428540200 ps
CPU time 509.07 seconds
Started Feb 21 01:06:59 PM PST 24
Finished Feb 21 01:15:29 PM PST 24
Peak memory 312112 kb
Host smart-567936f1-00d8-44d0-bb6d-400a54c04dd3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378568670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ct
rl_rw.378568670
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.3396060522
Short name T337
Test name
Test status
Simulation time 27758600 ps
CPU time 27.56 seconds
Started Feb 21 01:06:47 PM PST 24
Finished Feb 21 01:07:16 PM PST 24
Peak memory 274788 kb
Host smart-eb915fa1-64ce-4c5c-8ff2-3885a50248d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396060522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.3396060522
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2803333934
Short name T553
Test name
Test status
Simulation time 108916400 ps
CPU time 121.66 seconds
Started Feb 21 01:06:53 PM PST 24
Finished Feb 21 01:08:56 PM PST 24
Peak memory 275144 kb
Host smart-d707a6bf-9dd4-4940-9554-c24703b922ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803333934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2803333934
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.2417343905
Short name T546
Test name
Test status
Simulation time 7841490700 ps
CPU time 168.79 seconds
Started Feb 21 01:06:49 PM PST 24
Finished Feb 21 01:09:39 PM PST 24
Peak memory 264444 kb
Host smart-27f3c188-1428-4c69-883d-2bae239405ee
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417343905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.flash_ctrl_wo.2417343905
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.563849574
Short name T973
Test name
Test status
Simulation time 68275200 ps
CPU time 13.84 seconds
Started Feb 21 01:06:57 PM PST 24
Finished Feb 21 01:07:12 PM PST 24
Peak memory 264200 kb
Host smart-0aa09533-287d-43e1-8a36-18e9feda3dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563849574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.563849574
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.2613005582
Short name T927
Test name
Test status
Simulation time 34140500 ps
CPU time 13.4 seconds
Started Feb 21 01:06:57 PM PST 24
Finished Feb 21 01:07:10 PM PST 24
Peak memory 273984 kb
Host smart-fff0f7c7-d711-4d86-8d12-7f1010916cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613005582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.2613005582
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3874367657
Short name T985
Test name
Test status
Simulation time 10034730500 ps
CPU time 57.22 seconds
Started Feb 21 01:06:56 PM PST 24
Finished Feb 21 01:07:54 PM PST 24
Peak memory 288348 kb
Host smart-5a5ebb12-d01d-48d3-ae7f-73432886adbc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874367657 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.3874367657
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.1171622535
Short name T145
Test name
Test status
Simulation time 160186747300 ps
CPU time 866.25 seconds
Started Feb 21 01:06:48 PM PST 24
Finished Feb 21 01:21:15 PM PST 24
Peak memory 262196 kb
Host smart-a2f82393-e6ab-4a6e-8637-2b84940ee8ce
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171622535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.1171622535
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3130817653
Short name T1087
Test name
Test status
Simulation time 3421114500 ps
CPU time 70.82 seconds
Started Feb 21 01:06:49 PM PST 24
Finished Feb 21 01:08:01 PM PST 24
Peak memory 258284 kb
Host smart-4d5a2245-d7fb-4479-a76f-6addb15fe466
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130817653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.3130817653
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.2727532439
Short name T381
Test name
Test status
Simulation time 4952741000 ps
CPU time 162.06 seconds
Started Feb 21 01:06:59 PM PST 24
Finished Feb 21 01:09:42 PM PST 24
Peak memory 292692 kb
Host smart-d648ab1a-5004-452f-baab-56fb5ece87fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727532439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.2727532439
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.1517117253
Short name T16
Test name
Test status
Simulation time 13935937300 ps
CPU time 208.84 seconds
Started Feb 21 01:06:48 PM PST 24
Finished Feb 21 01:10:18 PM PST 24
Peak memory 289084 kb
Host smart-324087a8-2edb-48c0-8a1d-4f4e956b8b20
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517117253 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.1517117253
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.1947667606
Short name T1058
Test name
Test status
Simulation time 46819200 ps
CPU time 13.41 seconds
Started Feb 21 01:07:02 PM PST 24
Finished Feb 21 01:07:16 PM PST 24
Peak memory 264292 kb
Host smart-b631993e-299b-4017-8c92-50f5f50ef6ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947667606 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.1947667606
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.3276829364
Short name T125
Test name
Test status
Simulation time 26652032000 ps
CPU time 428.01 seconds
Started Feb 21 01:06:47 PM PST 24
Finished Feb 21 01:13:57 PM PST 24
Peak memory 272608 kb
Host smart-b651c141-49a3-4ca5-be2b-952c9d0ac5b0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276829364 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.3276829364
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.73961918
Short name T813
Test name
Test status
Simulation time 76435000 ps
CPU time 370.01 seconds
Started Feb 21 01:06:47 PM PST 24
Finished Feb 21 01:12:59 PM PST 24
Peak memory 264540 kb
Host smart-4ae350cb-cec3-454f-97c7-57baffc017fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73961918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.73961918
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.3343176981
Short name T461
Test name
Test status
Simulation time 39261200 ps
CPU time 13.68 seconds
Started Feb 21 01:06:49 PM PST 24
Finished Feb 21 01:07:04 PM PST 24
Peak memory 264428 kb
Host smart-cb1f73ea-0050-4d98-92db-742e0c4faee1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343176981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.3343176981
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.3553223619
Short name T533
Test name
Test status
Simulation time 17300200 ps
CPU time 76.06 seconds
Started Feb 21 01:06:49 PM PST 24
Finished Feb 21 01:08:06 PM PST 24
Peak memory 267544 kb
Host smart-bb086609-0aac-49bc-8095-b0de4f060299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553223619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.3553223619
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.548840538
Short name T562
Test name
Test status
Simulation time 229160700 ps
CPU time 38.4 seconds
Started Feb 21 01:06:54 PM PST 24
Finished Feb 21 01:07:33 PM PST 24
Peak memory 272784 kb
Host smart-7271364c-bc2a-4457-918c-aabd20cd1259
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548840538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_re_evict.548840538
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.3855024483
Short name T762
Test name
Test status
Simulation time 1559489900 ps
CPU time 82.69 seconds
Started Feb 21 01:06:48 PM PST 24
Finished Feb 21 01:08:12 PM PST 24
Peak memory 279916 kb
Host smart-a7773a53-b077-4ece-999d-8270772fa554
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855024483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_ro.3855024483
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.2379019877
Short name T510
Test name
Test status
Simulation time 47400164100 ps
CPU time 513.31 seconds
Started Feb 21 01:06:55 PM PST 24
Finished Feb 21 01:15:28 PM PST 24
Peak memory 313676 kb
Host smart-58da19f3-5287-446e-8493-c947600f13b3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379019877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c
trl_rw.2379019877
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.4123302752
Short name T766
Test name
Test status
Simulation time 58864700 ps
CPU time 34.89 seconds
Started Feb 21 01:06:49 PM PST 24
Finished Feb 21 01:07:25 PM PST 24
Peak memory 276308 kb
Host smart-4cc1e6d7-1662-4e08-9070-225669d088bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123302752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.4123302752
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.95178042
Short name T82
Test name
Test status
Simulation time 43445900 ps
CPU time 30.53 seconds
Started Feb 21 01:06:59 PM PST 24
Finished Feb 21 01:07:30 PM PST 24
Peak memory 271656 kb
Host smart-80d427c4-656a-41d8-a1c8-14c6e6794212
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95178042 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.95178042
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.98356791
Short name T81
Test name
Test status
Simulation time 24301173000 ps
CPU time 78.58 seconds
Started Feb 21 01:07:02 PM PST 24
Finished Feb 21 01:08:23 PM PST 24
Peak memory 258544 kb
Host smart-8e3c6d35-96a1-4664-ac2b-1b6d92c3fa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98356791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.98356791
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.2916241367
Short name T261
Test name
Test status
Simulation time 70165300 ps
CPU time 146.86 seconds
Started Feb 21 01:06:47 PM PST 24
Finished Feb 21 01:09:15 PM PST 24
Peak memory 278540 kb
Host smart-82d3b06d-3429-45d9-a9e1-7863fa7f7826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916241367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2916241367
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.2579224282
Short name T1120
Test name
Test status
Simulation time 13037680200 ps
CPU time 168.57 seconds
Started Feb 21 01:06:54 PM PST 24
Finished Feb 21 01:09:43 PM PST 24
Peak memory 264304 kb
Host smart-c5b88ecf-b485-480f-9cd3-b4cf30f3e543
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579224282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.flash_ctrl_wo.2579224282
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.3339038931
Short name T816
Test name
Test status
Simulation time 38262800 ps
CPU time 14.13 seconds
Started Feb 21 01:07:16 PM PST 24
Finished Feb 21 01:07:31 PM PST 24
Peak memory 264536 kb
Host smart-1baf1a9e-c099-42cb-9018-6fbfb661db04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339038931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
3339038931
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.1858693277
Short name T474
Test name
Test status
Simulation time 15424000 ps
CPU time 13.48 seconds
Started Feb 21 01:07:17 PM PST 24
Finished Feb 21 01:07:32 PM PST 24
Peak memory 274788 kb
Host smart-c5d8409e-9d61-47db-88fd-f4cbe585789f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858693277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.1858693277
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.217405671
Short name T700
Test name
Test status
Simulation time 14393300 ps
CPU time 21.73 seconds
Started Feb 21 01:07:00 PM PST 24
Finished Feb 21 01:07:22 PM PST 24
Peak memory 279368 kb
Host smart-e851cc3d-708f-4cd3-839b-9a92851cc98a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217405671 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.217405671
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1119659605
Short name T183
Test name
Test status
Simulation time 10037263800 ps
CPU time 58.12 seconds
Started Feb 21 01:07:16 PM PST 24
Finished Feb 21 01:08:14 PM PST 24
Peak memory 290508 kb
Host smart-c8e3e710-a182-410e-af3f-6426a3eeb2f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119659605 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1119659605
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.969410286
Short name T535
Test name
Test status
Simulation time 15498800 ps
CPU time 13.67 seconds
Started Feb 21 01:07:12 PM PST 24
Finished Feb 21 01:07:26 PM PST 24
Peak memory 264408 kb
Host smart-7d701b86-4151-4bc2-98c4-bb9a56838bf0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969410286 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.969410286
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.396040507
Short name T149
Test name
Test status
Simulation time 160197838200 ps
CPU time 758.35 seconds
Started Feb 21 01:07:03 PM PST 24
Finished Feb 21 01:19:44 PM PST 24
Peak memory 258136 kb
Host smart-68c7d97e-cd73-4539-a6c3-523c1387233b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396040507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.flash_ctrl_hw_rma_reset.396040507
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.4171375654
Short name T270
Test name
Test status
Simulation time 8273659400 ps
CPU time 160.11 seconds
Started Feb 21 01:06:59 PM PST 24
Finished Feb 21 01:09:40 PM PST 24
Peak memory 261544 kb
Host smart-21810108-6083-4573-9994-eb967aa1d419
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171375654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.4171375654
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.4204225783
Short name T385
Test name
Test status
Simulation time 1178368200 ps
CPU time 162.02 seconds
Started Feb 21 01:07:00 PM PST 24
Finished Feb 21 01:09:44 PM PST 24
Peak memory 292928 kb
Host smart-b4f613d8-b2cb-4786-8a68-c113bbf94095
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204225783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.4204225783
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1540326904
Short name T633
Test name
Test status
Simulation time 32498632700 ps
CPU time 237.03 seconds
Started Feb 21 01:06:54 PM PST 24
Finished Feb 21 01:10:52 PM PST 24
Peak memory 283948 kb
Host smart-fc2e75ae-a069-4bd8-b54f-348cb2a26c5f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540326904 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1540326904
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.18224871
Short name T137
Test name
Test status
Simulation time 3773711600 ps
CPU time 71.38 seconds
Started Feb 21 01:06:58 PM PST 24
Finished Feb 21 01:08:10 PM PST 24
Peak memory 258736 kb
Host smart-d891be02-b171-4fbc-8edb-4f36682d16e9
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18224871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.18224871
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.3138670076
Short name T11
Test name
Test status
Simulation time 15088300 ps
CPU time 13.39 seconds
Started Feb 21 01:07:14 PM PST 24
Finished Feb 21 01:07:27 PM PST 24
Peak memory 264424 kb
Host smart-a03213ed-796c-48c3-bd04-0a5dea665a6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138670076 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.3138670076
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.2256589678
Short name T103
Test name
Test status
Simulation time 40625624300 ps
CPU time 270.74 seconds
Started Feb 21 01:07:00 PM PST 24
Finished Feb 21 01:11:32 PM PST 24
Peak memory 272692 kb
Host smart-e877c58a-82b1-4bbf-b964-dd1d65a48b03
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256589678 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.2256589678
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.414103460
Short name T892
Test name
Test status
Simulation time 61558700 ps
CPU time 133.77 seconds
Started Feb 21 01:06:57 PM PST 24
Finished Feb 21 01:09:11 PM PST 24
Peak memory 259108 kb
Host smart-024030d0-3684-4f5a-ab52-cb60efa4a142
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414103460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ot
p_reset.414103460
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.891655828
Short name T84
Test name
Test status
Simulation time 74268800 ps
CPU time 432.39 seconds
Started Feb 21 01:07:00 PM PST 24
Finished Feb 21 01:14:13 PM PST 24
Peak memory 260648 kb
Host smart-3f568fb5-f673-4887-9b0f-63f856be1ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891655828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.891655828
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.386366450
Short name T578
Test name
Test status
Simulation time 81153000 ps
CPU time 13.62 seconds
Started Feb 21 01:06:57 PM PST 24
Finished Feb 21 01:07:11 PM PST 24
Peak memory 264384 kb
Host smart-b3e3f779-213f-4893-bcfb-6acf9ca6b84b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386366450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_res
et.386366450
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.13018088
Short name T122
Test name
Test status
Simulation time 783187000 ps
CPU time 503.56 seconds
Started Feb 21 01:07:03 PM PST 24
Finished Feb 21 01:15:29 PM PST 24
Peak memory 280028 kb
Host smart-38a69d55-5725-4870-959c-4082ab9064b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13018088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.13018088
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3661189395
Short name T513
Test name
Test status
Simulation time 234537300 ps
CPU time 37.95 seconds
Started Feb 21 01:06:57 PM PST 24
Finished Feb 21 01:07:36 PM PST 24
Peak memory 277340 kb
Host smart-e8bdd331-9cec-4887-8507-1f9bdff12d84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661189395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3661189395
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.3128181268
Short name T1066
Test name
Test status
Simulation time 1065876600 ps
CPU time 99.51 seconds
Started Feb 21 01:07:03 PM PST 24
Finished Feb 21 01:08:45 PM PST 24
Peak memory 280932 kb
Host smart-a7418a12-87d2-427a-9326-69dfe52407e8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128181268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_ro.3128181268
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.730396701
Short name T636
Test name
Test status
Simulation time 9510314400 ps
CPU time 501.38 seconds
Started Feb 21 01:06:57 PM PST 24
Finished Feb 21 01:15:19 PM PST 24
Peak memory 313704 kb
Host smart-ff8c822b-baaa-488a-bcbd-e67fd12c6002
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730396701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ct
rl_rw.730396701
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.3391924873
Short name T439
Test name
Test status
Simulation time 94482100 ps
CPU time 32.98 seconds
Started Feb 21 01:06:56 PM PST 24
Finished Feb 21 01:07:29 PM PST 24
Peak memory 273876 kb
Host smart-cd8a7945-0f9d-4563-8459-964ced5b620a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391924873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.3391924873
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.183817886
Short name T829
Test name
Test status
Simulation time 29237700 ps
CPU time 30.2 seconds
Started Feb 21 01:07:02 PM PST 24
Finished Feb 21 01:07:33 PM PST 24
Peak memory 273844 kb
Host smart-77607d68-fe38-42b6-8656-be81dd14b09c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183817886 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.183817886
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.3044025776
Short name T404
Test name
Test status
Simulation time 3482101000 ps
CPU time 72.15 seconds
Started Feb 21 01:06:59 PM PST 24
Finished Feb 21 01:08:11 PM PST 24
Peak memory 263860 kb
Host smart-7a48e4a8-3ee7-4ac6-992e-7aed13c18940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044025776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3044025776
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.3607385849
Short name T817
Test name
Test status
Simulation time 112605200 ps
CPU time 96.72 seconds
Started Feb 21 01:06:58 PM PST 24
Finished Feb 21 01:08:35 PM PST 24
Peak memory 275284 kb
Host smart-4f76f2a8-7d8b-477f-a4ab-b4ab07f205e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607385849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3607385849
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.2396265904
Short name T660
Test name
Test status
Simulation time 2072050800 ps
CPU time 137.08 seconds
Started Feb 21 01:07:02 PM PST 24
Finished Feb 21 01:09:20 PM PST 24
Peak memory 264300 kb
Host smart-cbe0923c-434e-4a04-bc72-e8d1668026fc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396265904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.flash_ctrl_wo.2396265904
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.2579041183
Short name T524
Test name
Test status
Simulation time 289839200 ps
CPU time 13.34 seconds
Started Feb 21 01:07:25 PM PST 24
Finished Feb 21 01:07:39 PM PST 24
Peak memory 264180 kb
Host smart-c48a0ff0-db38-4c08-b92b-fc7d76c70b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579041183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
2579041183
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.1647311913
Short name T571
Test name
Test status
Simulation time 70642600 ps
CPU time 15.7 seconds
Started Feb 21 01:07:12 PM PST 24
Finished Feb 21 01:07:28 PM PST 24
Peak memory 274780 kb
Host smart-063e8f82-81e6-49d1-ace5-f76c79a8c908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647311913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1647311913
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.1445569435
Short name T225
Test name
Test status
Simulation time 19650000 ps
CPU time 22.21 seconds
Started Feb 21 01:07:16 PM PST 24
Finished Feb 21 01:07:39 PM PST 24
Peak memory 279632 kb
Host smart-3711a0f2-8a2c-452e-8e81-20d119caaaa5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445569435 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.1445569435
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.505348049
Short name T1009
Test name
Test status
Simulation time 10111905000 ps
CPU time 38.57 seconds
Started Feb 21 01:07:29 PM PST 24
Finished Feb 21 01:08:09 PM PST 24
Peak memory 264424 kb
Host smart-398b7eb0-6f59-40be-8e86-2383f146b517
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505348049 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.505348049
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.802361477
Short name T717
Test name
Test status
Simulation time 60129221200 ps
CPU time 722.34 seconds
Started Feb 21 01:07:12 PM PST 24
Finished Feb 21 01:19:15 PM PST 24
Peak memory 258164 kb
Host smart-52edd671-dc52-4e5d-8660-9dad132c4a57
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802361477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.flash_ctrl_hw_rma_reset.802361477
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.2522404245
Short name T318
Test name
Test status
Simulation time 8428043800 ps
CPU time 128.07 seconds
Started Feb 21 01:07:12 PM PST 24
Finished Feb 21 01:09:20 PM PST 24
Peak memory 261552 kb
Host smart-45e73205-b84b-41b9-bc76-514654ca7eaf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522404245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.2522404245
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.2436586796
Short name T780
Test name
Test status
Simulation time 2130432300 ps
CPU time 142.03 seconds
Started Feb 21 01:07:18 PM PST 24
Finished Feb 21 01:09:40 PM PST 24
Peak memory 293144 kb
Host smart-6018e899-2de5-4620-8422-44eb1b566ad9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436586796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.2436586796
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2610351004
Short name T1037
Test name
Test status
Simulation time 11351743200 ps
CPU time 204.46 seconds
Started Feb 21 01:07:15 PM PST 24
Finished Feb 21 01:10:41 PM PST 24
Peak memory 292136 kb
Host smart-f215b212-556c-4150-87b2-50b2a35e2257
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610351004 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.2610351004
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.1003380810
Short name T415
Test name
Test status
Simulation time 3402685000 ps
CPU time 67.96 seconds
Started Feb 21 01:07:13 PM PST 24
Finished Feb 21 01:08:21 PM PST 24
Peak memory 259724 kb
Host smart-c498adbc-0f9a-4a66-8c95-b4f189eb3cdf
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003380810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1
003380810
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.458061618
Short name T1084
Test name
Test status
Simulation time 25690700 ps
CPU time 13.55 seconds
Started Feb 21 01:07:33 PM PST 24
Finished Feb 21 01:07:47 PM PST 24
Peak memory 264464 kb
Host smart-b1a3ab12-7b9c-470e-99e6-ea71ef85d9d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458061618 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.458061618
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.547339882
Short name T753
Test name
Test status
Simulation time 37151403900 ps
CPU time 536.23 seconds
Started Feb 21 01:07:18 PM PST 24
Finished Feb 21 01:16:16 PM PST 24
Peak memory 272944 kb
Host smart-62206abd-aaa8-4484-8d89-0e673bb6f113
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547339882 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_mp_regions.547339882
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.3155522036
Short name T1071
Test name
Test status
Simulation time 109110900 ps
CPU time 133.08 seconds
Started Feb 21 01:07:15 PM PST 24
Finished Feb 21 01:09:29 PM PST 24
Peak memory 260040 kb
Host smart-0160cf3d-5b81-4b34-a294-4cf74a78a565
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155522036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.3155522036
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.1248865020
Short name T1130
Test name
Test status
Simulation time 24634200 ps
CPU time 68.32 seconds
Started Feb 21 01:07:13 PM PST 24
Finished Feb 21 01:08:22 PM PST 24
Peak memory 264308 kb
Host smart-33f7cfb9-df0b-4a34-b2fa-7f3056d458d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248865020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.1248865020
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.2462084340
Short name T595
Test name
Test status
Simulation time 114107500 ps
CPU time 13.83 seconds
Started Feb 21 01:07:15 PM PST 24
Finished Feb 21 01:07:30 PM PST 24
Peak memory 264408 kb
Host smart-b7087d9f-47f0-4327-afde-ee16c1ee326e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462084340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.2462084340
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.638970740
Short name T1057
Test name
Test status
Simulation time 237808300 ps
CPU time 564.13 seconds
Started Feb 21 01:07:11 PM PST 24
Finished Feb 21 01:16:36 PM PST 24
Peak memory 280816 kb
Host smart-174f96ab-4b8b-4e84-9efb-7f4432b17df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638970740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.638970740
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.1383536247
Short name T333
Test name
Test status
Simulation time 125339100 ps
CPU time 36.07 seconds
Started Feb 21 01:07:12 PM PST 24
Finished Feb 21 01:07:49 PM PST 24
Peak memory 277160 kb
Host smart-cc9191f6-8918-49a2-a876-287ad5101ad2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383536247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.1383536247
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.3261181734
Short name T206
Test name
Test status
Simulation time 3557399300 ps
CPU time 87.91 seconds
Started Feb 21 01:07:12 PM PST 24
Finished Feb 21 01:08:41 PM PST 24
Peak memory 281064 kb
Host smart-670b6ce8-2af5-4c58-ad77-7976e9f2495a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261181734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_ro.3261181734
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.1960994604
Short name T86
Test name
Test status
Simulation time 3302915400 ps
CPU time 502.58 seconds
Started Feb 21 01:07:14 PM PST 24
Finished Feb 21 01:15:37 PM PST 24
Peak memory 312852 kb
Host smart-d7c1834e-03c5-4f00-bbab-f0cf09a456a9
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960994604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw.1960994604
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.4200700571
Short name T343
Test name
Test status
Simulation time 58832900 ps
CPU time 31 seconds
Started Feb 21 01:07:14 PM PST 24
Finished Feb 21 01:07:45 PM PST 24
Peak memory 272808 kb
Host smart-ec83bd29-c364-4625-b3d0-c22a288b15b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200700571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.4200700571
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.3086772300
Short name T339
Test name
Test status
Simulation time 43587100 ps
CPU time 27.6 seconds
Started Feb 21 01:07:15 PM PST 24
Finished Feb 21 01:07:44 PM PST 24
Peak memory 275112 kb
Host smart-5e11307f-23f4-40e5-a582-913153ef68e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086772300 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.3086772300
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.1302450833
Short name T646
Test name
Test status
Simulation time 1673406500 ps
CPU time 56.23 seconds
Started Feb 21 01:07:14 PM PST 24
Finished Feb 21 01:08:12 PM PST 24
Peak memory 258820 kb
Host smart-e0605f5b-ff37-4523-beb0-c9f9f7dbae6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302450833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1302450833
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.1162897987
Short name T380
Test name
Test status
Simulation time 95998300 ps
CPU time 199.93 seconds
Started Feb 21 01:07:14 PM PST 24
Finished Feb 21 01:10:35 PM PST 24
Peak memory 276744 kb
Host smart-81520d67-6a70-4722-b8ac-f6005209f443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162897987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1162897987
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.3224935387
Short name T1041
Test name
Test status
Simulation time 1769453000 ps
CPU time 129.74 seconds
Started Feb 21 01:07:13 PM PST 24
Finished Feb 21 01:09:23 PM PST 24
Peak memory 264416 kb
Host smart-7d1c358c-9836-480e-b8e3-5b7458706e98
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224935387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.flash_ctrl_wo.3224935387
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.3407162175
Short name T770
Test name
Test status
Simulation time 311312200 ps
CPU time 13.77 seconds
Started Feb 21 01:07:49 PM PST 24
Finished Feb 21 01:08:03 PM PST 24
Peak memory 264044 kb
Host smart-17ed3315-22d3-461f-9c59-b2cb37b012f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407162175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
3407162175
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.3034944155
Short name T651
Test name
Test status
Simulation time 13991000 ps
CPU time 13.41 seconds
Started Feb 21 01:07:34 PM PST 24
Finished Feb 21 01:07:48 PM PST 24
Peak memory 274004 kb
Host smart-a8fd8a0e-00fc-4182-b2e0-2423e0d1b6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034944155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.3034944155
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.709799440
Short name T701
Test name
Test status
Simulation time 13072500 ps
CPU time 21.77 seconds
Started Feb 21 01:07:49 PM PST 24
Finished Feb 21 01:08:11 PM PST 24
Peak memory 279356 kb
Host smart-29d3700d-7f4b-4ca3-bdc2-d3c085e169a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709799440 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.709799440
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.1580699332
Short name T981
Test name
Test status
Simulation time 10032582600 ps
CPU time 61.36 seconds
Started Feb 21 01:07:33 PM PST 24
Finished Feb 21 01:08:35 PM PST 24
Peak memory 291904 kb
Host smart-47fbef47-5ae0-46fc-b836-e43714b4241e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580699332 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.1580699332
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.3213681552
Short name T1094
Test name
Test status
Simulation time 18105500 ps
CPU time 13.67 seconds
Started Feb 21 01:07:34 PM PST 24
Finished Feb 21 01:07:48 PM PST 24
Peak memory 264380 kb
Host smart-a92d5cb6-7a03-44ff-ac7b-d64985407c50
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213681552 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.3213681552
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.3833283475
Short name T1053
Test name
Test status
Simulation time 540313840800 ps
CPU time 813.75 seconds
Started Feb 21 01:07:24 PM PST 24
Finished Feb 21 01:20:58 PM PST 24
Peak memory 263312 kb
Host smart-d92dd159-e096-4ac7-9246-e3a7b9b8f64d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833283475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.3833283475
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3300146120
Short name T530
Test name
Test status
Simulation time 17647873100 ps
CPU time 114.64 seconds
Started Feb 21 01:07:24 PM PST 24
Finished Feb 21 01:09:19 PM PST 24
Peak memory 261564 kb
Host smart-7e585c00-afaf-445f-810d-0f7afd7404e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300146120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.3300146120
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.3933339933
Short name T789
Test name
Test status
Simulation time 2333069400 ps
CPU time 152.52 seconds
Started Feb 21 01:07:34 PM PST 24
Finished Feb 21 01:10:07 PM PST 24
Peak memory 293268 kb
Host smart-1ca89b2d-9a65-4704-8bec-2bc62f1daef6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933339933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.3933339933
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2381133588
Short name T552
Test name
Test status
Simulation time 9287210000 ps
CPU time 203.38 seconds
Started Feb 21 01:07:34 PM PST 24
Finished Feb 21 01:10:58 PM PST 24
Peak memory 283820 kb
Host smart-c7439620-949b-4e76-b8f2-0e7074a19df0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381133588 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.2381133588
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.1919775728
Short name T607
Test name
Test status
Simulation time 1627840700 ps
CPU time 62.88 seconds
Started Feb 21 01:07:23 PM PST 24
Finished Feb 21 01:08:27 PM PST 24
Peak memory 259520 kb
Host smart-1a349456-0494-485b-9fb0-bfb0e835909e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919775728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.1
919775728
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.437379902
Short name T738
Test name
Test status
Simulation time 9243037300 ps
CPU time 698.68 seconds
Started Feb 21 01:07:23 PM PST 24
Finished Feb 21 01:19:03 PM PST 24
Peak memory 272464 kb
Host smart-dfab430a-3774-4280-b09c-9f9877be062d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437379902 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_mp_regions.437379902
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.247768944
Short name T704
Test name
Test status
Simulation time 197386700 ps
CPU time 113.04 seconds
Started Feb 21 01:07:29 PM PST 24
Finished Feb 21 01:09:23 PM PST 24
Peak memory 259068 kb
Host smart-979ba27b-32af-4619-b71b-15547407043f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247768944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ot
p_reset.247768944
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.2692317025
Short name T342
Test name
Test status
Simulation time 54787100 ps
CPU time 154.37 seconds
Started Feb 21 01:07:25 PM PST 24
Finished Feb 21 01:10:00 PM PST 24
Peak memory 261640 kb
Host smart-d87bd82a-318f-4204-adb1-3eb763da3dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692317025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.2692317025
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.2327444728
Short name T697
Test name
Test status
Simulation time 34820100 ps
CPU time 13.68 seconds
Started Feb 21 01:07:35 PM PST 24
Finished Feb 21 01:07:49 PM PST 24
Peak memory 263616 kb
Host smart-2b5bc44d-2cd3-4317-9e19-0167a37cb2c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327444728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.2327444728
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2148326579
Short name T785
Test name
Test status
Simulation time 5987712100 ps
CPU time 1004.41 seconds
Started Feb 21 01:07:28 PM PST 24
Finished Feb 21 01:24:14 PM PST 24
Peak memory 284248 kb
Host smart-355d8733-413a-41d8-b362-ba3bce60f934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148326579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2148326579
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.3644048810
Short name T1014
Test name
Test status
Simulation time 194445500 ps
CPU time 36.2 seconds
Started Feb 21 01:07:34 PM PST 24
Finished Feb 21 01:08:11 PM PST 24
Peak memory 272808 kb
Host smart-d008a2aa-d2da-4124-bfe5-f9c658550b47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644048810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.3644048810
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.3961988426
Short name T998
Test name
Test status
Simulation time 534613900 ps
CPU time 108.71 seconds
Started Feb 21 01:07:25 PM PST 24
Finished Feb 21 01:09:14 PM PST 24
Peak memory 280164 kb
Host smart-2f5ced69-2f6b-4789-8cff-1800ab640a06
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961988426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_ro.3961988426
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.1207151655
Short name T875
Test name
Test status
Simulation time 5268990800 ps
CPU time 440.3 seconds
Started Feb 21 01:07:28 PM PST 24
Finished Feb 21 01:14:49 PM PST 24
Peak memory 313692 kb
Host smart-adb35acb-92a5-4645-a61d-1857f94d00d4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207151655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c
trl_rw.1207151655
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.3114573425
Short name T670
Test name
Test status
Simulation time 51828600 ps
CPU time 32.84 seconds
Started Feb 21 01:07:34 PM PST 24
Finished Feb 21 01:08:07 PM PST 24
Peak memory 272856 kb
Host smart-e9be261c-344a-40cd-bb4c-7ab9265ffd7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114573425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.3114573425
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2741543024
Short name T1093
Test name
Test status
Simulation time 122078800 ps
CPU time 38.58 seconds
Started Feb 21 01:07:38 PM PST 24
Finished Feb 21 01:08:17 PM PST 24
Peak memory 272788 kb
Host smart-42769343-0103-4f4a-8f2c-890d1fbb2b9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741543024 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.2741543024
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.441671053
Short name T400
Test name
Test status
Simulation time 388766500 ps
CPU time 55.63 seconds
Started Feb 21 01:07:36 PM PST 24
Finished Feb 21 01:08:32 PM PST 24
Peak memory 258796 kb
Host smart-7f9e47a0-eecf-4c8f-a7d3-e241af361814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441671053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.441671053
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.1115617577
Short name T750
Test name
Test status
Simulation time 24558100 ps
CPU time 75.54 seconds
Started Feb 21 01:07:25 PM PST 24
Finished Feb 21 01:08:41 PM PST 24
Peak memory 274960 kb
Host smart-252c65f7-9e95-4d97-a929-15c9f494532f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115617577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1115617577
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.3334640514
Short name T116
Test name
Test status
Simulation time 3114213700 ps
CPU time 174.98 seconds
Started Feb 21 01:07:24 PM PST 24
Finished Feb 21 01:10:19 PM PST 24
Peak memory 264416 kb
Host smart-2bdebfc2-4c75-489c-8d8b-fbe674fb90ea
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334640514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.flash_ctrl_wo.3334640514
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.4227114786
Short name T936
Test name
Test status
Simulation time 46559500 ps
CPU time 13.92 seconds
Started Feb 21 01:07:51 PM PST 24
Finished Feb 21 01:08:05 PM PST 24
Peak memory 263480 kb
Host smart-33cebe10-a934-4853-9ea9-8f11b53cf04d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227114786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
4227114786
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.2847585592
Short name T378
Test name
Test status
Simulation time 22570500 ps
CPU time 13.39 seconds
Started Feb 21 01:07:50 PM PST 24
Finished Feb 21 01:08:04 PM PST 24
Peak memory 273872 kb
Host smart-70250d2f-f667-40b8-8d99-bd2d82a93bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847585592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2847585592
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.751348223
Short name T373
Test name
Test status
Simulation time 123061100 ps
CPU time 21.78 seconds
Started Feb 21 01:07:50 PM PST 24
Finished Feb 21 01:08:12 PM PST 24
Peak memory 279832 kb
Host smart-f7404996-3ee5-4811-9cd8-ab93d9404a81
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751348223 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.751348223
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3983549289
Short name T754
Test name
Test status
Simulation time 10035443300 ps
CPU time 54 seconds
Started Feb 21 01:07:52 PM PST 24
Finished Feb 21 01:08:47 PM PST 24
Peak memory 285304 kb
Host smart-273d03ad-4cd5-45ef-9233-913dbe020c0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983549289 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3983549289
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.783527696
Short name T590
Test name
Test status
Simulation time 23190800 ps
CPU time 13.35 seconds
Started Feb 21 01:07:50 PM PST 24
Finished Feb 21 01:08:04 PM PST 24
Peak memory 263700 kb
Host smart-55fa1e78-e247-44fe-aaf7-106e4c296872
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783527696 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.783527696
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2342950750
Short name T141
Test name
Test status
Simulation time 240243568600 ps
CPU time 862.08 seconds
Started Feb 21 01:07:36 PM PST 24
Finished Feb 21 01:21:58 PM PST 24
Peak memory 258348 kb
Host smart-4cd2a6b6-86af-4c3d-afb0-5bd3f8a35a15
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342950750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.2342950750
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.2637461466
Short name T680
Test name
Test status
Simulation time 8204905100 ps
CPU time 147.47 seconds
Started Feb 21 01:07:33 PM PST 24
Finished Feb 21 01:10:01 PM PST 24
Peak memory 261280 kb
Host smart-b32bb9d5-f919-4619-b5ad-cd76d8ba3223
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637461466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.2637461466
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.1913786510
Short name T874
Test name
Test status
Simulation time 24272979800 ps
CPU time 178.16 seconds
Started Feb 21 01:07:33 PM PST 24
Finished Feb 21 01:10:32 PM PST 24
Peak memory 292920 kb
Host smart-e2a25a22-d263-4b67-a8d4-c08889cf0352
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913786510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.1913786510
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.3969928657
Short name T544
Test name
Test status
Simulation time 36964358400 ps
CPU time 250.61 seconds
Started Feb 21 01:07:49 PM PST 24
Finished Feb 21 01:12:00 PM PST 24
Peak memory 283968 kb
Host smart-c3414d75-466d-49ba-a133-c7d5468c9078
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969928657 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.3969928657
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.1317682720
Short name T695
Test name
Test status
Simulation time 10150834000 ps
CPU time 66.53 seconds
Started Feb 21 01:07:49 PM PST 24
Finished Feb 21 01:08:56 PM PST 24
Peak memory 259540 kb
Host smart-249dace0-5d86-416a-b40d-03f9ede7cc92
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317682720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.1
317682720
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1553393439
Short name T814
Test name
Test status
Simulation time 15850400 ps
CPU time 13.43 seconds
Started Feb 21 01:07:52 PM PST 24
Finished Feb 21 01:08:06 PM PST 24
Peak memory 264448 kb
Host smart-e1090be2-d27e-4d11-a02b-a13274cd979c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553393439 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1553393439
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.1195615373
Short name T897
Test name
Test status
Simulation time 11271558500 ps
CPU time 288.8 seconds
Started Feb 21 01:07:34 PM PST 24
Finished Feb 21 01:12:23 PM PST 24
Peak memory 272460 kb
Host smart-37bbb51a-d2ae-4781-bd34-a54f938df361
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195615373 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.1195615373
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.3510542020
Short name T889
Test name
Test status
Simulation time 38472000 ps
CPU time 130.08 seconds
Started Feb 21 01:07:33 PM PST 24
Finished Feb 21 01:09:44 PM PST 24
Peak memory 262668 kb
Host smart-ee6064c0-a839-4371-aac8-d8a32c5f230f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510542020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.3510542020
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.1255185338
Short name T458
Test name
Test status
Simulation time 54325100 ps
CPU time 236.22 seconds
Started Feb 21 01:07:35 PM PST 24
Finished Feb 21 01:11:32 PM PST 24
Peak memory 261504 kb
Host smart-e9c60210-8084-4c9a-bbc5-b81ac4d4d29b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255185338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1255185338
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.4125750318
Short name T1019
Test name
Test status
Simulation time 275725500 ps
CPU time 13.53 seconds
Started Feb 21 01:07:50 PM PST 24
Finished Feb 21 01:08:04 PM PST 24
Peak memory 264424 kb
Host smart-a55c8c23-b4ea-43c0-a860-376e0b511478
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125750318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.4125750318
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.1650648209
Short name T21
Test name
Test status
Simulation time 1478560500 ps
CPU time 545.79 seconds
Started Feb 21 01:07:36 PM PST 24
Finished Feb 21 01:16:42 PM PST 24
Peak memory 282812 kb
Host smart-06d69294-be60-4b3b-8f2b-b912f6d32f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650648209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.1650648209
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.2110504813
Short name T387
Test name
Test status
Simulation time 306717100 ps
CPU time 33.89 seconds
Started Feb 21 01:07:49 PM PST 24
Finished Feb 21 01:08:24 PM PST 24
Peak memory 272812 kb
Host smart-00095817-f615-4aa9-b44c-fb35778ea49a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110504813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.2110504813
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.4272261764
Short name T641
Test name
Test status
Simulation time 2058007800 ps
CPU time 111.36 seconds
Started Feb 21 01:07:36 PM PST 24
Finished Feb 21 01:09:27 PM PST 24
Peak memory 280836 kb
Host smart-c87fdcb0-52a9-4d29-8bdc-bd8206ebb425
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272261764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_ro.4272261764
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.1429588560
Short name T798
Test name
Test status
Simulation time 3555257700 ps
CPU time 542.62 seconds
Started Feb 21 01:07:36 PM PST 24
Finished Feb 21 01:16:39 PM PST 24
Peak memory 313660 kb
Host smart-b6d51d9a-cce7-424c-88c0-9665147c82d6
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429588560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_rw.1429588560
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.108903918
Short name T767
Test name
Test status
Simulation time 178320100 ps
CPU time 30.98 seconds
Started Feb 21 01:07:51 PM PST 24
Finished Feb 21 01:08:23 PM PST 24
Peak memory 265620 kb
Host smart-f15b0408-4511-4287-b088-6edeeb3353e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108903918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_rw_evict.108903918
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.1987405100
Short name T331
Test name
Test status
Simulation time 84077800 ps
CPU time 28.38 seconds
Started Feb 21 01:07:50 PM PST 24
Finished Feb 21 01:08:18 PM PST 24
Peak memory 272808 kb
Host smart-92da63ef-9467-4b00-8220-1bb2cfe85c85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987405100 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.1987405100
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.1323681492
Short name T872
Test name
Test status
Simulation time 4296609800 ps
CPU time 69.62 seconds
Started Feb 21 01:07:50 PM PST 24
Finished Feb 21 01:09:00 PM PST 24
Peak memory 263436 kb
Host smart-3616e0aa-377c-4025-bb92-8e878eba9d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323681492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1323681492
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.2896376784
Short name T623
Test name
Test status
Simulation time 159569000 ps
CPU time 100.66 seconds
Started Feb 21 01:07:37 PM PST 24
Finished Feb 21 01:09:18 PM PST 24
Peak memory 274320 kb
Host smart-2c222a79-074d-4d49-9fe5-0bf2887dc934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896376784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.2896376784
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.3673218567
Short name T928
Test name
Test status
Simulation time 4212081100 ps
CPU time 171.66 seconds
Started Feb 21 01:07:33 PM PST 24
Finished Feb 21 01:10:25 PM PST 24
Peak memory 264300 kb
Host smart-9f727c0f-5047-4b3a-b2ca-cca394057110
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673218567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.flash_ctrl_wo.3673218567
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.390836370
Short name T1040
Test name
Test status
Simulation time 85698000 ps
CPU time 13.47 seconds
Started Feb 21 01:08:01 PM PST 24
Finished Feb 21 01:08:15 PM PST 24
Peak memory 264416 kb
Host smart-045643f7-386a-4620-9445-3fd810aaf63b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390836370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.390836370
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.631484705
Short name T525
Test name
Test status
Simulation time 60238300 ps
CPU time 15.91 seconds
Started Feb 21 01:07:57 PM PST 24
Finished Feb 21 01:08:14 PM PST 24
Peak memory 274016 kb
Host smart-43c7f652-a44a-4960-9fa2-bd9a964f339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631484705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.631484705
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.2856017124
Short name T1000
Test name
Test status
Simulation time 82265700 ps
CPU time 22.12 seconds
Started Feb 21 01:07:58 PM PST 24
Finished Feb 21 01:08:21 PM PST 24
Peak memory 279428 kb
Host smart-d89624b8-4d62-48b4-82bf-2e828fad1415
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856017124 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.2856017124
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.4090381518
Short name T1039
Test name
Test status
Simulation time 10044202000 ps
CPU time 47.58 seconds
Started Feb 21 01:07:59 PM PST 24
Finished Feb 21 01:08:48 PM PST 24
Peak memory 263912 kb
Host smart-defa2cd0-d32c-4626-8892-3d3f3c303a32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090381518 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.4090381518
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.1455370395
Short name T1081
Test name
Test status
Simulation time 15049000 ps
CPU time 13.36 seconds
Started Feb 21 01:08:00 PM PST 24
Finished Feb 21 01:08:14 PM PST 24
Peak memory 264264 kb
Host smart-c262b56f-c7d1-402d-926e-77a86cdb8417
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455370395 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.1455370395
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.1765869046
Short name T722
Test name
Test status
Simulation time 40130045500 ps
CPU time 786.27 seconds
Started Feb 21 01:07:49 PM PST 24
Finished Feb 21 01:20:56 PM PST 24
Peak memory 258192 kb
Host smart-8551ce5f-7ebb-4287-93f6-24fb8707192a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765869046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.1765869046
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.4216437890
Short name T720
Test name
Test status
Simulation time 5229026800 ps
CPU time 216.34 seconds
Started Feb 21 01:07:50 PM PST 24
Finished Feb 21 01:11:27 PM PST 24
Peak memory 261164 kb
Host smart-3ff0e4bc-7c04-4f4e-b4cb-45557b365dc2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216437890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.4216437890
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.1714590371
Short name T677
Test name
Test status
Simulation time 6066436600 ps
CPU time 176.63 seconds
Started Feb 21 01:07:57 PM PST 24
Finished Feb 21 01:10:55 PM PST 24
Peak memory 293184 kb
Host smart-b50c04a7-d866-4606-ae44-e2efce9a6a1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714590371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.1714590371
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.492923008
Short name T469
Test name
Test status
Simulation time 79871505500 ps
CPU time 258.69 seconds
Started Feb 21 01:08:00 PM PST 24
Finished Feb 21 01:12:20 PM PST 24
Peak memory 292016 kb
Host smart-514bc0c1-1323-48b8-bd6d-507366113800
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492923008 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.492923008
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.19544450
Short name T414
Test name
Test status
Simulation time 2024775900 ps
CPU time 95.09 seconds
Started Feb 21 01:07:49 PM PST 24
Finished Feb 21 01:09:25 PM PST 24
Peak memory 258948 kb
Host smart-085c7a66-f68c-4d47-80d4-3d3de5e9b982
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19544450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.19544450
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2333575533
Short name T643
Test name
Test status
Simulation time 24190600 ps
CPU time 13.56 seconds
Started Feb 21 01:08:01 PM PST 24
Finished Feb 21 01:08:15 PM PST 24
Peak memory 264428 kb
Host smart-9eddc6a4-d3e1-49cd-8523-a8e82b5eafec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333575533 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2333575533
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.2242764966
Short name T121
Test name
Test status
Simulation time 125190222300 ps
CPU time 471.33 seconds
Started Feb 21 01:07:51 PM PST 24
Finished Feb 21 01:15:42 PM PST 24
Peak memory 272992 kb
Host smart-881ec5dd-7882-49ff-ba9a-099c3659e53c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242764966 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.2242764966
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.1055694713
Short name T1067
Test name
Test status
Simulation time 174735200 ps
CPU time 109.51 seconds
Started Feb 21 01:07:51 PM PST 24
Finished Feb 21 01:09:40 PM PST 24
Peak memory 258756 kb
Host smart-7f65084f-c77d-4fda-a021-80e94eebe01c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055694713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.1055694713
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.1996736522
Short name T1015
Test name
Test status
Simulation time 1485708700 ps
CPU time 457.04 seconds
Started Feb 21 01:07:50 PM PST 24
Finished Feb 21 01:15:27 PM PST 24
Peak memory 260760 kb
Host smart-52012589-21db-46d7-bc20-14d1cadf2733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996736522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1996736522
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.3385175346
Short name T1016
Test name
Test status
Simulation time 69098700 ps
CPU time 13.41 seconds
Started Feb 21 01:07:57 PM PST 24
Finished Feb 21 01:08:12 PM PST 24
Peak memory 264420 kb
Host smart-0536654f-f1e8-49cd-9b33-0f15d3a3f1d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385175346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.3385175346
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.473133564
Short name T71
Test name
Test status
Simulation time 9484530600 ps
CPU time 1277.42 seconds
Started Feb 21 01:07:53 PM PST 24
Finished Feb 21 01:29:11 PM PST 24
Peak memory 285044 kb
Host smart-83b46caf-644a-445e-86ab-55c7fb7e8709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473133564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.473133564
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.587162977
Short name T666
Test name
Test status
Simulation time 90957900 ps
CPU time 35.46 seconds
Started Feb 21 01:07:59 PM PST 24
Finished Feb 21 01:08:35 PM PST 24
Peak memory 277264 kb
Host smart-87a12c40-e498-4c56-a302-23c947664034
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587162977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_re_evict.587162977
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.1457711840
Short name T207
Test name
Test status
Simulation time 457236000 ps
CPU time 99.84 seconds
Started Feb 21 01:08:02 PM PST 24
Finished Feb 21 01:09:43 PM PST 24
Peak memory 280528 kb
Host smart-a9216c86-a00c-498f-95f7-6d1b05bcfa34
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457711840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_ro.1457711840
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.1815416074
Short name T548
Test name
Test status
Simulation time 3946778300 ps
CPU time 468.45 seconds
Started Feb 21 01:07:58 PM PST 24
Finished Feb 21 01:15:48 PM PST 24
Peak memory 313736 kb
Host smart-1e4db683-e0c7-417c-9717-4ce54489608f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815416074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw.1815416074
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.3755295555
Short name T993
Test name
Test status
Simulation time 85924600 ps
CPU time 31.39 seconds
Started Feb 21 01:07:57 PM PST 24
Finished Feb 21 01:08:30 PM PST 24
Peak memory 274864 kb
Host smart-d3615bb5-3c8d-4ff3-bd80-859f0d69e4d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755295555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.3755295555
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.3966146469
Short name T581
Test name
Test status
Simulation time 2447885000 ps
CPU time 74.99 seconds
Started Feb 21 01:08:01 PM PST 24
Finished Feb 21 01:09:16 PM PST 24
Peak memory 264556 kb
Host smart-e4349d01-f53c-4b9a-8471-93ef79980fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966146469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3966146469
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.1962981381
Short name T990
Test name
Test status
Simulation time 74887000 ps
CPU time 122.8 seconds
Started Feb 21 01:07:50 PM PST 24
Finished Feb 21 01:09:54 PM PST 24
Peak memory 275816 kb
Host smart-dde05da6-0278-4efe-b67e-9a82a6ee345d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962981381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1962981381
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.3825038910
Short name T1060
Test name
Test status
Simulation time 9890369100 ps
CPU time 223.08 seconds
Started Feb 21 01:07:58 PM PST 24
Finished Feb 21 01:11:42 PM PST 24
Peak memory 264340 kb
Host smart-5e8c25fa-bcc8-4f8c-9727-95a5c2c67880
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825038910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.flash_ctrl_wo.3825038910
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.453684958
Short name T949
Test name
Test status
Simulation time 39232100 ps
CPU time 13.75 seconds
Started Feb 21 01:08:18 PM PST 24
Finished Feb 21 01:08:32 PM PST 24
Peak memory 263868 kb
Host smart-4287e776-1cf3-4e14-aabe-ebb2a5735447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453684958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.453684958
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.3315598439
Short name T1116
Test name
Test status
Simulation time 26082300 ps
CPU time 13.34 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:08:29 PM PST 24
Peak memory 275016 kb
Host smart-70f141e5-0130-4c01-819e-4ca749bef1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315598439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.3315598439
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1915917767
Short name T964
Test name
Test status
Simulation time 10019609800 ps
CPU time 91.17 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:09:48 PM PST 24
Peak memory 320980 kb
Host smart-2b1d8e21-8166-4042-813f-41acffe5b14e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915917767 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1915917767
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.3365772878
Short name T731
Test name
Test status
Simulation time 17172800 ps
CPU time 13.4 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:08:30 PM PST 24
Peak memory 263788 kb
Host smart-d97039a7-f055-41c9-95d8-53a37787abfe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365772878 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.3365772878
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.2860361652
Short name T504
Test name
Test status
Simulation time 4400502900 ps
CPU time 187.13 seconds
Started Feb 21 01:07:58 PM PST 24
Finished Feb 21 01:11:07 PM PST 24
Peak memory 261512 kb
Host smart-184869af-9ff9-4257-ad0f-ec5dff322b53
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860361652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.2860361652
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.836396335
Short name T839
Test name
Test status
Simulation time 2266342000 ps
CPU time 149.43 seconds
Started Feb 21 01:07:57 PM PST 24
Finished Feb 21 01:10:28 PM PST 24
Peak memory 292244 kb
Host smart-c00df7a4-8e59-4679-9aab-e945dfb4134d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836396335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas
h_ctrl_intr_rd.836396335
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.498190391
Short name T844
Test name
Test status
Simulation time 9199994300 ps
CPU time 250.2 seconds
Started Feb 21 01:08:18 PM PST 24
Finished Feb 21 01:12:28 PM PST 24
Peak memory 289104 kb
Host smart-e7389e59-0f4c-42c3-bdf1-e331a9c31f3c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498190391 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.498190391
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2806219068
Short name T484
Test name
Test status
Simulation time 4251846300 ps
CPU time 63.97 seconds
Started Feb 21 01:07:59 PM PST 24
Finished Feb 21 01:09:03 PM PST 24
Peak memory 258936 kb
Host smart-a9582468-117d-4974-8acc-6d470aea3b91
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806219068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
806219068
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.2311352134
Short name T557
Test name
Test status
Simulation time 22736600 ps
CPU time 13.44 seconds
Started Feb 21 01:08:15 PM PST 24
Finished Feb 21 01:08:29 PM PST 24
Peak memory 264424 kb
Host smart-511a74f0-a0b8-41b1-81eb-7b81d0cb56a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311352134 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.2311352134
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.2011830971
Short name T992
Test name
Test status
Simulation time 2052974800 ps
CPU time 185.33 seconds
Started Feb 21 01:08:01 PM PST 24
Finished Feb 21 01:11:07 PM PST 24
Peak memory 264412 kb
Host smart-9ece0cb1-b179-4961-9c71-3d1969dc1174
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011830971 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.2011830971
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.2935642443
Short name T94
Test name
Test status
Simulation time 73919700 ps
CPU time 133.95 seconds
Started Feb 21 01:07:58 PM PST 24
Finished Feb 21 01:10:13 PM PST 24
Peak memory 259028 kb
Host smart-3e4226ab-4121-4df0-8582-32db921fc687
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935642443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.2935642443
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.2765956025
Short name T895
Test name
Test status
Simulation time 109920500 ps
CPU time 150.78 seconds
Started Feb 21 01:07:58 PM PST 24
Finished Feb 21 01:10:30 PM PST 24
Peak memory 260512 kb
Host smart-73a4f83f-2bd2-4707-b8e1-f3a3a4057034
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765956025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.2765956025
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.1510776896
Short name T1024
Test name
Test status
Simulation time 102977100 ps
CPU time 13.87 seconds
Started Feb 21 01:08:15 PM PST 24
Finished Feb 21 01:08:29 PM PST 24
Peak memory 264460 kb
Host smart-8c3edd9d-9113-4f52-b36c-04a4eaddf4b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510776896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.1510776896
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.1612663411
Short name T783
Test name
Test status
Simulation time 48644600 ps
CPU time 79.31 seconds
Started Feb 21 01:07:59 PM PST 24
Finished Feb 21 01:09:19 PM PST 24
Peak memory 267780 kb
Host smart-a83519fb-48f0-4c7e-b500-70f81826351f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612663411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1612663411
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.2568446403
Short name T334
Test name
Test status
Simulation time 289672700 ps
CPU time 38.29 seconds
Started Feb 21 01:08:15 PM PST 24
Finished Feb 21 01:08:53 PM PST 24
Peak memory 265692 kb
Host smart-f111130f-b91b-419b-8917-a0aa277d57cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568446403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.2568446403
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.2722740062
Short name T209
Test name
Test status
Simulation time 4267971800 ps
CPU time 99.85 seconds
Started Feb 21 01:07:58 PM PST 24
Finished Feb 21 01:09:39 PM PST 24
Peak memory 281040 kb
Host smart-235b661a-8175-4bae-9db7-aa70a33f837b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722740062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_ro.2722740062
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.1765440441
Short name T864
Test name
Test status
Simulation time 4731971600 ps
CPU time 494.96 seconds
Started Feb 21 01:08:00 PM PST 24
Finished Feb 21 01:16:16 PM PST 24
Peak memory 308644 kb
Host smart-5c44fec4-90dd-4b47-aac3-29e8f200d445
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765440441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_rw.1765440441
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.2468201631
Short name T563
Test name
Test status
Simulation time 34454400 ps
CPU time 30.81 seconds
Started Feb 21 01:08:17 PM PST 24
Finished Feb 21 01:08:48 PM PST 24
Peak memory 275096 kb
Host smart-12d3eea8-22db-46c3-b78b-0ffd4962501a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468201631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.2468201631
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.3157368337
Short name T1056
Test name
Test status
Simulation time 39241700 ps
CPU time 30.23 seconds
Started Feb 21 01:08:15 PM PST 24
Finished Feb 21 01:08:46 PM PST 24
Peak memory 274852 kb
Host smart-73e6a142-5137-40a6-b94c-abb18f1b200c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157368337 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.3157368337
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.1330763079
Short name T540
Test name
Test status
Simulation time 10730525000 ps
CPU time 89.07 seconds
Started Feb 21 01:08:15 PM PST 24
Finished Feb 21 01:09:44 PM PST 24
Peak memory 263624 kb
Host smart-b3ce1b59-1257-4633-85aa-1a69ab56df89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330763079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1330763079
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.3032051900
Short name T386
Test name
Test status
Simulation time 19154300 ps
CPU time 146.04 seconds
Started Feb 21 01:07:59 PM PST 24
Finished Feb 21 01:10:26 PM PST 24
Peak memory 276340 kb
Host smart-1e4e3290-846b-4990-9c7c-04c8e9eac04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032051900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.3032051900
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.689360278
Short name T729
Test name
Test status
Simulation time 955420400 ps
CPU time 50.46 seconds
Started Feb 21 01:08:02 PM PST 24
Finished Feb 21 01:08:53 PM PST 24
Peak memory 264308 kb
Host smart-d0fdecb7-6ac4-4d63-a723-d71270edddd7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689360278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_wo.689360278
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.3319834436
Short name T29
Test name
Test status
Simulation time 50391200 ps
CPU time 13.47 seconds
Started Feb 21 01:03:39 PM PST 24
Finished Feb 21 01:03:53 PM PST 24
Peak memory 263380 kb
Host smart-bfff3b04-2234-488a-b4ac-7d9aba71c9eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319834436 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.3319834436
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.4004912745
Short name T463
Test name
Test status
Simulation time 44823400 ps
CPU time 13.78 seconds
Started Feb 21 01:03:36 PM PST 24
Finished Feb 21 01:03:51 PM PST 24
Peak memory 263632 kb
Host smart-68c6c80c-b673-4739-b59d-0e82e74873d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004912745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.4
004912745
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.672831996
Short name T765
Test name
Test status
Simulation time 41156400 ps
CPU time 13.86 seconds
Started Feb 21 01:03:37 PM PST 24
Finished Feb 21 01:03:52 PM PST 24
Peak memory 264404 kb
Host smart-0b157157-7cb9-40d6-ae4b-68e7ad500d83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672831996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
flash_ctrl_config_regwen.672831996
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.247483447
Short name T579
Test name
Test status
Simulation time 16415400 ps
CPU time 13.29 seconds
Started Feb 21 01:03:35 PM PST 24
Finished Feb 21 01:03:48 PM PST 24
Peak memory 274304 kb
Host smart-db61888c-b0a5-4175-a740-8007aa0bef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247483447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.247483447
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.3020699195
Short name T902
Test name
Test status
Simulation time 194383100 ps
CPU time 104.12 seconds
Started Feb 21 01:03:24 PM PST 24
Finished Feb 21 01:05:08 PM PST 24
Peak memory 272904 kb
Host smart-3f7eebbe-8b3a-4287-a254-ad6219630e8b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020699195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.3020699195
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.295819136
Short name T456
Test name
Test status
Simulation time 31736800 ps
CPU time 20.66 seconds
Started Feb 21 01:03:21 PM PST 24
Finished Feb 21 01:03:42 PM PST 24
Peak memory 264708 kb
Host smart-820fc374-4b4b-48cf-be44-f31bba5b9f68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295819136 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.295819136
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.2398437354
Short name T51
Test name
Test status
Simulation time 122807100 ps
CPU time 236.56 seconds
Started Feb 21 01:03:08 PM PST 24
Finished Feb 21 01:07:05 PM PST 24
Peak memory 260344 kb
Host smart-4fba1245-f153-4cce-9371-f51bc4576a58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398437354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.2398437354
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.3065842301
Short name T129
Test name
Test status
Simulation time 9385202100 ps
CPU time 2194.92 seconds
Started Feb 21 01:03:23 PM PST 24
Finished Feb 21 01:39:59 PM PST 24
Peak memory 263148 kb
Host smart-04e2fd7f-8bfb-4ffc-ad7e-8554d02fac43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065842301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.3065842301
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.720820224
Short name T112
Test name
Test status
Simulation time 3275606000 ps
CPU time 834.63 seconds
Started Feb 21 01:03:18 PM PST 24
Finished Feb 21 01:17:14 PM PST 24
Peak memory 264480 kb
Host smart-aed99229-3256-4a7c-9518-0b385e791353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720820224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.720820224
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.3234126395
Short name T360
Test name
Test status
Simulation time 202309100 ps
CPU time 19.78 seconds
Started Feb 21 01:03:05 PM PST 24
Finished Feb 21 01:03:25 PM PST 24
Peak memory 264444 kb
Host smart-1fc1215e-2391-4e8b-9600-8f88ce27e95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234126395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.3234126395
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.875114231
Short name T187
Test name
Test status
Simulation time 1359876300 ps
CPU time 34.75 seconds
Started Feb 21 01:03:36 PM PST 24
Finished Feb 21 01:04:12 PM PST 24
Peak memory 272780 kb
Host smart-dcc9af64-e8f6-4e65-a827-4302fde6b963
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875114231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_fs_sup.875114231
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.783708979
Short name T107
Test name
Test status
Simulation time 125629845200 ps
CPU time 2650.75 seconds
Started Feb 21 01:03:03 PM PST 24
Finished Feb 21 01:47:15 PM PST 24
Peak memory 262356 kb
Host smart-20978be5-6819-459d-8808-83f33ab1d379
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783708979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_full_mem_access.783708979
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.4288723735
Short name T288
Test name
Test status
Simulation time 481115200 ps
CPU time 124.84 seconds
Started Feb 21 01:03:03 PM PST 24
Finished Feb 21 01:05:09 PM PST 24
Peak memory 264524 kb
Host smart-fe348629-987f-46ee-884e-714aaa07100a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4288723735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.4288723735
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.645985449
Short name T295
Test name
Test status
Simulation time 10034888900 ps
CPU time 57.13 seconds
Started Feb 21 01:03:52 PM PST 24
Finished Feb 21 01:04:49 PM PST 24
Peak memory 292008 kb
Host smart-83acad77-6185-4fc5-aad3-f11be80fa534
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645985449 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.645985449
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.3093255031
Short name T66
Test name
Test status
Simulation time 110034800 ps
CPU time 13.34 seconds
Started Feb 21 01:03:48 PM PST 24
Finished Feb 21 01:04:02 PM PST 24
Peak memory 264400 kb
Host smart-4f5b8386-56a2-4c73-aa16-ed54424c44fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093255031 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.3093255031
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.3269035945
Short name T752
Test name
Test status
Simulation time 134496875800 ps
CPU time 1859.88 seconds
Started Feb 21 01:03:04 PM PST 24
Finished Feb 21 01:34:05 PM PST 24
Peak memory 262884 kb
Host smart-c051e94a-0a20-4267-814c-406eab5afd44
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269035945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.3269035945
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.1472244534
Short name T1123
Test name
Test status
Simulation time 130160931400 ps
CPU time 836.97 seconds
Started Feb 21 01:03:04 PM PST 24
Finished Feb 21 01:17:01 PM PST 24
Peak memory 258196 kb
Host smart-c4a85e44-f2b0-44c6-b04b-123aed7521d6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472244534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.1472244534
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.4150651114
Short name T778
Test name
Test status
Simulation time 6543287000 ps
CPU time 137.64 seconds
Started Feb 21 01:03:05 PM PST 24
Finished Feb 21 01:05:23 PM PST 24
Peak memory 261468 kb
Host smart-a18f5e80-8882-4868-9db3-36b4f9079eed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150651114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.4150651114
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.2482785675
Short name T266
Test name
Test status
Simulation time 6553233100 ps
CPU time 504.3 seconds
Started Feb 21 01:03:21 PM PST 24
Finished Feb 21 01:11:46 PM PST 24
Peak memory 319652 kb
Host smart-bc73ea95-d91c-476b-93a5-f5b7cf70c11d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482785675 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.2482785675
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.388037394
Short name T823
Test name
Test status
Simulation time 33150586600 ps
CPU time 213.72 seconds
Started Feb 21 01:03:22 PM PST 24
Finished Feb 21 01:06:56 PM PST 24
Peak memory 289100 kb
Host smart-ad189968-4d17-4fe8-97ac-7673e8dad53a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388037394 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.388037394
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.1391251222
Short name T860
Test name
Test status
Simulation time 4347854900 ps
CPU time 109 seconds
Started Feb 21 01:03:20 PM PST 24
Finished Feb 21 01:05:10 PM PST 24
Peak memory 264392 kb
Host smart-579df79c-03a6-451a-a41e-8b768e926366
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391251222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.1391251222
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.3135204374
Short name T591
Test name
Test status
Simulation time 78131706500 ps
CPU time 350.3 seconds
Started Feb 21 01:03:22 PM PST 24
Finished Feb 21 01:09:12 PM PST 24
Peak memory 264384 kb
Host smart-e846e9a6-9665-48eb-9bd5-f3789cad7792
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313
5204374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.3135204374
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.2769695027
Short name T413
Test name
Test status
Simulation time 13603176700 ps
CPU time 78.98 seconds
Started Feb 21 01:03:18 PM PST 24
Finished Feb 21 01:04:37 PM PST 24
Peak memory 259556 kb
Host smart-4c7b71f7-15a1-48bb-af55-d866a70bd8e9
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769695027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2769695027
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.899082015
Short name T675
Test name
Test status
Simulation time 15423600 ps
CPU time 14.18 seconds
Started Feb 21 01:03:48 PM PST 24
Finished Feb 21 01:04:03 PM PST 24
Peak memory 264468 kb
Host smart-c0e3f10c-a2d9-4e3c-a13f-36434fce253f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899082015 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.899082015
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.700439770
Short name T50
Test name
Test status
Simulation time 3218129300 ps
CPU time 74.66 seconds
Started Feb 21 01:03:21 PM PST 24
Finished Feb 21 01:04:36 PM PST 24
Peak memory 259800 kb
Host smart-53e82d32-1aef-43e8-ad7b-2b8931fd4570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700439770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.700439770
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.1975033905
Short name T787
Test name
Test status
Simulation time 9611120500 ps
CPU time 145.84 seconds
Started Feb 21 01:03:04 PM PST 24
Finished Feb 21 01:05:30 PM PST 24
Peak memory 264408 kb
Host smart-9104d727-11f1-478c-a99d-839d9e4994ee
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975033905 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.1975033905
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.1589492491
Short name T1078
Test name
Test status
Simulation time 91978800 ps
CPU time 136.69 seconds
Started Feb 21 01:03:04 PM PST 24
Finished Feb 21 01:05:21 PM PST 24
Peak memory 258632 kb
Host smart-d9dd0b80-9811-4efb-a9b5-5caa90d3afb9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589492491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.1589492491
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.665402159
Short name T922
Test name
Test status
Simulation time 1838558200 ps
CPU time 238.9 seconds
Started Feb 21 01:03:19 PM PST 24
Finished Feb 21 01:07:19 PM PST 24
Peak memory 281032 kb
Host smart-ff3a2faf-d8be-41bb-89f5-b2b9f42c8567
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665402159 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.665402159
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.222410773
Short name T229
Test name
Test status
Simulation time 2940973600 ps
CPU time 290.21 seconds
Started Feb 21 01:03:03 PM PST 24
Finished Feb 21 01:07:54 PM PST 24
Peak memory 261688 kb
Host smart-0e38039b-f6f4-4f8c-83ed-1de52cd10a0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222410773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.222410773
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.4278671111
Short name T178
Test name
Test status
Simulation time 794857300 ps
CPU time 75.99 seconds
Started Feb 21 01:03:35 PM PST 24
Finished Feb 21 01:04:51 PM PST 24
Peak memory 264644 kb
Host smart-ea1ed80d-e6ed-4bd6-9307-9877f6ac497f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278671111 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.4278671111
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.2146134202
Short name T219
Test name
Test status
Simulation time 25258900 ps
CPU time 14.26 seconds
Started Feb 21 01:03:51 PM PST 24
Finished Feb 21 01:04:05 PM PST 24
Peak memory 264708 kb
Host smart-37b30132-c9c5-4917-b1e8-0cd99a112121
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146134202 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.2146134202
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.2858077595
Short name T971
Test name
Test status
Simulation time 19052400 ps
CPU time 13.48 seconds
Started Feb 21 01:03:20 PM PST 24
Finished Feb 21 01:03:34 PM PST 24
Peak memory 263700 kb
Host smart-9da965c0-2fae-4666-9cc1-4d8f7273b4d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858077595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.2858077595
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.965223167
Short name T869
Test name
Test status
Simulation time 75114800 ps
CPU time 325.44 seconds
Started Feb 21 01:03:08 PM PST 24
Finished Feb 21 01:08:34 PM PST 24
Peak memory 280776 kb
Host smart-1cde30ff-6dea-4c54-98df-2c41f5e5ef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965223167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.965223167
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.323319864
Short name T227
Test name
Test status
Simulation time 3673912500 ps
CPU time 146.32 seconds
Started Feb 21 01:03:04 PM PST 24
Finished Feb 21 01:05:30 PM PST 24
Peak memory 264456 kb
Host smart-3feb572c-fac0-4219-a865-e013c5ba47d8
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=323319864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.323319864
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.1944546357
Short name T346
Test name
Test status
Simulation time 199447600 ps
CPU time 31.44 seconds
Started Feb 21 01:03:49 PM PST 24
Finished Feb 21 01:04:21 PM PST 24
Peak memory 278712 kb
Host smart-d5cb9120-a4bb-48db-aded-ed60c8bf2a63
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944546357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.1944546357
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.2485206372
Short name T791
Test name
Test status
Simulation time 56679900 ps
CPU time 33.46 seconds
Started Feb 21 01:03:20 PM PST 24
Finished Feb 21 01:03:55 PM PST 24
Peak memory 272836 kb
Host smart-f0d28332-6d7d-451b-9130-e2e17ce6323e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485206372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.2485206372
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1857560112
Short name T1127
Test name
Test status
Simulation time 31731800 ps
CPU time 22.39 seconds
Started Feb 21 01:03:21 PM PST 24
Finished Feb 21 01:03:44 PM PST 24
Peak memory 264580 kb
Host smart-32f9ec1e-5b8d-463d-98b2-95268292d9af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857560112 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.1857560112
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.489022753
Short name T1101
Test name
Test status
Simulation time 88365300 ps
CPU time 22.7 seconds
Started Feb 21 01:03:21 PM PST 24
Finished Feb 21 01:03:44 PM PST 24
Peak memory 264576 kb
Host smart-bd0e9e0d-d51a-48fa-a1d4-c7d69f14275a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489022753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_read_word_sweep_serr.489022753
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.1946311191
Short name T163
Test name
Test status
Simulation time 443102566300 ps
CPU time 1243.28 seconds
Started Feb 21 01:03:50 PM PST 24
Finished Feb 21 01:24:33 PM PST 24
Peak memory 258300 kb
Host smart-1ff80359-a34c-4413-a4ba-ed32b546cb43
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946311191 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.1946311191
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.2048391448
Short name T429
Test name
Test status
Simulation time 513228200 ps
CPU time 115.57 seconds
Started Feb 21 01:03:21 PM PST 24
Finished Feb 21 01:05:17 PM PST 24
Peak memory 280456 kb
Host smart-bc1527cc-9ea6-47b7-a126-672b049ae4dd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048391448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_ro.2048391448
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.2773593132
Short name T831
Test name
Test status
Simulation time 2026417300 ps
CPU time 140.72 seconds
Started Feb 21 01:03:24 PM PST 24
Finished Feb 21 01:05:45 PM PST 24
Peak memory 281032 kb
Host smart-4be10bd5-e264-4fd8-9a28-264fd72291e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2773593132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.2773593132
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.3293360412
Short name T434
Test name
Test status
Simulation time 1424388200 ps
CPU time 113.43 seconds
Started Feb 21 01:03:22 PM PST 24
Finished Feb 21 01:05:16 PM PST 24
Peak memory 281028 kb
Host smart-7e8afaf4-89b9-42f1-9a79-a15d7456d653
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293360412 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.3293360412
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.1346866549
Short name T940
Test name
Test status
Simulation time 13605996700 ps
CPU time 464.16 seconds
Started Feb 21 01:03:23 PM PST 24
Finished Feb 21 01:11:08 PM PST 24
Peak memory 308552 kb
Host smart-4cfaee91-7c20-42db-9240-bc3ac74c7168
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346866549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_rw.1346866549
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.2616858978
Short name T335
Test name
Test status
Simulation time 28129400 ps
CPU time 28.1 seconds
Started Feb 21 01:03:24 PM PST 24
Finished Feb 21 01:03:52 PM PST 24
Peak memory 272188 kb
Host smart-d33049dd-6cc1-4b2a-823e-f71e3bc8729b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616858978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.2616858978
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2562590643
Short name T616
Test name
Test status
Simulation time 45005800 ps
CPU time 30.93 seconds
Started Feb 21 01:03:19 PM PST 24
Finished Feb 21 01:03:51 PM PST 24
Peak memory 274868 kb
Host smart-f0129444-b20d-4f5f-8737-ee54db7a07ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562590643 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2562590643
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.1360054098
Short name T991
Test name
Test status
Simulation time 3202699600 ps
CPU time 566.16 seconds
Started Feb 21 01:03:20 PM PST 24
Finished Feb 21 01:12:46 PM PST 24
Peak memory 312256 kb
Host smart-eac1bed2-a9cd-4158-82a0-7770d482e927
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360054098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.1360054098
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.1582657981
Short name T406
Test name
Test status
Simulation time 2819997400 ps
CPU time 68.05 seconds
Started Feb 21 01:03:19 PM PST 24
Finished Feb 21 01:04:28 PM PST 24
Peak memory 263428 kb
Host smart-7ea58bb1-fbb6-49a2-908f-6e883ee6615f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582657981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.1582657981
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.543075648
Short name T545
Test name
Test status
Simulation time 2740162700 ps
CPU time 80.43 seconds
Started Feb 21 01:03:19 PM PST 24
Finished Feb 21 01:04:40 PM PST 24
Peak memory 264576 kb
Host smart-b63ca8bd-e876-4670-a336-9a97f2dc0951
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543075648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_serr_address.543075648
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.3010862993
Short name T721
Test name
Test status
Simulation time 637981700 ps
CPU time 45.38 seconds
Started Feb 21 01:03:19 PM PST 24
Finished Feb 21 01:04:05 PM PST 24
Peak memory 272848 kb
Host smart-e8dfe2dd-9602-4385-9a60-7fe8beb097d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010862993 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.3010862993
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.2716080385
Short name T611
Test name
Test status
Simulation time 14777800 ps
CPU time 76.34 seconds
Started Feb 21 01:03:04 PM PST 24
Finished Feb 21 01:04:21 PM PST 24
Peak memory 275072 kb
Host smart-f74a141b-e68e-40a2-927a-4702431b2e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716080385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2716080385
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.210865638
Short name T815
Test name
Test status
Simulation time 15896600 ps
CPU time 26.39 seconds
Started Feb 21 01:03:07 PM PST 24
Finished Feb 21 01:03:33 PM PST 24
Peak memory 258428 kb
Host smart-73993168-2907-42c3-8aa9-672a62b7e93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210865638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.210865638
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.1338722359
Short name T140
Test name
Test status
Simulation time 8698761200 ps
CPU time 1780.74 seconds
Started Feb 21 01:03:51 PM PST 24
Finished Feb 21 01:33:33 PM PST 24
Peak memory 289076 kb
Host smart-ca441f65-9109-47f0-b346-f161d81ecde6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338722359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.1338722359
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.464269639
Short name T812
Test name
Test status
Simulation time 191370900 ps
CPU time 26.34 seconds
Started Feb 21 01:03:06 PM PST 24
Finished Feb 21 01:03:33 PM PST 24
Peak memory 258656 kb
Host smart-48849f91-147f-476a-b454-0bf077e37b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464269639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.464269639
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.2067693831
Short name T952
Test name
Test status
Simulation time 2242790000 ps
CPU time 159.52 seconds
Started Feb 21 01:03:24 PM PST 24
Finished Feb 21 01:06:04 PM PST 24
Peak memory 263120 kb
Host smart-7e6a6f02-0aa5-4fb5-8e5b-2ee172fdef66
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067693831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_wo.2067693831
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.1934142870
Short name T435
Test name
Test status
Simulation time 106447900 ps
CPU time 13.55 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:08:30 PM PST 24
Peak memory 263900 kb
Host smart-08cf71a5-c38d-4401-9a7b-046071828af4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934142870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
1934142870
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.567126817
Short name T972
Test name
Test status
Simulation time 14711400 ps
CPU time 16.32 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:08:33 PM PST 24
Peak memory 274868 kb
Host smart-8bd436f9-159b-40ed-8f28-f998379e6c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567126817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.567126817
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.4167536817
Short name T984
Test name
Test status
Simulation time 38924400 ps
CPU time 21.83 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:08:38 PM PST 24
Peak memory 279656 kb
Host smart-77424e2d-dd64-4d63-b3f5-e399378d3397
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167536817 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.4167536817
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2471072310
Short name T983
Test name
Test status
Simulation time 8115660000 ps
CPU time 214.28 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:11:50 PM PST 24
Peak memory 261296 kb
Host smart-f3de46f4-6dac-4cf8-873e-2adde13746b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471072310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.2471072310
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.3815438922
Short name T1070
Test name
Test status
Simulation time 1840026900 ps
CPU time 139.93 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:10:36 PM PST 24
Peak memory 292872 kb
Host smart-0545c5ea-a3a9-469e-916b-2a57005144c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815438922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.3815438922
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2260005550
Short name T948
Test name
Test status
Simulation time 46525460300 ps
CPU time 249.15 seconds
Started Feb 21 01:08:17 PM PST 24
Finished Feb 21 01:12:27 PM PST 24
Peak memory 284068 kb
Host smart-7017e688-2a37-4dfd-8414-62bc4b829ca0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260005550 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.2260005550
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.3913960489
Short name T419
Test name
Test status
Simulation time 228509000 ps
CPU time 13.42 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:08:30 PM PST 24
Peak memory 264360 kb
Host smart-c22699b6-20b4-4deb-9ad8-6f6b015ac8aa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913960489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.3913960489
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.2630538319
Short name T667
Test name
Test status
Simulation time 75162100 ps
CPU time 32.05 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:08:48 PM PST 24
Peak memory 274936 kb
Host smart-c3ff4d8a-12a6-4c90-957f-ac59e47af181
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630538319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.2630538319
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2938579134
Short name T1106
Test name
Test status
Simulation time 74402600 ps
CPU time 31.42 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:08:48 PM PST 24
Peak memory 271708 kb
Host smart-64858412-afcb-42e4-94ae-5f09bdeb8616
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938579134 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2938579134
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.3586978268
Short name T692
Test name
Test status
Simulation time 9643068600 ps
CPU time 68.39 seconds
Started Feb 21 01:08:17 PM PST 24
Finished Feb 21 01:09:26 PM PST 24
Peak memory 263292 kb
Host smart-f3874f96-7820-4d17-aa30-1e7876a1d13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586978268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3586978268
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.4153520912
Short name T763
Test name
Test status
Simulation time 56672100 ps
CPU time 52.23 seconds
Started Feb 21 01:08:17 PM PST 24
Finished Feb 21 01:09:10 PM PST 24
Peak memory 269732 kb
Host smart-f4ef1444-f5a4-480b-a219-290350d3f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153520912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.4153520912
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.3926652032
Short name T442
Test name
Test status
Simulation time 31084500 ps
CPU time 13.99 seconds
Started Feb 21 01:08:29 PM PST 24
Finished Feb 21 01:08:43 PM PST 24
Peak memory 264512 kb
Host smart-9af66902-5c93-45b3-bc75-3c5252e01122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926652032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
3926652032
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.3893948505
Short name T573
Test name
Test status
Simulation time 13413900 ps
CPU time 15.9 seconds
Started Feb 21 01:08:32 PM PST 24
Finished Feb 21 01:08:48 PM PST 24
Peak memory 274168 kb
Host smart-ac4668bc-a34d-441f-a76d-76609fdf7014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893948505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.3893948505
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.758829768
Short name T323
Test name
Test status
Simulation time 17804308000 ps
CPU time 130.6 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:10:27 PM PST 24
Peak memory 261460 kb
Host smart-b775ebc4-d0fb-4cc8-a099-9819a2a91507
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758829768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_h
w_sec_otp.758829768
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.1804690449
Short name T566
Test name
Test status
Simulation time 2629129100 ps
CPU time 163.37 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:11:00 PM PST 24
Peak memory 292652 kb
Host smart-10403790-31b4-4e5d-ad2e-2f61deeccddf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804690449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.1804690449
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.58668866
Short name T1090
Test name
Test status
Simulation time 17115859200 ps
CPU time 184.41 seconds
Started Feb 21 01:08:15 PM PST 24
Finished Feb 21 01:11:20 PM PST 24
Peak memory 292160 kb
Host smart-379546d5-bf00-45bd-8af2-9ed0316c4104
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58668866 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.58668866
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.3197861136
Short name T994
Test name
Test status
Simulation time 141875800 ps
CPU time 133.43 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:10:30 PM PST 24
Peak memory 258916 kb
Host smart-c8c559f7-95d5-41ee-ba04-b0e3883d4a60
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197861136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.3197861136
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.3850647493
Short name T888
Test name
Test status
Simulation time 79560000 ps
CPU time 13.54 seconds
Started Feb 21 01:08:28 PM PST 24
Finished Feb 21 01:08:42 PM PST 24
Peak memory 264428 kb
Host smart-8d2d2e22-5238-453e-9a18-35cb8ee83e22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850647493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.3850647493
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.396058019
Short name T696
Test name
Test status
Simulation time 38737700 ps
CPU time 30.78 seconds
Started Feb 21 01:08:28 PM PST 24
Finished Feb 21 01:08:59 PM PST 24
Peak memory 271624 kb
Host smart-48534957-092f-40bc-87a3-df024d6b95a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396058019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_rw_evict.396058019
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.3996556189
Short name T891
Test name
Test status
Simulation time 29225200 ps
CPU time 31.27 seconds
Started Feb 21 01:08:34 PM PST 24
Finished Feb 21 01:09:07 PM PST 24
Peak memory 265600 kb
Host smart-baa1bb28-b39a-49f5-ad94-37eae1ab22c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996556189 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.3996556189
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.2800266698
Short name T749
Test name
Test status
Simulation time 3027319800 ps
CPU time 56.11 seconds
Started Feb 21 01:08:30 PM PST 24
Finished Feb 21 01:09:27 PM PST 24
Peak memory 262892 kb
Host smart-af501a03-372b-45de-94ea-fef1d72cd643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800266698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2800266698
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.2114559717
Short name T560
Test name
Test status
Simulation time 23405900 ps
CPU time 122.68 seconds
Started Feb 21 01:08:16 PM PST 24
Finished Feb 21 01:10:19 PM PST 24
Peak memory 276160 kb
Host smart-4001eca7-ef3e-45e7-9e44-06df645185ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114559717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2114559717
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.2310670200
Short name T383
Test name
Test status
Simulation time 51313600 ps
CPU time 13.29 seconds
Started Feb 21 01:08:30 PM PST 24
Finished Feb 21 01:08:44 PM PST 24
Peak memory 263508 kb
Host smart-da773bd2-d154-49d5-8284-5276b9760e1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310670200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
2310670200
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.1599083054
Short name T662
Test name
Test status
Simulation time 88497000 ps
CPU time 15.51 seconds
Started Feb 21 01:08:32 PM PST 24
Finished Feb 21 01:08:48 PM PST 24
Peak memory 273952 kb
Host smart-2a64cc48-6303-4612-b6f0-d1db7710f647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599083054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.1599083054
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.3812330965
Short name T604
Test name
Test status
Simulation time 22353900 ps
CPU time 20.53 seconds
Started Feb 21 01:08:29 PM PST 24
Finished Feb 21 01:08:50 PM PST 24
Peak memory 272888 kb
Host smart-1404871e-228f-4df1-8927-fdc23d05d4a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812330965 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.3812330965
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.665481841
Short name T559
Test name
Test status
Simulation time 13035504900 ps
CPU time 115.66 seconds
Started Feb 21 01:08:30 PM PST 24
Finished Feb 21 01:10:26 PM PST 24
Peak memory 261756 kb
Host smart-793c2a12-38d6-46f0-bb90-635a05a81e9b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665481841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_h
w_sec_otp.665481841
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.3048610987
Short name T960
Test name
Test status
Simulation time 1192056800 ps
CPU time 159.66 seconds
Started Feb 21 01:08:31 PM PST 24
Finished Feb 21 01:11:11 PM PST 24
Peak memory 293272 kb
Host smart-7f60e861-364a-4e60-9d53-1ad0c2358e97
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048610987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.3048610987
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2580055999
Short name T687
Test name
Test status
Simulation time 16000135400 ps
CPU time 197.53 seconds
Started Feb 21 01:08:29 PM PST 24
Finished Feb 21 01:11:46 PM PST 24
Peak memory 284044 kb
Host smart-c2d8a5ef-0e58-4f6f-9df7-eed2f427c4a6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580055999 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.2580055999
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.4031165762
Short name T863
Test name
Test status
Simulation time 110591300 ps
CPU time 111.91 seconds
Started Feb 21 01:08:27 PM PST 24
Finished Feb 21 01:10:19 PM PST 24
Peak memory 258696 kb
Host smart-4fbbd56d-2bf7-4836-824a-4a9b0cf834a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031165762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.4031165762
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.1515834792
Short name T659
Test name
Test status
Simulation time 47145200 ps
CPU time 14.05 seconds
Started Feb 21 01:08:30 PM PST 24
Finished Feb 21 01:08:44 PM PST 24
Peak memory 264428 kb
Host smart-71b0701c-658f-467d-baa8-ad63e3cb0aad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515834792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.1515834792
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.69304128
Short name T732
Test name
Test status
Simulation time 74491000 ps
CPU time 30.64 seconds
Started Feb 21 01:08:32 PM PST 24
Finished Feb 21 01:09:03 PM PST 24
Peak memory 274840 kb
Host smart-c448decc-3ba8-4432-aa45-d698faa3777d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69304128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flas
h_ctrl_rw_evict.69304128
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.1984220461
Short name T593
Test name
Test status
Simulation time 42942500 ps
CPU time 31.15 seconds
Started Feb 21 01:08:28 PM PST 24
Finished Feb 21 01:08:59 PM PST 24
Peak memory 272828 kb
Host smart-826a2807-bc2b-4101-8e76-e11dc282717d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984220461 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.1984220461
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.584589090
Short name T919
Test name
Test status
Simulation time 6925363700 ps
CPU time 63.03 seconds
Started Feb 21 01:08:35 PM PST 24
Finished Feb 21 01:09:39 PM PST 24
Peak memory 263456 kb
Host smart-bd9d33a2-68f4-4976-9550-8e99b7f8f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584589090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.584589090
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.1667673161
Short name T1119
Test name
Test status
Simulation time 41468400 ps
CPU time 124.17 seconds
Started Feb 21 01:08:32 PM PST 24
Finished Feb 21 01:10:37 PM PST 24
Peak memory 276072 kb
Host smart-63ae1bbf-c976-4e88-bb14-3359cb512740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667673161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.1667673161
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.1589855739
Short name T428
Test name
Test status
Simulation time 115603800 ps
CPU time 13.78 seconds
Started Feb 21 01:08:35 PM PST 24
Finished Feb 21 01:08:49 PM PST 24
Peak memory 263984 kb
Host smart-626b2d26-e3e1-47ab-8c45-78bbeb4c1039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589855739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
1589855739
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.3107006659
Short name T811
Test name
Test status
Simulation time 14872000 ps
CPU time 13.83 seconds
Started Feb 21 01:08:29 PM PST 24
Finished Feb 21 01:08:43 PM PST 24
Peak memory 273816 kb
Host smart-41cd4b0f-5abd-4242-aa3e-325a8bee381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107006659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.3107006659
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.3449466643
Short name T683
Test name
Test status
Simulation time 19759200 ps
CPU time 21.74 seconds
Started Feb 21 01:08:29 PM PST 24
Finished Feb 21 01:08:51 PM PST 24
Peak memory 279444 kb
Host smart-e15871cb-840c-4527-807f-0ece0f9c973e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449466643 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.3449466643
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.3158658359
Short name T856
Test name
Test status
Simulation time 2836692800 ps
CPU time 64.34 seconds
Started Feb 21 01:08:28 PM PST 24
Finished Feb 21 01:09:33 PM PST 24
Peak memory 258316 kb
Host smart-dce7dd20-606e-4a09-a744-c192de15fbaf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158658359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.3158658359
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.4194498555
Short name T287
Test name
Test status
Simulation time 4630531700 ps
CPU time 151.4 seconds
Started Feb 21 01:08:28 PM PST 24
Finished Feb 21 01:10:59 PM PST 24
Peak memory 293308 kb
Host smart-26ae46d9-ef61-4df9-bc72-13f0f3d8765b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194498555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.4194498555
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2304766603
Short name T223
Test name
Test status
Simulation time 45924748300 ps
CPU time 202.41 seconds
Started Feb 21 01:08:30 PM PST 24
Finished Feb 21 01:11:53 PM PST 24
Peak memory 283972 kb
Host smart-2c8de679-cd72-4805-97f1-312c063631a2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304766603 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2304766603
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.2312970855
Short name T160
Test name
Test status
Simulation time 150565400 ps
CPU time 113.96 seconds
Started Feb 21 01:08:30 PM PST 24
Finished Feb 21 01:10:24 PM PST 24
Peak memory 259080 kb
Host smart-0e65bc0c-23fd-42a4-90b3-57670f850736
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312970855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.2312970855
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.1479295405
Short name T620
Test name
Test status
Simulation time 47708000 ps
CPU time 13.48 seconds
Started Feb 21 01:08:30 PM PST 24
Finished Feb 21 01:08:44 PM PST 24
Peak memory 264452 kb
Host smart-4956af8a-f1c2-49f5-a97e-8b31c7c07d43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479295405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.1479295405
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.1511935221
Short name T341
Test name
Test status
Simulation time 98644300 ps
CPU time 28.34 seconds
Started Feb 21 01:08:39 PM PST 24
Finished Feb 21 01:09:08 PM PST 24
Peak memory 274780 kb
Host smart-8a69ba4c-287f-4bba-a67a-3adee3632e4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511935221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.1511935221
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.1893301640
Short name T1030
Test name
Test status
Simulation time 29544200 ps
CPU time 31.41 seconds
Started Feb 21 01:08:31 PM PST 24
Finished Feb 21 01:09:03 PM PST 24
Peak memory 274876 kb
Host smart-71d677f8-c4eb-4a46-80e7-90216ae48f5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893301640 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.1893301640
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.2180659425
Short name T963
Test name
Test status
Simulation time 4362270000 ps
CPU time 70.98 seconds
Started Feb 21 01:08:31 PM PST 24
Finished Feb 21 01:09:42 PM PST 24
Peak memory 263352 kb
Host smart-f5549b24-55a5-4c0c-8d87-39e880fcc241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180659425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.2180659425
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.499909770
Short name T543
Test name
Test status
Simulation time 81743500 ps
CPU time 98.77 seconds
Started Feb 21 01:08:27 PM PST 24
Finished Feb 21 01:10:06 PM PST 24
Peak memory 274216 kb
Host smart-aaacf29c-3dc5-4c76-a2a1-6504c114e64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499909770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.499909770
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.2253907463
Short name T619
Test name
Test status
Simulation time 354842100 ps
CPU time 14.03 seconds
Started Feb 21 01:08:45 PM PST 24
Finished Feb 21 01:09:00 PM PST 24
Peak memory 264212 kb
Host smart-a0090e9f-315e-449d-87ee-c83df6e14201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253907463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
2253907463
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.31991901
Short name T713
Test name
Test status
Simulation time 18941500 ps
CPU time 15.66 seconds
Started Feb 21 01:08:58 PM PST 24
Finished Feb 21 01:09:14 PM PST 24
Peak memory 274800 kb
Host smart-fed3553d-d4e0-495c-878d-b5ed584554f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31991901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.31991901
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.2570635095
Short name T937
Test name
Test status
Simulation time 10276200 ps
CPU time 22.25 seconds
Started Feb 21 01:08:48 PM PST 24
Finished Feb 21 01:09:11 PM PST 24
Peak memory 272804 kb
Host smart-7977875d-2a96-4124-b386-96f3b2c12010
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570635095 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.2570635095
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.3959642784
Short name T589
Test name
Test status
Simulation time 1967408200 ps
CPU time 124.81 seconds
Started Feb 21 01:08:46 PM PST 24
Finished Feb 21 01:10:51 PM PST 24
Peak memory 261604 kb
Host smart-2bb6debb-f2c8-43e4-86ff-5c63a9c77493
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959642784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.3959642784
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.2196406412
Short name T433
Test name
Test status
Simulation time 2648972200 ps
CPU time 151.24 seconds
Started Feb 21 01:08:51 PM PST 24
Finished Feb 21 01:11:23 PM PST 24
Peak memory 292672 kb
Host smart-0f735998-f8e7-44df-997e-99b1ace9217b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196406412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.2196406412
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.4147987666
Short name T941
Test name
Test status
Simulation time 31607045200 ps
CPU time 230.32 seconds
Started Feb 21 01:08:46 PM PST 24
Finished Feb 21 01:12:37 PM PST 24
Peak memory 284192 kb
Host smart-87e7adce-f887-4d44-891a-edc1bd1ab6ab
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147987666 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.4147987666
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.2832858316
Short name T799
Test name
Test status
Simulation time 169308400 ps
CPU time 136.97 seconds
Started Feb 21 01:08:48 PM PST 24
Finished Feb 21 01:11:06 PM PST 24
Peak memory 259020 kb
Host smart-b25fd7ce-1d24-402c-9caf-2e3a914cb215
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832858316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.2832858316
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.26712628
Short name T1098
Test name
Test status
Simulation time 33757900 ps
CPU time 14.07 seconds
Started Feb 21 01:08:49 PM PST 24
Finished Feb 21 01:09:03 PM PST 24
Peak memory 264352 kb
Host smart-cd2c80cf-e1e6-42c3-b8f8-ebe6831b8f33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26712628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_rese
t.26712628
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.2631681604
Short name T979
Test name
Test status
Simulation time 57025300 ps
CPU time 33.71 seconds
Started Feb 21 01:08:44 PM PST 24
Finished Feb 21 01:09:19 PM PST 24
Peak memory 265636 kb
Host smart-0cc05139-7bc2-40fc-b6b3-90e1ff2f9662
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631681604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.2631681604
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.831302805
Short name T980
Test name
Test status
Simulation time 52970400 ps
CPU time 31.31 seconds
Started Feb 21 01:08:44 PM PST 24
Finished Feb 21 01:09:16 PM PST 24
Peak memory 276064 kb
Host smart-e0ef5ef6-b07e-4b1f-b42b-93481ec83b78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831302805 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.831302805
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.3857679489
Short name T467
Test name
Test status
Simulation time 8816804100 ps
CPU time 80.13 seconds
Started Feb 21 01:09:00 PM PST 24
Finished Feb 21 01:10:21 PM PST 24
Peak memory 263396 kb
Host smart-034fcaea-e391-4ade-81b2-c06fb18a4c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857679489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3857679489
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.35265403
Short name T808
Test name
Test status
Simulation time 88687200 ps
CPU time 49.19 seconds
Started Feb 21 01:08:42 PM PST 24
Finished Feb 21 01:09:32 PM PST 24
Peak memory 269712 kb
Host smart-0830ac71-6b7c-49ef-a926-aec783c2d9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35265403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.35265403
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.3060156632
Short name T90
Test name
Test status
Simulation time 82270700 ps
CPU time 13.56 seconds
Started Feb 21 01:08:55 PM PST 24
Finished Feb 21 01:09:09 PM PST 24
Peak memory 263960 kb
Host smart-8b9f4977-fc26-4d18-b2b7-aba21c643d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060156632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
3060156632
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.265530518
Short name T655
Test name
Test status
Simulation time 102689100 ps
CPU time 16.06 seconds
Started Feb 21 01:08:56 PM PST 24
Finished Feb 21 01:09:13 PM PST 24
Peak memory 274780 kb
Host smart-7dd53304-b321-4a98-b8ab-829519a8ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265530518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.265530518
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.248892770
Short name T1099
Test name
Test status
Simulation time 20461200 ps
CPU time 21.96 seconds
Started Feb 21 01:08:45 PM PST 24
Finished Feb 21 01:09:07 PM PST 24
Peak memory 272872 kb
Host smart-1f25d8d7-82ea-4aba-a16b-c43a3408b867
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248892770 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.248892770
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.686926172
Short name T935
Test name
Test status
Simulation time 1225827000 ps
CPU time 103.52 seconds
Started Feb 21 01:08:42 PM PST 24
Finished Feb 21 01:10:27 PM PST 24
Peak memory 258236 kb
Host smart-6abfba80-768f-4e3a-bfc3-0b38b396111d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686926172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_h
w_sec_otp.686926172
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.4097435749
Short name T645
Test name
Test status
Simulation time 1014369600 ps
CPU time 153.46 seconds
Started Feb 21 01:08:44 PM PST 24
Finished Feb 21 01:11:18 PM PST 24
Peak memory 292800 kb
Host smart-07a92bc6-ee11-499f-a9ff-69d7b7637063
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097435749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_intr_rd.4097435749
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3043144725
Short name T930
Test name
Test status
Simulation time 17333901200 ps
CPU time 197.18 seconds
Started Feb 21 01:08:58 PM PST 24
Finished Feb 21 01:12:16 PM PST 24
Peak memory 293184 kb
Host smart-c43aaba7-6d09-403a-ad4b-c56acab9081c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043144725 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.3043144725
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.1097366343
Short name T1052
Test name
Test status
Simulation time 182614600 ps
CPU time 13.75 seconds
Started Feb 21 01:08:46 PM PST 24
Finished Feb 21 01:09:00 PM PST 24
Peak memory 264428 kb
Host smart-442eedaf-b46c-4f44-99cb-dc1f459ad640
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097366343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.1097366343
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.3925410888
Short name T344
Test name
Test status
Simulation time 31996600 ps
CPU time 31.19 seconds
Started Feb 21 01:08:48 PM PST 24
Finished Feb 21 01:09:20 PM PST 24
Peak memory 272860 kb
Host smart-4562efc9-c0d6-4cbd-aa25-dc017c7a415c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925410888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.3925410888
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.3881388057
Short name T855
Test name
Test status
Simulation time 57939100 ps
CPU time 30.81 seconds
Started Feb 21 01:08:49 PM PST 24
Finished Feb 21 01:09:20 PM PST 24
Peak memory 273784 kb
Host smart-edb5e323-f94f-49e9-8368-f842b946acc3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881388057 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.3881388057
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.690170055
Short name T882
Test name
Test status
Simulation time 24682300 ps
CPU time 97.09 seconds
Started Feb 21 01:08:48 PM PST 24
Finished Feb 21 01:10:26 PM PST 24
Peak memory 274332 kb
Host smart-6c78729f-9cb3-4f51-a3a6-a26b3c4fbce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690170055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.690170055
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.1760388040
Short name T432
Test name
Test status
Simulation time 82157800 ps
CPU time 13.74 seconds
Started Feb 21 01:09:07 PM PST 24
Finished Feb 21 01:09:21 PM PST 24
Peak memory 264488 kb
Host smart-c18cf181-8953-46cc-8b6d-88a48eafa0cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760388040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
1760388040
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.2310737944
Short name T520
Test name
Test status
Simulation time 26059800 ps
CPU time 15.92 seconds
Started Feb 21 01:08:59 PM PST 24
Finished Feb 21 01:09:15 PM PST 24
Peak memory 274016 kb
Host smart-1283fa31-8bf6-4f88-b388-740c58a641c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310737944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.2310737944
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.2326641892
Short name T781
Test name
Test status
Simulation time 14016700 ps
CPU time 22.04 seconds
Started Feb 21 01:09:08 PM PST 24
Finished Feb 21 01:09:31 PM PST 24
Peak memory 279408 kb
Host smart-e8b7dc66-eae6-40a4-a571-a68d89fc7ad9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326641892 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.2326641892
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.994578158
Short name T933
Test name
Test status
Simulation time 595960200 ps
CPU time 62.68 seconds
Started Feb 21 01:09:01 PM PST 24
Finished Feb 21 01:10:04 PM PST 24
Peak memory 258388 kb
Host smart-eb79358e-739e-4181-98ae-1eb7fb225644
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994578158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_h
w_sec_otp.994578158
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.2243022387
Short name T1079
Test name
Test status
Simulation time 2707145400 ps
CPU time 164.02 seconds
Started Feb 21 01:09:00 PM PST 24
Finished Feb 21 01:11:45 PM PST 24
Peak memory 293288 kb
Host smart-68472328-b97c-4939-b2ff-31175697149e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243022387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.2243022387
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1239937590
Short name T962
Test name
Test status
Simulation time 83063868300 ps
CPU time 242.76 seconds
Started Feb 21 01:09:06 PM PST 24
Finished Feb 21 01:13:09 PM PST 24
Peak memory 293192 kb
Host smart-897b2781-c53f-4372-9e6b-ed2b76d79195
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239937590 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1239937590
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.3217992030
Short name T788
Test name
Test status
Simulation time 40610800 ps
CPU time 114.67 seconds
Started Feb 21 01:09:01 PM PST 24
Finished Feb 21 01:10:56 PM PST 24
Peak memory 259196 kb
Host smart-ff0da04d-32e3-443b-86d3-a5a44f5cfef0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217992030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.3217992030
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.47481275
Short name T1121
Test name
Test status
Simulation time 32989700 ps
CPU time 13.6 seconds
Started Feb 21 01:08:59 PM PST 24
Finished Feb 21 01:09:14 PM PST 24
Peak memory 264456 kb
Host smart-d658a44b-4b4b-4348-8bb6-d378a1a43440
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47481275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_rese
t.47481275
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.2215898857
Short name T445
Test name
Test status
Simulation time 85787200 ps
CPU time 31.99 seconds
Started Feb 21 01:08:58 PM PST 24
Finished Feb 21 01:09:30 PM PST 24
Peak memory 273828 kb
Host smart-96c1f0e9-c88f-4797-a8a0-214b651d232c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215898857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.2215898857
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3969611475
Short name T338
Test name
Test status
Simulation time 31502600 ps
CPU time 31.65 seconds
Started Feb 21 01:09:00 PM PST 24
Finished Feb 21 01:09:32 PM PST 24
Peak memory 272796 kb
Host smart-4c801ef6-a06c-4ec5-b847-0d9063dfe2bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969611475 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.3969611475
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.2321119913
Short name T626
Test name
Test status
Simulation time 2686341900 ps
CPU time 54.41 seconds
Started Feb 21 01:09:09 PM PST 24
Finished Feb 21 01:10:05 PM PST 24
Peak memory 258660 kb
Host smart-64a1ceb0-1449-4db9-ad2e-df9161b13f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321119913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2321119913
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.994132852
Short name T627
Test name
Test status
Simulation time 42909900 ps
CPU time 97.82 seconds
Started Feb 21 01:08:58 PM PST 24
Finished Feb 21 01:10:36 PM PST 24
Peak memory 274244 kb
Host smart-fb0680ee-e918-4ab0-b400-72f16da75599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994132852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.994132852
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.3729202727
Short name T954
Test name
Test status
Simulation time 43015000 ps
CPU time 13.52 seconds
Started Feb 21 01:09:08 PM PST 24
Finished Feb 21 01:09:23 PM PST 24
Peak memory 264488 kb
Host smart-4aea9202-b652-41cc-b43c-d3c2225de556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729202727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
3729202727
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.3939938522
Short name T425
Test name
Test status
Simulation time 16723200 ps
CPU time 13.24 seconds
Started Feb 21 01:09:07 PM PST 24
Finished Feb 21 01:09:21 PM PST 24
Peak memory 274844 kb
Host smart-bf56d29b-bdec-4173-8e7b-7bed444df253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939938522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3939938522
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.244183370
Short name T172
Test name
Test status
Simulation time 11407300 ps
CPU time 21.13 seconds
Started Feb 21 01:08:59 PM PST 24
Finished Feb 21 01:09:21 PM PST 24
Peak memory 272872 kb
Host smart-13c665c4-64c2-453e-840f-124cc7ef3b74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244183370 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.244183370
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.431474414
Short name T473
Test name
Test status
Simulation time 1205523500 ps
CPU time 36.58 seconds
Started Feb 21 01:08:58 PM PST 24
Finished Feb 21 01:09:36 PM PST 24
Peak memory 261136 kb
Host smart-ac1fd31b-6dc7-443e-bd0d-691441a6b949
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431474414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_h
w_sec_otp.431474414
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.1729875891
Short name T689
Test name
Test status
Simulation time 1139454600 ps
CPU time 171.27 seconds
Started Feb 21 01:09:05 PM PST 24
Finished Feb 21 01:11:56 PM PST 24
Peak memory 289136 kb
Host smart-977e7a02-d613-495e-a5a5-199ccbdbf7c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729875891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.1729875891
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1729361535
Short name T320
Test name
Test status
Simulation time 8723007500 ps
CPU time 211.04 seconds
Started Feb 21 01:09:00 PM PST 24
Finished Feb 21 01:12:32 PM PST 24
Peak memory 283716 kb
Host smart-972a4ffc-5c12-4b28-b91e-ed8260c08f3b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729361535 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1729361535
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.928041633
Short name T475
Test name
Test status
Simulation time 130650900 ps
CPU time 131.59 seconds
Started Feb 21 01:09:02 PM PST 24
Finished Feb 21 01:11:15 PM PST 24
Peak memory 261496 kb
Host smart-1f6b6afa-2018-4341-a93f-5293e1a5fc29
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928041633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ot
p_reset.928041633
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.4033709794
Short name T836
Test name
Test status
Simulation time 32663100 ps
CPU time 14.32 seconds
Started Feb 21 01:08:59 PM PST 24
Finished Feb 21 01:09:15 PM PST 24
Peak memory 264416 kb
Host smart-0291b7d6-4b1e-4d9d-89de-db63fe2ed9f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033709794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.4033709794
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.141823778
Short name T671
Test name
Test status
Simulation time 43057900 ps
CPU time 31.06 seconds
Started Feb 21 01:09:17 PM PST 24
Finished Feb 21 01:09:49 PM PST 24
Peak memory 273832 kb
Host smart-9fbe4b79-2574-411d-9293-2a2f741e3b77
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141823778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_rw_evict.141823778
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.3216073556
Short name T967
Test name
Test status
Simulation time 31312000 ps
CPU time 31.02 seconds
Started Feb 21 01:08:58 PM PST 24
Finished Feb 21 01:09:30 PM PST 24
Peak memory 273860 kb
Host smart-b75bfc8f-4624-4e40-892c-d0b85d52a5db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216073556 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.3216073556
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.1215220297
Short name T371
Test name
Test status
Simulation time 2059471700 ps
CPU time 74.16 seconds
Started Feb 21 01:09:01 PM PST 24
Finished Feb 21 01:10:16 PM PST 24
Peak memory 258772 kb
Host smart-ef802825-b89a-4df5-8812-32e2812f3aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215220297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.1215220297
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.3368510260
Short name T476
Test name
Test status
Simulation time 83195900 ps
CPU time 147.58 seconds
Started Feb 21 01:09:00 PM PST 24
Finished Feb 21 01:11:28 PM PST 24
Peak memory 276700 kb
Host smart-e05677c5-6cff-445d-9428-8d4c3bac14ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368510260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.3368510260
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.2925801482
Short name T613
Test name
Test status
Simulation time 119010300 ps
CPU time 13.77 seconds
Started Feb 21 01:09:10 PM PST 24
Finished Feb 21 01:09:24 PM PST 24
Peak memory 263928 kb
Host smart-e8ea7347-fc77-49e0-85bd-badde2f3aaeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925801482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
2925801482
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.646950437
Short name T801
Test name
Test status
Simulation time 28412300 ps
CPU time 15.79 seconds
Started Feb 21 01:09:17 PM PST 24
Finished Feb 21 01:09:34 PM PST 24
Peak memory 274788 kb
Host smart-d123f270-c990-4e9a-a9f9-f22baacf35ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646950437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.646950437
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.2196353393
Short name T649
Test name
Test status
Simulation time 16361500 ps
CPU time 21.95 seconds
Started Feb 21 01:09:10 PM PST 24
Finished Feb 21 01:09:33 PM PST 24
Peak memory 272796 kb
Host smart-92af9afa-1f3d-46c6-88fe-97f5dcad8931
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196353393 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.2196353393
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2186811348
Short name T426
Test name
Test status
Simulation time 3470238900 ps
CPU time 149.66 seconds
Started Feb 21 01:09:09 PM PST 24
Finished Feb 21 01:11:40 PM PST 24
Peak memory 261628 kb
Host smart-ff4cbcc5-45d4-4124-933d-4d2cc85628c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186811348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.2186811348
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.2173108366
Short name T744
Test name
Test status
Simulation time 1327199500 ps
CPU time 162.79 seconds
Started Feb 21 01:09:16 PM PST 24
Finished Feb 21 01:12:00 PM PST 24
Peak memory 289156 kb
Host smart-868ee88b-a824-4340-9e53-ea24af475ee4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173108366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.2173108366
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3348882200
Short name T828
Test name
Test status
Simulation time 7602994900 ps
CPU time 178.49 seconds
Started Feb 21 01:09:09 PM PST 24
Finished Feb 21 01:12:08 PM PST 24
Peak memory 289156 kb
Host smart-69b7b378-44a5-48a0-90d1-20a4c54c4ce2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348882200 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3348882200
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.2726262478
Short name T568
Test name
Test status
Simulation time 72312000 ps
CPU time 136.23 seconds
Started Feb 21 01:09:17 PM PST 24
Finished Feb 21 01:11:34 PM PST 24
Peak memory 258676 kb
Host smart-2d47b47d-1cd5-47ac-9996-5695a8e93657
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726262478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.2726262478
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.2775634287
Short name T501
Test name
Test status
Simulation time 21882300 ps
CPU time 13.48 seconds
Started Feb 21 01:09:10 PM PST 24
Finished Feb 21 01:09:24 PM PST 24
Peak memory 264424 kb
Host smart-415a0567-ad13-41d9-a672-daab9b41775e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775634287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.2775634287
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.4196595953
Short name T1109
Test name
Test status
Simulation time 180648900 ps
CPU time 35.37 seconds
Started Feb 21 01:09:17 PM PST 24
Finished Feb 21 01:09:53 PM PST 24
Peak memory 272820 kb
Host smart-0d09ec1b-c0ea-49a2-8d90-0fdfcf5c11d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196595953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.4196595953
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.413110291
Short name T1036
Test name
Test status
Simulation time 44966200 ps
CPU time 31.54 seconds
Started Feb 21 01:09:17 PM PST 24
Finished Feb 21 01:09:49 PM PST 24
Peak memory 274800 kb
Host smart-fb0b1a38-4326-4036-807a-6b109a2e0e53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413110291 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.413110291
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.146599228
Short name T401
Test name
Test status
Simulation time 620737300 ps
CPU time 61.48 seconds
Started Feb 21 01:09:15 PM PST 24
Finished Feb 21 01:10:19 PM PST 24
Peak memory 263576 kb
Host smart-540af5cd-3deb-4dd0-841b-33681e7a446d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146599228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.146599228
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.3756936582
Short name T742
Test name
Test status
Simulation time 25230700 ps
CPU time 75.36 seconds
Started Feb 21 01:09:17 PM PST 24
Finished Feb 21 01:10:33 PM PST 24
Peak memory 275072 kb
Host smart-39a2f344-b601-43b1-b70f-626b4818db4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756936582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.3756936582
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.2130950302
Short name T491
Test name
Test status
Simulation time 99046400 ps
CPU time 13.86 seconds
Started Feb 21 01:09:19 PM PST 24
Finished Feb 21 01:09:33 PM PST 24
Peak memory 264152 kb
Host smart-c96e5f7f-626e-46c4-abfc-15c2fbcaf548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130950302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
2130950302
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.3981637297
Short name T512
Test name
Test status
Simulation time 47887400 ps
CPU time 13.77 seconds
Started Feb 21 01:09:21 PM PST 24
Finished Feb 21 01:09:35 PM PST 24
Peak memory 274240 kb
Host smart-0f55b5d5-1112-41dc-9102-40d2189fced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981637297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.3981637297
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.1351413700
Short name T775
Test name
Test status
Simulation time 24168600 ps
CPU time 21.68 seconds
Started Feb 21 01:09:14 PM PST 24
Finished Feb 21 01:09:39 PM PST 24
Peak memory 272760 kb
Host smart-493d75f3-e389-4586-b15c-9dcf8524452f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351413700 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.1351413700
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3947983090
Short name T906
Test name
Test status
Simulation time 1845794100 ps
CPU time 56.12 seconds
Started Feb 21 01:09:09 PM PST 24
Finished Feb 21 01:10:06 PM PST 24
Peak memory 258372 kb
Host smart-b084aa8f-d094-4193-931f-9827c9a440b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947983090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.3947983090
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.1080808066
Short name T1061
Test name
Test status
Simulation time 3743049900 ps
CPU time 149.69 seconds
Started Feb 21 01:09:09 PM PST 24
Finished Feb 21 01:11:39 PM PST 24
Peak memory 293168 kb
Host smart-ccb01e3d-df84-4aa1-89b4-d1815e2141ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080808066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.1080808066
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.4230278670
Short name T747
Test name
Test status
Simulation time 16427723700 ps
CPU time 193.48 seconds
Started Feb 21 01:09:13 PM PST 24
Finished Feb 21 01:12:29 PM PST 24
Peak memory 283764 kb
Host smart-e58a9201-6197-4839-acd0-ca6b9b602314
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230278670 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.4230278670
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.2999303847
Short name T878
Test name
Test status
Simulation time 177193200 ps
CPU time 114.6 seconds
Started Feb 21 01:09:15 PM PST 24
Finished Feb 21 01:11:12 PM PST 24
Peak memory 258844 kb
Host smart-567144aa-c76f-44f6-8d56-77fcf25913da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999303847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.2999303847
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.740473163
Short name T621
Test name
Test status
Simulation time 118936400 ps
CPU time 14.35 seconds
Started Feb 21 01:09:08 PM PST 24
Finished Feb 21 01:09:23 PM PST 24
Peak memory 264416 kb
Host smart-04464aa6-6630-4f06-8a80-8fbd6e67a15f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740473163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_res
et.740473163
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.1754812068
Short name T345
Test name
Test status
Simulation time 62046500 ps
CPU time 30.62 seconds
Started Feb 21 01:09:16 PM PST 24
Finished Feb 21 01:09:48 PM PST 24
Peak memory 274816 kb
Host smart-f7d58cca-815b-4d68-b02c-dafee7960fe1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754812068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.1754812068
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.2898354778
Short name T810
Test name
Test status
Simulation time 37316700 ps
CPU time 28.87 seconds
Started Feb 21 01:09:11 PM PST 24
Finished Feb 21 01:09:40 PM PST 24
Peak memory 273836 kb
Host smart-96f588dc-77cf-4253-a688-c72a8e00b023
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898354778 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.2898354778
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.1827221515
Short name T584
Test name
Test status
Simulation time 2050020200 ps
CPU time 71.36 seconds
Started Feb 21 01:09:26 PM PST 24
Finished Feb 21 01:10:39 PM PST 24
Peak memory 264352 kb
Host smart-6e32189b-0b45-4977-a6c5-050c8daa7f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827221515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.1827221515
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.243092733
Short name T1103
Test name
Test status
Simulation time 48118900 ps
CPU time 124.16 seconds
Started Feb 21 01:09:11 PM PST 24
Finished Feb 21 01:11:16 PM PST 24
Peak memory 274620 kb
Host smart-54413e39-0a1c-44d3-b49f-4b8b1da46a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243092733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.243092733
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.313552107
Short name T876
Test name
Test status
Simulation time 52116000 ps
CPU time 13.74 seconds
Started Feb 21 01:04:13 PM PST 24
Finished Feb 21 01:04:27 PM PST 24
Peak memory 263552 kb
Host smart-064f19ae-c861-4f96-af7e-335daba85d09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313552107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.313552107
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.3825110236
Short name T529
Test name
Test status
Simulation time 76558000 ps
CPU time 13.75 seconds
Started Feb 21 01:04:13 PM PST 24
Finished Feb 21 01:04:27 PM PST 24
Peak memory 264372 kb
Host smart-8615a4c4-1254-46c2-858d-0676f5e620af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825110236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.3825110236
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.2567572197
Short name T905
Test name
Test status
Simulation time 14993800 ps
CPU time 16.05 seconds
Started Feb 21 01:04:20 PM PST 24
Finished Feb 21 01:04:37 PM PST 24
Peak memory 273848 kb
Host smart-6af40455-1632-4a2d-b47e-93c24f72fab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567572197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2567572197
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.3236192954
Short name T210
Test name
Test status
Simulation time 109822000 ps
CPU time 101.97 seconds
Started Feb 21 01:03:48 PM PST 24
Finished Feb 21 01:05:31 PM PST 24
Peak memory 272908 kb
Host smart-65c5b24e-4424-4bd6-b7df-d3d845afa9d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236192954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.3236192954
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.3578989266
Short name T726
Test name
Test status
Simulation time 105936000 ps
CPU time 21.71 seconds
Started Feb 21 01:04:17 PM PST 24
Finished Feb 21 01:04:39 PM PST 24
Peak memory 272744 kb
Host smart-59090594-1081-499f-82b0-d7073e80472d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578989266 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.3578989266
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.2542578417
Short name T24
Test name
Test status
Simulation time 2579507200 ps
CPU time 420.78 seconds
Started Feb 21 01:03:50 PM PST 24
Finished Feb 21 01:10:51 PM PST 24
Peak memory 260368 kb
Host smart-199008db-499b-489b-a56e-f65f4604ea1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542578417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2542578417
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.3759218223
Short name T654
Test name
Test status
Simulation time 5204453000 ps
CPU time 2451.27 seconds
Started Feb 21 01:03:47 PM PST 24
Finished Feb 21 01:44:40 PM PST 24
Peak memory 264456 kb
Host smart-ba7c7e8c-70b1-4e6d-8b90-c6cb77a63837
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759218223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.3759218223
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.663433062
Short name T826
Test name
Test status
Simulation time 748431200 ps
CPU time 2554.88 seconds
Started Feb 21 01:03:52 PM PST 24
Finished Feb 21 01:46:27 PM PST 24
Peak memory 263920 kb
Host smart-8c57e1fb-896c-486f-833d-69e03d6a00c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663433062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.663433062
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.3870904817
Short name T532
Test name
Test status
Simulation time 1060008300 ps
CPU time 792.58 seconds
Started Feb 21 01:03:52 PM PST 24
Finished Feb 21 01:17:05 PM PST 24
Peak memory 264400 kb
Host smart-2fcd50cb-ddbf-4b19-b5d1-d8fd2ab72f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870904817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3870904817
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.2886579626
Short name T38
Test name
Test status
Simulation time 692975500 ps
CPU time 26.06 seconds
Started Feb 21 01:03:50 PM PST 24
Finished Feb 21 01:04:17 PM PST 24
Peak memory 264456 kb
Host smart-13f471a9-8dcf-4df5-b379-30bc6c5b0997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886579626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.2886579626
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.2752061919
Short name T1063
Test name
Test status
Simulation time 279482400 ps
CPU time 34.42 seconds
Started Feb 21 01:04:13 PM PST 24
Finished Feb 21 01:04:48 PM PST 24
Peak memory 275464 kb
Host smart-7d685b3b-99b2-497f-9218-f14d3845622a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752061919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.2752061919
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.1200297233
Short name T773
Test name
Test status
Simulation time 159023338200 ps
CPU time 2464.51 seconds
Started Feb 21 01:03:49 PM PST 24
Finished Feb 21 01:44:54 PM PST 24
Peak memory 261388 kb
Host smart-ac2114d1-a451-4a49-a533-002af7e6abc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200297233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.1200297233
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.2264099701
Short name T285
Test name
Test status
Simulation time 63275700 ps
CPU time 113.44 seconds
Started Feb 21 01:03:35 PM PST 24
Finished Feb 21 01:05:29 PM PST 24
Peak memory 261548 kb
Host smart-d040c35d-5420-4349-bc80-f2ac899ccee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2264099701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2264099701
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.988246917
Short name T294
Test name
Test status
Simulation time 16176200 ps
CPU time 13.64 seconds
Started Feb 21 01:04:13 PM PST 24
Finished Feb 21 01:04:26 PM PST 24
Peak memory 264408 kb
Host smart-bca69b25-6a55-4dff-b2f4-8d548c5e368d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988246917 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.988246917
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.407174765
Short name T146
Test name
Test status
Simulation time 60130412600 ps
CPU time 725.52 seconds
Started Feb 21 01:03:50 PM PST 24
Finished Feb 21 01:15:56 PM PST 24
Peak memory 262216 kb
Host smart-6bb5e3bc-f26c-4173-92e0-f925cd100026
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407174765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_hw_rma_reset.407174765
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.2228756550
Short name T909
Test name
Test status
Simulation time 3300469200 ps
CPU time 104.85 seconds
Started Feb 21 01:03:48 PM PST 24
Finished Feb 21 01:05:34 PM PST 24
Peak memory 258372 kb
Host smart-ea35e8ea-be65-4c0d-80b2-69490d3bbb1f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228756550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.2228756550
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.2431596
Short name T278
Test name
Test status
Simulation time 8567086500 ps
CPU time 568.5 seconds
Started Feb 21 01:03:56 PM PST 24
Finished Feb 21 01:13:25 PM PST 24
Peak memory 314044 kb
Host smart-2347bde4-35aa-47c2-86fb-ec5562f4e394
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431596 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_integrity.2431596
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.3235284925
Short name T1097
Test name
Test status
Simulation time 1159355700 ps
CPU time 137.19 seconds
Started Feb 21 01:04:12 PM PST 24
Finished Feb 21 01:06:30 PM PST 24
Peak memory 293740 kb
Host smart-0b1580fd-a5b0-49be-997d-8d698b31ac16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235284925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.3235284925
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.2240601759
Short name T505
Test name
Test status
Simulation time 8817386400 ps
CPU time 230.98 seconds
Started Feb 21 01:04:13 PM PST 24
Finished Feb 21 01:08:04 PM PST 24
Peak memory 284252 kb
Host smart-fcda7794-905b-4a8c-97d1-6c9d1a8be25c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240601759 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.2240601759
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.2638478896
Short name T830
Test name
Test status
Simulation time 208454891400 ps
CPU time 410.53 seconds
Started Feb 21 01:04:12 PM PST 24
Finished Feb 21 01:11:03 PM PST 24
Peak memory 264416 kb
Host smart-6013b698-776a-4948-ac5a-597944ba9a4b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263
8478896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.2638478896
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.3725159433
Short name T1069
Test name
Test status
Simulation time 1905513300 ps
CPU time 56.15 seconds
Started Feb 21 01:03:52 PM PST 24
Finished Feb 21 01:04:48 PM PST 24
Peak memory 259520 kb
Host smart-300e919e-6d86-4100-b3aa-02267d6f3ab9
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725159433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.3725159433
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.4184567881
Short name T300
Test name
Test status
Simulation time 46222400 ps
CPU time 13.49 seconds
Started Feb 21 01:04:17 PM PST 24
Finished Feb 21 01:04:31 PM PST 24
Peak memory 264420 kb
Host smart-3211f5b5-c800-4025-8e63-a0e4a232a0ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184567881 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.4184567881
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.3156623922
Short name T58
Test name
Test status
Simulation time 956301600 ps
CPU time 72.58 seconds
Started Feb 21 01:03:52 PM PST 24
Finished Feb 21 01:05:05 PM PST 24
Peak memory 258904 kb
Host smart-8fa45f56-d826-4792-9297-cd04cf31184e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156623922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.3156623922
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.1152315325
Short name T806
Test name
Test status
Simulation time 3709336100 ps
CPU time 146.56 seconds
Started Feb 21 01:03:51 PM PST 24
Finished Feb 21 01:06:18 PM PST 24
Peak memory 264448 kb
Host smart-b3f74cd0-7b40-4617-8322-270133b1b575
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152315325 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.1152315325
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.60490096
Short name T903
Test name
Test status
Simulation time 44031500 ps
CPU time 135.38 seconds
Started Feb 21 01:03:49 PM PST 24
Finished Feb 21 01:06:05 PM PST 24
Peak memory 259048 kb
Host smart-43fa08d2-26e4-4f1c-8dd8-f1eb94927046
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60490096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_
reset.60490096
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.549331005
Short name T610
Test name
Test status
Simulation time 7735408000 ps
CPU time 164.28 seconds
Started Feb 21 01:03:51 PM PST 24
Finished Feb 21 01:06:36 PM PST 24
Peak memory 281072 kb
Host smart-d14ef710-793c-4dbe-a04a-329351e355ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549331005 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.549331005
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.240897585
Short name T92
Test name
Test status
Simulation time 55769100 ps
CPU time 13.56 seconds
Started Feb 21 01:04:11 PM PST 24
Finished Feb 21 01:04:25 PM PST 24
Peak memory 277580 kb
Host smart-ede8539d-0306-4961-9f91-39ed7a31232b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=240897585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.240897585
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.147553298
Short name T497
Test name
Test status
Simulation time 1482111700 ps
CPU time 336.71 seconds
Started Feb 21 01:03:53 PM PST 24
Finished Feb 21 01:09:30 PM PST 24
Peak memory 264492 kb
Host smart-0a09f525-936d-4e2d-99e5-eaa139046967
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=147553298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.147553298
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.3732119684
Short name T1055
Test name
Test status
Simulation time 854348200 ps
CPU time 45.36 seconds
Started Feb 21 01:04:11 PM PST 24
Finished Feb 21 01:04:57 PM PST 24
Peak memory 264608 kb
Host smart-ca7b96fd-5706-408a-88d0-b72fd3072715
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732119684 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3732119684
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.3675753792
Short name T779
Test name
Test status
Simulation time 19746800 ps
CPU time 13.47 seconds
Started Feb 21 01:04:19 PM PST 24
Finished Feb 21 01:04:33 PM PST 24
Peak memory 264404 kb
Host smart-42bb8ffa-4f89-46ac-8f6f-67ebf4ad2d1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675753792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.3675753792
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.508293874
Short name T274
Test name
Test status
Simulation time 158226300 ps
CPU time 79.38 seconds
Started Feb 21 01:03:50 PM PST 24
Finished Feb 21 01:05:10 PM PST 24
Peak memory 267992 kb
Host smart-b0eec915-313f-43cc-bad6-f648471fcf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508293874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.508293874
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.3555418867
Short name T650
Test name
Test status
Simulation time 107523300 ps
CPU time 103.25 seconds
Started Feb 21 01:03:50 PM PST 24
Finished Feb 21 01:05:33 PM PST 24
Peak memory 264176 kb
Host smart-2ec172bf-b402-4feb-a4bb-9e27edcad4a1
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3555418867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.3555418867
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.3633125180
Short name T73
Test name
Test status
Simulation time 77482400 ps
CPU time 32.78 seconds
Started Feb 21 01:04:14 PM PST 24
Finished Feb 21 01:04:47 PM PST 24
Peak memory 273828 kb
Host smart-859c08ae-c579-4a38-b61e-bc159ba99e4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633125180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.3633125180
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.2768365036
Short name T598
Test name
Test status
Simulation time 92678900 ps
CPU time 21.29 seconds
Started Feb 21 01:03:51 PM PST 24
Finished Feb 21 01:04:12 PM PST 24
Peak memory 264556 kb
Host smart-622b341e-8c83-4416-9f81-70e4dcf25ff3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768365036 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.2768365036
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.3452792656
Short name T772
Test name
Test status
Simulation time 41508500 ps
CPU time 22.63 seconds
Started Feb 21 01:03:52 PM PST 24
Finished Feb 21 01:04:15 PM PST 24
Peak memory 264568 kb
Host smart-521c6d06-0d05-4347-a1c9-c9b93bc4406b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452792656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.3452792656
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.511961442
Short name T679
Test name
Test status
Simulation time 859607700 ps
CPU time 118.1 seconds
Started Feb 21 01:03:50 PM PST 24
Finished Feb 21 01:05:49 PM PST 24
Peak memory 281004 kb
Host smart-056ed348-994f-4501-8474-0e40a07f9b68
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511961442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_ro.511961442
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.2928034645
Short name T198
Test name
Test status
Simulation time 1521905600 ps
CPU time 179.18 seconds
Started Feb 21 01:03:59 PM PST 24
Finished Feb 21 01:06:58 PM PST 24
Peak memory 281436 kb
Host smart-927cf1f3-2427-4559-a2d0-eb6560760795
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2928034645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2928034645
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.1828514885
Short name T561
Test name
Test status
Simulation time 1357373200 ps
CPU time 128.47 seconds
Started Feb 21 01:03:50 PM PST 24
Finished Feb 21 01:05:59 PM PST 24
Peak memory 295648 kb
Host smart-45933ca3-7dfe-41e9-b4f4-43fb7c2573b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828514885 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.1828514885
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.1046990120
Short name T944
Test name
Test status
Simulation time 6529688800 ps
CPU time 440.33 seconds
Started Feb 21 01:03:50 PM PST 24
Finished Feb 21 01:11:11 PM PST 24
Peak memory 313700 kb
Host smart-ba6a1a16-e3f2-47f1-a3fc-77d73915a685
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046990120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_rw.1046990120
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.583369756
Short name T915
Test name
Test status
Simulation time 67502945700 ps
CPU time 598.58 seconds
Started Feb 21 01:03:49 PM PST 24
Finished Feb 21 01:13:48 PM PST 24
Peak memory 332948 kb
Host smart-63ed421a-3f4a-44b2-8934-ac875b0f21a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583369756 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.flash_ctrl_rw_derr.583369756
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.1684863125
Short name T1005
Test name
Test status
Simulation time 211575200 ps
CPU time 31.54 seconds
Started Feb 21 01:04:12 PM PST 24
Finished Feb 21 01:04:44 PM PST 24
Peak memory 277232 kb
Host smart-85d4d522-7b85-4ddc-b149-f637a8c9caec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684863125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.1684863125
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.3344502356
Short name T755
Test name
Test status
Simulation time 39367900 ps
CPU time 31.03 seconds
Started Feb 21 01:04:20 PM PST 24
Finished Feb 21 01:04:52 PM PST 24
Peak memory 273808 kb
Host smart-09b94268-0694-4283-ba49-78941e70220c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344502356 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.3344502356
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.293185467
Short name T459
Test name
Test status
Simulation time 14198999000 ps
CPU time 557.45 seconds
Started Feb 21 01:03:48 PM PST 24
Finished Feb 21 01:13:07 PM PST 24
Peak memory 311140 kb
Host smart-aabe6b99-e2c6-41de-b52f-a070d463bf94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293185467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_se
rr.293185467
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.2814689670
Short name T13
Test name
Test status
Simulation time 5334048500 ps
CPU time 4673.84 seconds
Started Feb 21 01:04:18 PM PST 24
Finished Feb 21 02:22:13 PM PST 24
Peak memory 285892 kb
Host smart-6bf1ea05-4733-4356-a446-3fb42f1d219b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814689670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.2814689670
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.1867734691
Short name T644
Test name
Test status
Simulation time 2435176600 ps
CPU time 62.15 seconds
Started Feb 21 01:04:13 PM PST 24
Finished Feb 21 01:05:16 PM PST 24
Peak memory 264288 kb
Host smart-3011cbe8-7315-49df-b866-db47c6c13164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867734691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1867734691
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.1333216208
Short name T1096
Test name
Test status
Simulation time 519717400 ps
CPU time 61.68 seconds
Started Feb 21 01:03:55 PM PST 24
Finished Feb 21 01:04:57 PM PST 24
Peak memory 264604 kb
Host smart-aa1420f2-7e13-4c5e-91da-4449de6290f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333216208 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.1333216208
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.974949784
Short name T706
Test name
Test status
Simulation time 2326618400 ps
CPU time 62.78 seconds
Started Feb 21 01:03:55 PM PST 24
Finished Feb 21 01:04:58 PM PST 24
Peak memory 272824 kb
Host smart-c8d72b88-1f0d-4e10-8a16-89b6d656f6d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974949784 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_counter.974949784
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.140856472
Short name T1100
Test name
Test status
Simulation time 135454000 ps
CPU time 50.33 seconds
Started Feb 21 01:03:49 PM PST 24
Finished Feb 21 01:04:40 PM PST 24
Peak memory 269764 kb
Host smart-8e04075a-17fb-45e0-8c98-a3e945157c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140856472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.140856472
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.3052242720
Short name T639
Test name
Test status
Simulation time 112724500 ps
CPU time 26.46 seconds
Started Feb 21 01:03:39 PM PST 24
Finished Feb 21 01:04:06 PM PST 24
Peak memory 258228 kb
Host smart-9df65156-acfe-467d-bae6-4cf9aba969af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052242720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3052242720
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.393272894
Short name T638
Test name
Test status
Simulation time 992920800 ps
CPU time 1248.72 seconds
Started Feb 21 01:04:14 PM PST 24
Finished Feb 21 01:25:03 PM PST 24
Peak memory 287684 kb
Host smart-db982fe9-fd14-4398-b810-7749816b4907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393272894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress
_all.393272894
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.3987108845
Short name T534
Test name
Test status
Simulation time 23213700 ps
CPU time 26.14 seconds
Started Feb 21 01:03:32 PM PST 24
Finished Feb 21 01:03:59 PM PST 24
Peak memory 258156 kb
Host smart-c511113c-f63e-407b-8b1f-da3c556bf878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987108845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3987108845
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.292713334
Short name T452
Test name
Test status
Simulation time 3957424300 ps
CPU time 131.66 seconds
Started Feb 21 01:03:47 PM PST 24
Finished Feb 21 01:06:00 PM PST 24
Peak memory 264388 kb
Host smart-e8102c7b-9199-4a36-9995-c6b0a0578497
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292713334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_wo.292713334
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.1319516652
Short name T33
Test name
Test status
Simulation time 228970000 ps
CPU time 13.85 seconds
Started Feb 21 01:09:23 PM PST 24
Finished Feb 21 01:09:37 PM PST 24
Peak memory 264096 kb
Host smart-e00c9a36-7474-49e1-b187-3021e4295b74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319516652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
1319516652
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.1504454166
Short name T507
Test name
Test status
Simulation time 16704800 ps
CPU time 13.33 seconds
Started Feb 21 01:09:22 PM PST 24
Finished Feb 21 01:09:36 PM PST 24
Peak memory 273876 kb
Host smart-03aec0aa-e39c-4cd1-895f-c15839d2615f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504454166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.1504454166
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.1988773950
Short name T802
Test name
Test status
Simulation time 11110100 ps
CPU time 21.64 seconds
Started Feb 21 01:09:21 PM PST 24
Finished Feb 21 01:09:43 PM PST 24
Peak memory 264472 kb
Host smart-9747b96c-5ca1-4def-aaa0-e61e4d25135c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988773950 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.1988773950
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.654945406
Short name T431
Test name
Test status
Simulation time 4463149500 ps
CPU time 178.04 seconds
Started Feb 21 01:09:21 PM PST 24
Finished Feb 21 01:12:20 PM PST 24
Peak memory 260836 kb
Host smart-efce3368-3eea-4694-ac97-deec106a4d32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654945406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_h
w_sec_otp.654945406
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.4216588972
Short name T1025
Test name
Test status
Simulation time 6216079800 ps
CPU time 163.89 seconds
Started Feb 21 01:09:23 PM PST 24
Finished Feb 21 01:12:09 PM PST 24
Peak memory 293260 kb
Host smart-a14b6cb7-e43e-495b-9efd-3c6665010727
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216588972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.4216588972
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3799095594
Short name T914
Test name
Test status
Simulation time 8945834600 ps
CPU time 208.76 seconds
Started Feb 21 01:09:23 PM PST 24
Finished Feb 21 01:12:54 PM PST 24
Peak memory 283728 kb
Host smart-5407a790-c875-489f-8ff7-a93d62b25d54
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799095594 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.3799095594
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.580328044
Short name T640
Test name
Test status
Simulation time 325182600 ps
CPU time 132.97 seconds
Started Feb 21 01:09:21 PM PST 24
Finished Feb 21 01:11:35 PM PST 24
Peak memory 258964 kb
Host smart-716bd9b1-04af-4469-b971-e8858ffc2f89
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580328044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_ot
p_reset.580328044
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.113309798
Short name T1092
Test name
Test status
Simulation time 62307900 ps
CPU time 31.9 seconds
Started Feb 21 01:09:23 PM PST 24
Finished Feb 21 01:09:57 PM PST 24
Peak memory 273864 kb
Host smart-304b54f6-2009-4985-999b-949cbd43acdd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113309798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_rw_evict.113309798
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.1115724290
Short name T269
Test name
Test status
Simulation time 96980000 ps
CPU time 33.51 seconds
Started Feb 21 01:09:19 PM PST 24
Finished Feb 21 01:09:52 PM PST 24
Peak memory 272828 kb
Host smart-3f7e033b-21bc-4cd4-a695-a8823348d401
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115724290 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.1115724290
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.4211890097
Short name T1124
Test name
Test status
Simulation time 1970920600 ps
CPU time 69.9 seconds
Started Feb 21 01:09:21 PM PST 24
Finished Feb 21 01:10:32 PM PST 24
Peak memory 264344 kb
Host smart-c1e521ab-c834-4f2c-b808-b522cbd3207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211890097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.4211890097
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.4180696818
Short name T218
Test name
Test status
Simulation time 101555600 ps
CPU time 100.02 seconds
Started Feb 21 01:09:17 PM PST 24
Finished Feb 21 01:10:58 PM PST 24
Peak memory 275720 kb
Host smart-0847d217-8ad9-41ff-9b17-276a125bf18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180696818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.4180696818
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.2147038114
Short name T664
Test name
Test status
Simulation time 72044500 ps
CPU time 14.26 seconds
Started Feb 21 01:09:22 PM PST 24
Finished Feb 21 01:09:37 PM PST 24
Peak memory 264340 kb
Host smart-1d500921-eb1c-4bdd-9b48-db088a86562b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147038114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
2147038114
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.2355974030
Short name T737
Test name
Test status
Simulation time 52086100 ps
CPU time 13.28 seconds
Started Feb 21 01:09:22 PM PST 24
Finished Feb 21 01:09:36 PM PST 24
Peak memory 273820 kb
Host smart-3f935c85-6cd3-41a4-9949-f1b9ec0d3652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355974030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.2355974030
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.1036957768
Short name T1033
Test name
Test status
Simulation time 10990200 ps
CPU time 21.71 seconds
Started Feb 21 01:09:21 PM PST 24
Finished Feb 21 01:09:43 PM PST 24
Peak memory 279612 kb
Host smart-7b2e1985-970b-495d-947d-46016bc3c11d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036957768 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.1036957768
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.2518981134
Short name T44
Test name
Test status
Simulation time 3599469000 ps
CPU time 130.59 seconds
Started Feb 21 01:09:23 PM PST 24
Finished Feb 21 01:11:35 PM PST 24
Peak memory 261548 kb
Host smart-4ada1680-85a7-4edf-b11d-1c131624c80b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518981134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.2518981134
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.1480761413
Short name T417
Test name
Test status
Simulation time 15579705800 ps
CPU time 207.86 seconds
Started Feb 21 01:09:19 PM PST 24
Finished Feb 21 01:12:47 PM PST 24
Peak memory 289132 kb
Host smart-7c62c788-08b6-4a51-a9bc-a11194dd9444
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480761413 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.1480761413
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.2841144786
Short name T570
Test name
Test status
Simulation time 131825500 ps
CPU time 114.71 seconds
Started Feb 21 01:09:23 PM PST 24
Finished Feb 21 01:11:20 PM PST 24
Peak memory 258620 kb
Host smart-86380729-1bcf-44e1-9cc2-37591c0ece4a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841144786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.2841144786
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.1598036478
Short name T769
Test name
Test status
Simulation time 217051900 ps
CPU time 32.56 seconds
Started Feb 21 01:09:17 PM PST 24
Finished Feb 21 01:09:50 PM PST 24
Peak memory 273840 kb
Host smart-606bc333-cf1e-4071-b221-e4624847d1c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598036478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.1598036478
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.1957665159
Short name T479
Test name
Test status
Simulation time 383140200 ps
CPU time 38.04 seconds
Started Feb 21 01:09:21 PM PST 24
Finished Feb 21 01:09:59 PM PST 24
Peak memory 265600 kb
Host smart-7f2e0e67-696a-42ae-b606-4058b4ee9a0f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957665159 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.1957665159
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.3926610396
Short name T821
Test name
Test status
Simulation time 1794049900 ps
CPU time 66.38 seconds
Started Feb 21 01:09:23 PM PST 24
Finished Feb 21 01:10:31 PM PST 24
Peak memory 263308 kb
Host smart-fbe3375c-7388-47d9-885b-95336fb6a5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926610396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3926610396
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.1306456183
Short name T736
Test name
Test status
Simulation time 48275200 ps
CPU time 124.26 seconds
Started Feb 21 01:09:21 PM PST 24
Finished Feb 21 01:11:25 PM PST 24
Peak memory 274504 kb
Host smart-65e32dc6-837d-4d80-bc9b-3866d77e2063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306456183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1306456183
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.3994099735
Short name T319
Test name
Test status
Simulation time 48257300 ps
CPU time 14.01 seconds
Started Feb 21 01:09:21 PM PST 24
Finished Feb 21 01:09:36 PM PST 24
Peak memory 264028 kb
Host smart-dd90b3cf-d709-43e7-bbd9-8ddebdb843e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994099735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
3994099735
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.3144047123
Short name T164
Test name
Test status
Simulation time 9934300 ps
CPU time 21.78 seconds
Started Feb 21 01:09:22 PM PST 24
Finished Feb 21 01:09:44 PM PST 24
Peak memory 279776 kb
Host smart-01fa9d1a-8c9e-46d8-9cab-1a18e3ed723c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144047123 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.3144047123
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.4282985804
Short name T957
Test name
Test status
Simulation time 2340642900 ps
CPU time 85.47 seconds
Started Feb 21 01:09:23 PM PST 24
Finished Feb 21 01:10:51 PM PST 24
Peak memory 261472 kb
Host smart-0a0c7926-0c72-441e-bc0a-70eaea933c34
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282985804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.4282985804
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.3969540138
Short name T448
Test name
Test status
Simulation time 4392796500 ps
CPU time 169.03 seconds
Started Feb 21 01:09:20 PM PST 24
Finished Feb 21 01:12:10 PM PST 24
Peak memory 292208 kb
Host smart-d17e9589-dc4d-44f5-a436-b6c3f2f0e10c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969540138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.3969540138
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.3023174609
Short name T113
Test name
Test status
Simulation time 8211946600 ps
CPU time 199.56 seconds
Started Feb 21 01:09:23 PM PST 24
Finished Feb 21 01:12:43 PM PST 24
Peak memory 284012 kb
Host smart-e2b0a8f8-94fd-4ac9-b41a-9a9e431b3f76
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023174609 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.3023174609
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.1371517609
Short name T714
Test name
Test status
Simulation time 163081900 ps
CPU time 131.91 seconds
Started Feb 21 01:09:21 PM PST 24
Finished Feb 21 01:11:33 PM PST 24
Peak memory 258700 kb
Host smart-022e04f8-2c40-4dbc-bd21-e245887dbdc5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371517609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.1371517609
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.2688540038
Short name T1073
Test name
Test status
Simulation time 124153400 ps
CPU time 32.11 seconds
Started Feb 21 01:09:21 PM PST 24
Finished Feb 21 01:09:53 PM PST 24
Peak memory 272804 kb
Host smart-2819d03e-0f35-46b6-9276-a1157a3f29a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688540038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.2688540038
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.585273432
Short name T1034
Test name
Test status
Simulation time 759716500 ps
CPU time 35.95 seconds
Started Feb 21 01:09:26 PM PST 24
Finished Feb 21 01:10:04 PM PST 24
Peak memory 277228 kb
Host smart-08b7f351-30f4-49c2-94ba-de1fe73b0a89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585273432 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.585273432
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.1267530210
Short name T635
Test name
Test status
Simulation time 7478316400 ps
CPU time 73.15 seconds
Started Feb 21 01:09:20 PM PST 24
Finished Feb 21 01:10:33 PM PST 24
Peak memory 263556 kb
Host smart-7a049def-58ce-4cd6-9898-30ed8f3585b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267530210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.1267530210
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.2925674868
Short name T25
Test name
Test status
Simulation time 43961000 ps
CPU time 77.41 seconds
Started Feb 21 01:09:20 PM PST 24
Finished Feb 21 01:10:37 PM PST 24
Peak memory 275400 kb
Host smart-2e90014b-7962-40e4-a64d-94fc64f91160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925674868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.2925674868
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.197693330
Short name T723
Test name
Test status
Simulation time 165863300 ps
CPU time 13.63 seconds
Started Feb 21 01:09:35 PM PST 24
Finished Feb 21 01:09:49 PM PST 24
Peak memory 263924 kb
Host smart-6b3a070d-7c74-4323-91e7-49f411654693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197693330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.197693330
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.2550094987
Short name T950
Test name
Test status
Simulation time 24478400 ps
CPU time 15.52 seconds
Started Feb 21 01:09:38 PM PST 24
Finished Feb 21 01:09:54 PM PST 24
Peak memory 274136 kb
Host smart-ec943b6a-4a82-4a7c-9235-6a9262f58198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550094987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2550094987
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.3915246501
Short name T97
Test name
Test status
Simulation time 15465800 ps
CPU time 21.92 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:09:56 PM PST 24
Peak memory 264736 kb
Host smart-c1000bd2-7b8e-4fef-923a-f54660961c17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915246501 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.3915246501
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.4294173504
Short name T596
Test name
Test status
Simulation time 15280477400 ps
CPU time 52.6 seconds
Started Feb 21 01:09:20 PM PST 24
Finished Feb 21 01:10:13 PM PST 24
Peak memory 258376 kb
Host smart-2d7bf56e-a9a2-4420-ae17-d939eaf67933
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294173504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.4294173504
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.1517468714
Short name T600
Test name
Test status
Simulation time 5210617200 ps
CPU time 165.44 seconds
Started Feb 21 01:09:24 PM PST 24
Finished Feb 21 01:12:11 PM PST 24
Peak memory 291780 kb
Host smart-f97a21ec-e563-4efe-8538-2428bca62242
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517468714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.1517468714
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.837779429
Short name T612
Test name
Test status
Simulation time 17678023400 ps
CPU time 194.54 seconds
Started Feb 21 01:09:23 PM PST 24
Finished Feb 21 01:12:40 PM PST 24
Peak memory 283860 kb
Host smart-307c817d-f81e-40d3-b9e0-596e1c54a6ec
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837779429 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.837779429
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.2775714314
Short name T1133
Test name
Test status
Simulation time 33221500 ps
CPU time 131.51 seconds
Started Feb 21 01:09:27 PM PST 24
Finished Feb 21 01:11:39 PM PST 24
Peak memory 263096 kb
Host smart-76268db4-a281-458e-9aa6-28779020af0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775714314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.2775714314
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.763105770
Short name T74
Test name
Test status
Simulation time 48311000 ps
CPU time 33.01 seconds
Started Feb 21 01:09:35 PM PST 24
Finished Feb 21 01:10:08 PM PST 24
Peak memory 272816 kb
Host smart-edbc097a-fb26-47b9-9faf-6304eb72c750
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763105770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_rw_evict.763105770
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.3832370807
Short name T403
Test name
Test status
Simulation time 3756840400 ps
CPU time 75.93 seconds
Started Feb 21 01:09:38 PM PST 24
Finished Feb 21 01:10:54 PM PST 24
Peak memory 258760 kb
Host smart-3fefb703-f943-49b1-b47a-035661ea3e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832370807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.3832370807
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.1683399104
Short name T495
Test name
Test status
Simulation time 27769900 ps
CPU time 121.15 seconds
Started Feb 21 01:09:20 PM PST 24
Finished Feb 21 01:11:21 PM PST 24
Peak memory 274540 kb
Host smart-5b79bc1e-75cc-4df9-a62d-f364aead45e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683399104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.1683399104
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.3446475669
Short name T976
Test name
Test status
Simulation time 27458100 ps
CPU time 15.81 seconds
Started Feb 21 01:09:32 PM PST 24
Finished Feb 21 01:09:49 PM PST 24
Peak memory 274004 kb
Host smart-5a319dd8-cee2-4cc8-aac0-0a8518139723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446475669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3446475669
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.1630002124
Short name T165
Test name
Test status
Simulation time 10113200 ps
CPU time 21.54 seconds
Started Feb 21 01:09:36 PM PST 24
Finished Feb 21 01:09:58 PM PST 24
Peak memory 272696 kb
Host smart-978fd99a-19ce-412b-b5dd-47bac66cb1b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630002124 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.1630002124
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3696397699
Short name T541
Test name
Test status
Simulation time 8674862500 ps
CPU time 86.89 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:11:01 PM PST 24
Peak memory 258400 kb
Host smart-bd2fbc13-fe89-4744-b82f-fc9c0644b6fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696397699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.3696397699
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.1642724454
Short name T852
Test name
Test status
Simulation time 2713209900 ps
CPU time 166.56 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:12:21 PM PST 24
Peak memory 291780 kb
Host smart-3c1141bb-4f1e-4163-ae6b-f0597cbd9eb6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642724454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.1642724454
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3941184485
Short name T418
Test name
Test status
Simulation time 8710431500 ps
CPU time 184.5 seconds
Started Feb 21 01:09:32 PM PST 24
Finished Feb 21 01:12:37 PM PST 24
Peak memory 283836 kb
Host smart-e8a78918-8ef1-4142-94bd-da077e80bc99
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941184485 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.3941184485
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.2288224987
Short name T166
Test name
Test status
Simulation time 203756300 ps
CPU time 134.39 seconds
Started Feb 21 01:09:34 PM PST 24
Finished Feb 21 01:11:48 PM PST 24
Peak memory 260176 kb
Host smart-ac07a410-f1fa-40b2-8a66-38d92520cd80
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288224987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.2288224987
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.1216134408
Short name T208
Test name
Test status
Simulation time 47010900 ps
CPU time 29.36 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:10:03 PM PST 24
Peak memory 273852 kb
Host smart-facf60dc-b932-41cb-b3ff-678b79e168e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216134408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.1216134408
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2682329278
Short name T712
Test name
Test status
Simulation time 35859500 ps
CPU time 31.91 seconds
Started Feb 21 01:09:32 PM PST 24
Finished Feb 21 01:10:04 PM PST 24
Peak memory 273836 kb
Host smart-6f5a6c0d-82bb-4cb6-9111-809316e4fe7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682329278 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2682329278
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.1629191782
Short name T316
Test name
Test status
Simulation time 90493900 ps
CPU time 74.94 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:10:49 PM PST 24
Peak memory 273888 kb
Host smart-33ae060b-627e-49d1-856e-573afacbed28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629191782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1629191782
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.2504888589
Short name T657
Test name
Test status
Simulation time 37280400 ps
CPU time 13.71 seconds
Started Feb 21 01:09:35 PM PST 24
Finished Feb 21 01:09:49 PM PST 24
Peak memory 264452 kb
Host smart-0b80d418-fe08-413f-8272-d84860bc4f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504888589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
2504888589
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.1649257887
Short name T690
Test name
Test status
Simulation time 66145900 ps
CPU time 15.58 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:09:50 PM PST 24
Peak memory 274828 kb
Host smart-03c52f98-2f96-4f1a-8600-b8896b8b349e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649257887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.1649257887
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.2581723046
Short name T516
Test name
Test status
Simulation time 10941800 ps
CPU time 21.57 seconds
Started Feb 21 01:09:32 PM PST 24
Finished Feb 21 01:09:54 PM PST 24
Peak memory 279864 kb
Host smart-11fe297a-1322-4819-b733-afbc49092ec0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581723046 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.2581723046
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.789014925
Short name T327
Test name
Test status
Simulation time 6503936500 ps
CPU time 106.27 seconds
Started Feb 21 01:09:34 PM PST 24
Finished Feb 21 01:11:21 PM PST 24
Peak memory 261184 kb
Host smart-e446bf0e-7908-4843-b15e-64cda0b15a94
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789014925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_h
w_sec_otp.789014925
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.1102129893
Short name T550
Test name
Test status
Simulation time 4092617300 ps
CPU time 146.26 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:12:00 PM PST 24
Peak memory 284000 kb
Host smart-68fb2b62-bedd-4469-83e1-1ab18c675701
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102129893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.1102129893
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.254489824
Short name T938
Test name
Test status
Simulation time 17913065200 ps
CPU time 216.5 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:13:11 PM PST 24
Peak memory 284024 kb
Host smart-9eff2175-9cb6-4c9f-8549-1712e71f9d8a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254489824 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.254489824
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.4187711445
Short name T63
Test name
Test status
Simulation time 117922600 ps
CPU time 112.87 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:11:27 PM PST 24
Peak memory 258928 kb
Host smart-55b61580-4463-42be-81e8-cb0ab65c9898
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187711445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.4187711445
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.3944772705
Short name T120
Test name
Test status
Simulation time 310933900 ps
CPU time 33.67 seconds
Started Feb 21 01:09:32 PM PST 24
Finished Feb 21 01:10:07 PM PST 24
Peak memory 272808 kb
Host smart-fdcb9086-1fd4-4b7e-a9f2-ce08801a3edd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944772705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.3944772705
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.3114534179
Short name T698
Test name
Test status
Simulation time 31238600 ps
CPU time 31.04 seconds
Started Feb 21 01:09:35 PM PST 24
Finished Feb 21 01:10:06 PM PST 24
Peak memory 274880 kb
Host smart-6b133fc4-7027-45e5-87f4-deba4abbb6a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114534179 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.3114534179
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.1285016636
Short name T794
Test name
Test status
Simulation time 9700487000 ps
CPU time 210.72 seconds
Started Feb 21 01:09:35 PM PST 24
Finished Feb 21 01:13:06 PM PST 24
Peak memory 280672 kb
Host smart-cd5a505f-912c-4ada-af3f-df5e5793cda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285016636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1285016636
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.732949429
Short name T1074
Test name
Test status
Simulation time 87384300 ps
CPU time 14.52 seconds
Started Feb 21 01:09:47 PM PST 24
Finished Feb 21 01:10:02 PM PST 24
Peak memory 263200 kb
Host smart-6b1b105c-69f9-4795-8782-00a8d28d3af9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732949429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.732949429
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.3908491356
Short name T1083
Test name
Test status
Simulation time 15001000 ps
CPU time 16.05 seconds
Started Feb 21 01:09:45 PM PST 24
Finished Feb 21 01:10:02 PM PST 24
Peak memory 274804 kb
Host smart-071cd344-06e5-44e8-8eab-6548f5524514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908491356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3908491356
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1068012983
Short name T515
Test name
Test status
Simulation time 21012382000 ps
CPU time 61.65 seconds
Started Feb 21 01:09:36 PM PST 24
Finished Feb 21 01:10:38 PM PST 24
Peak memory 258316 kb
Host smart-7c5fd0ac-e6d5-4128-bf46-f57e803d4e6e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068012983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.1068012983
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.889579157
Short name T890
Test name
Test status
Simulation time 9098898100 ps
CPU time 204.23 seconds
Started Feb 21 01:09:45 PM PST 24
Finished Feb 21 01:13:10 PM PST 24
Peak memory 283784 kb
Host smart-89126e33-04b6-402c-8d66-db9a03b8c811
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889579157 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.889579157
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.3429691166
Short name T1128
Test name
Test status
Simulation time 73312700 ps
CPU time 112.82 seconds
Started Feb 21 01:09:35 PM PST 24
Finished Feb 21 01:11:28 PM PST 24
Peak memory 259004 kb
Host smart-331820bc-2a83-4579-9b6f-f6e2e4840271
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429691166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.3429691166
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2859781302
Short name T138
Test name
Test status
Simulation time 107708400 ps
CPU time 31.18 seconds
Started Feb 21 01:09:45 PM PST 24
Finished Feb 21 01:10:17 PM PST 24
Peak memory 275932 kb
Host smart-27700f27-2202-4f38-b7e4-9e3e9920306e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859781302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2859781302
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.479223665
Short name T678
Test name
Test status
Simulation time 107847500 ps
CPU time 30.73 seconds
Started Feb 21 01:09:52 PM PST 24
Finished Feb 21 01:10:23 PM PST 24
Peak memory 272792 kb
Host smart-4aa5b8d3-6ce1-40af-9266-75362274ac3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479223665 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.479223665
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.3910570032
Short name T893
Test name
Test status
Simulation time 17411089100 ps
CPU time 80.41 seconds
Started Feb 21 01:09:53 PM PST 24
Finished Feb 21 01:11:15 PM PST 24
Peak memory 263348 kb
Host smart-2b17861f-b97d-4121-9462-4f1021e346c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910570032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.3910570032
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.2286150684
Short name T1062
Test name
Test status
Simulation time 23477400 ps
CPU time 98.83 seconds
Started Feb 21 01:09:33 PM PST 24
Finished Feb 21 01:11:13 PM PST 24
Peak memory 274268 kb
Host smart-c7893dae-ea1e-4571-919d-6c251bc586ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286150684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2286150684
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.2111710874
Short name T685
Test name
Test status
Simulation time 50126800 ps
CPU time 13.27 seconds
Started Feb 21 01:09:46 PM PST 24
Finished Feb 21 01:10:00 PM PST 24
Peak memory 264340 kb
Host smart-686f6dd3-fe0f-44a5-9c6f-8d2c941bd05d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111710874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
2111710874
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.4014805910
Short name T35
Test name
Test status
Simulation time 15863300 ps
CPU time 15.67 seconds
Started Feb 21 01:09:44 PM PST 24
Finished Feb 21 01:10:00 PM PST 24
Peak memory 275016 kb
Host smart-23561fb1-c8a7-4154-9b17-cf674819db9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014805910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.4014805910
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.2649619516
Short name T326
Test name
Test status
Simulation time 6254285300 ps
CPU time 117.53 seconds
Started Feb 21 01:09:44 PM PST 24
Finished Feb 21 01:11:42 PM PST 24
Peak memory 261228 kb
Host smart-a942852b-42e9-44e5-a0c5-84e6956d8123
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649619516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.2649619516
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.1067658658
Short name T583
Test name
Test status
Simulation time 1662973300 ps
CPU time 165.03 seconds
Started Feb 21 01:09:45 PM PST 24
Finished Feb 21 01:12:31 PM PST 24
Peak memory 289228 kb
Host smart-795c21d4-19de-4de3-af0b-ec100924ec65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067658658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.1067658658
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.3379838627
Short name T444
Test name
Test status
Simulation time 39189896400 ps
CPU time 205.95 seconds
Started Feb 21 01:09:46 PM PST 24
Finished Feb 21 01:13:12 PM PST 24
Peak memory 290160 kb
Host smart-5242c779-3657-4330-afcb-a919fe2ef779
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379838627 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.3379838627
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.2918544745
Short name T290
Test name
Test status
Simulation time 27839700 ps
CPU time 28.63 seconds
Started Feb 21 01:09:44 PM PST 24
Finished Feb 21 01:10:13 PM PST 24
Peak memory 265636 kb
Host smart-5c1f050b-6525-4d44-881d-99c63de79fec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918544745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.2918544745
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3483689534
Short name T45
Test name
Test status
Simulation time 35290700 ps
CPU time 31.5 seconds
Started Feb 21 01:09:55 PM PST 24
Finished Feb 21 01:10:27 PM PST 24
Peak memory 273860 kb
Host smart-28d3b7ce-23de-44d2-9608-9042f9a39bf4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483689534 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3483689534
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.3998749687
Short name T965
Test name
Test status
Simulation time 1048565100 ps
CPU time 61.42 seconds
Started Feb 21 01:09:45 PM PST 24
Finished Feb 21 01:10:46 PM PST 24
Peak memory 258808 kb
Host smart-74e89da8-c0eb-4eb3-9cfb-dbf7b0c1d51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998749687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.3998749687
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.6048553
Short name T805
Test name
Test status
Simulation time 16831700 ps
CPU time 99.75 seconds
Started Feb 21 01:09:52 PM PST 24
Finished Feb 21 01:11:32 PM PST 24
Peak memory 275400 kb
Host smart-dea8fbf7-6eec-46e7-8a78-aa9092fbb226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6048553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.6048553
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.4255009424
Short name T468
Test name
Test status
Simulation time 85427000 ps
CPU time 13.59 seconds
Started Feb 21 01:10:01 PM PST 24
Finished Feb 21 01:10:16 PM PST 24
Peak memory 263940 kb
Host smart-69c0c1a0-4f28-44ad-8af4-2c772677530a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255009424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
4255009424
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.2524671425
Short name T421
Test name
Test status
Simulation time 14524100 ps
CPU time 13.24 seconds
Started Feb 21 01:10:00 PM PST 24
Finished Feb 21 01:10:13 PM PST 24
Peak memory 273984 kb
Host smart-642c5164-dcf7-40b6-961b-e9440d491684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524671425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2524671425
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.657742760
Short name T134
Test name
Test status
Simulation time 11140800 ps
CPU time 21.64 seconds
Started Feb 21 01:10:01 PM PST 24
Finished Feb 21 01:10:23 PM PST 24
Peak memory 272884 kb
Host smart-c04bea3f-099f-4329-b95b-84ea2f5c6248
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657742760 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.657742760
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.561865790
Short name T526
Test name
Test status
Simulation time 1561472600 ps
CPU time 72.87 seconds
Started Feb 21 01:09:47 PM PST 24
Finished Feb 21 01:11:00 PM PST 24
Peak memory 261200 kb
Host smart-64a784e6-8ebb-485a-9ec0-064008215e73
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561865790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_h
w_sec_otp.561865790
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.3300911609
Short name T647
Test name
Test status
Simulation time 9318009000 ps
CPU time 187.51 seconds
Started Feb 21 01:09:47 PM PST 24
Finished Feb 21 01:12:55 PM PST 24
Peak memory 289116 kb
Host smart-d0f0fca3-4437-48b4-8378-184d14de8a8f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300911609 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.3300911609
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.1567688935
Short name T511
Test name
Test status
Simulation time 38359700 ps
CPU time 133.57 seconds
Started Feb 21 01:09:52 PM PST 24
Finished Feb 21 01:12:06 PM PST 24
Peak memory 258708 kb
Host smart-43aec957-2a78-40b9-9120-ce5271b9abe4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567688935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.1567688935
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.1874019503
Short name T1026
Test name
Test status
Simulation time 64080700 ps
CPU time 31.19 seconds
Started Feb 21 01:09:46 PM PST 24
Finished Feb 21 01:10:18 PM PST 24
Peak memory 271732 kb
Host smart-5ca31566-9d94-4fed-bd09-56c9aea0eac6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874019503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.1874019503
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.1700165196
Short name T1029
Test name
Test status
Simulation time 104891300 ps
CPU time 30.83 seconds
Started Feb 21 01:10:01 PM PST 24
Finished Feb 21 01:10:32 PM PST 24
Peak memory 265600 kb
Host smart-c44b8184-a145-4a9e-9793-be6c9f6e155a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700165196 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.1700165196
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.372980323
Short name T410
Test name
Test status
Simulation time 24229576800 ps
CPU time 88.92 seconds
Started Feb 21 01:10:00 PM PST 24
Finished Feb 21 01:11:30 PM PST 24
Peak memory 258744 kb
Host smart-c5b15f92-2d7b-4641-9189-bde6202bb838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372980323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.372980323
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.4113914407
Short name T693
Test name
Test status
Simulation time 29913100 ps
CPU time 171.17 seconds
Started Feb 21 01:09:45 PM PST 24
Finished Feb 21 01:12:36 PM PST 24
Peak memory 278256 kb
Host smart-6db3b220-d752-4df5-ad1b-56f34667b8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113914407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.4113914407
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.3387881393
Short name T412
Test name
Test status
Simulation time 58374400 ps
CPU time 13.55 seconds
Started Feb 21 01:10:02 PM PST 24
Finished Feb 21 01:10:16 PM PST 24
Peak memory 263556 kb
Host smart-81b3fb75-f44d-4dfd-af10-e1adb2fe4ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387881393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
3387881393
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.1047177157
Short name T777
Test name
Test status
Simulation time 39830000 ps
CPU time 13.2 seconds
Started Feb 21 01:10:01 PM PST 24
Finished Feb 21 01:10:15 PM PST 24
Peak memory 273864 kb
Host smart-a2ec687d-8f1e-45e0-b7cc-0f10ebb11caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047177157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.1047177157
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.342901047
Short name T171
Test name
Test status
Simulation time 16936600 ps
CPU time 21.71 seconds
Started Feb 21 01:10:02 PM PST 24
Finished Feb 21 01:10:24 PM PST 24
Peak memory 264732 kb
Host smart-f74c2918-1676-4c32-8081-b4038d64c94d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342901047 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.342901047
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.3085064558
Short name T871
Test name
Test status
Simulation time 2859739300 ps
CPU time 47.12 seconds
Started Feb 21 01:10:00 PM PST 24
Finished Feb 21 01:10:48 PM PST 24
Peak memory 261484 kb
Host smart-b99c88b4-9fdd-4659-aad1-7cb2f335e689
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085064558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.3085064558
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.4107126921
Short name T212
Test name
Test status
Simulation time 3245988800 ps
CPU time 163.18 seconds
Started Feb 21 01:10:00 PM PST 24
Finished Feb 21 01:12:44 PM PST 24
Peak memory 289188 kb
Host smart-0edfcee8-3bca-4011-847c-5f046b49029b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107126921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.4107126921
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3324400925
Short name T499
Test name
Test status
Simulation time 19333081300 ps
CPU time 217.16 seconds
Started Feb 21 01:09:59 PM PST 24
Finished Feb 21 01:13:37 PM PST 24
Peak memory 283772 kb
Host smart-13f8f0f7-c36b-4498-927f-778b441cfd3b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324400925 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.3324400925
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.1270560161
Short name T672
Test name
Test status
Simulation time 91702300 ps
CPU time 116.39 seconds
Started Feb 21 01:09:58 PM PST 24
Finished Feb 21 01:11:55 PM PST 24
Peak memory 258796 kb
Host smart-73310b6b-d1d0-4e43-9460-38ae0c15d4e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270560161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.1270560161
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.3064896481
Short name T268
Test name
Test status
Simulation time 219566500 ps
CPU time 31.71 seconds
Started Feb 21 01:10:01 PM PST 24
Finished Feb 21 01:10:34 PM PST 24
Peak memory 274916 kb
Host smart-eb6afc5a-999c-465d-870d-5a66f73a6a67
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064896481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.3064896481
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.2577157756
Short name T340
Test name
Test status
Simulation time 45122100 ps
CPU time 31.37 seconds
Started Feb 21 01:10:03 PM PST 24
Finished Feb 21 01:10:35 PM PST 24
Peak memory 271908 kb
Host smart-d2d24d4a-70e2-47b0-b0b4-7ce04cebfd28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577157756 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.2577157756
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.3279250482
Short name T397
Test name
Test status
Simulation time 3881930000 ps
CPU time 68.35 seconds
Started Feb 21 01:10:02 PM PST 24
Finished Feb 21 01:11:11 PM PST 24
Peak memory 264404 kb
Host smart-e42fa34c-fbb0-4837-bf65-9f84dc7bd116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279250482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.3279250482
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.716200967
Short name T883
Test name
Test status
Simulation time 59795800 ps
CPU time 75.99 seconds
Started Feb 21 01:10:00 PM PST 24
Finished Feb 21 01:11:17 PM PST 24
Peak memory 275192 kb
Host smart-d31ad90e-6089-467e-8dc9-566146be0a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716200967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.716200967
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.2153590582
Short name T281
Test name
Test status
Simulation time 128435400 ps
CPU time 13.75 seconds
Started Feb 21 01:04:34 PM PST 24
Finished Feb 21 01:04:49 PM PST 24
Peak memory 264144 kb
Host smart-a4089298-7791-4239-bd35-9d2efdc82061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153590582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.2
153590582
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.403310244
Short name T233
Test name
Test status
Simulation time 22468900 ps
CPU time 13.95 seconds
Started Feb 21 01:04:37 PM PST 24
Finished Feb 21 01:04:54 PM PST 24
Peak memory 263656 kb
Host smart-22f85974-0bf5-46c4-a6ce-c1e8c74e5a88
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403310244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
flash_ctrl_config_regwen.403310244
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.4181509367
Short name T1003
Test name
Test status
Simulation time 16245100 ps
CPU time 15.58 seconds
Started Feb 21 01:04:35 PM PST 24
Finished Feb 21 01:04:51 PM PST 24
Peak memory 274720 kb
Host smart-42badc9a-7c0b-4419-9a0a-08ced8098b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181509367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.4181509367
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.3496583922
Short name T786
Test name
Test status
Simulation time 9951100 ps
CPU time 20.86 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 01:05:01 PM PST 24
Peak memory 279604 kb
Host smart-b103b839-9604-4365-9f10-bff8fcb9f2e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496583922 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.3496583922
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.585057175
Short name T800
Test name
Test status
Simulation time 10762532200 ps
CPU time 392.96 seconds
Started Feb 21 01:04:26 PM PST 24
Finished Feb 21 01:11:00 PM PST 24
Peak memory 262148 kb
Host smart-73c12e4d-6106-484c-a874-a94545f57055
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585057175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.585057175
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.121883363
Short name T130
Test name
Test status
Simulation time 16825204000 ps
CPU time 2187.39 seconds
Started Feb 21 01:04:27 PM PST 24
Finished Feb 21 01:40:55 PM PST 24
Peak memory 264388 kb
Host smart-efaed87f-782b-45b9-a678-e4381c049590
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121883363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erro
r_mp.121883363
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.1636974589
Short name T188
Test name
Test status
Simulation time 3341949300 ps
CPU time 2630.36 seconds
Started Feb 21 01:04:27 PM PST 24
Finished Feb 21 01:48:18 PM PST 24
Peak memory 264364 kb
Host smart-2d7aa42d-9406-4ef9-bcf8-fd23dde73662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636974589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1636974589
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.3557994126
Short name T901
Test name
Test status
Simulation time 2666243100 ps
CPU time 888.21 seconds
Started Feb 21 01:04:28 PM PST 24
Finished Feb 21 01:19:16 PM PST 24
Peak memory 272644 kb
Host smart-fd8c8f99-c52b-416c-a62a-3a4acd8e9a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557994126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.3557994126
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.228040316
Short name T745
Test name
Test status
Simulation time 341810812200 ps
CPU time 2103.02 seconds
Started Feb 21 01:04:28 PM PST 24
Finished Feb 21 01:39:31 PM PST 24
Peak memory 264288 kb
Host smart-4a0c1572-cb4c-4e93-8017-8ecc554979c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228040316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.flash_ctrl_host_ctrl_arb.228040316
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.3254883298
Short name T576
Test name
Test status
Simulation time 38266900 ps
CPU time 69.93 seconds
Started Feb 21 01:04:28 PM PST 24
Finished Feb 21 01:05:38 PM PST 24
Peak memory 264432 kb
Host smart-7eba465b-58ae-4a40-a0a3-34320e62e548
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254883298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.3254883298
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2077992031
Short name T904
Test name
Test status
Simulation time 10019564800 ps
CPU time 168.82 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 01:07:29 PM PST 24
Peak memory 281284 kb
Host smart-638fbf92-ef77-4f43-9b34-0a81daa67518
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077992031 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.2077992031
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.1611879925
Short name T978
Test name
Test status
Simulation time 62879900 ps
CPU time 13.45 seconds
Started Feb 21 01:04:41 PM PST 24
Finished Feb 21 01:04:55 PM PST 24
Peak memory 264312 kb
Host smart-dbc302c7-31ef-46cf-b412-963864277f00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611879925 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.1611879925
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.433423090
Short name T951
Test name
Test status
Simulation time 50134138700 ps
CPU time 718.43 seconds
Started Feb 21 01:04:26 PM PST 24
Finished Feb 21 01:16:25 PM PST 24
Peak memory 258300 kb
Host smart-68fb9090-51a5-4df6-b6de-bf5811ac2bdf
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433423090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_hw_rma_reset.433423090
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.3657071579
Short name T849
Test name
Test status
Simulation time 969582700 ps
CPU time 37.17 seconds
Started Feb 21 01:04:27 PM PST 24
Finished Feb 21 01:05:05 PM PST 24
Peak memory 258292 kb
Host smart-430f346c-f9a2-42b1-b962-4beb3589b1e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657071579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.3657071579
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.2931765336
Short name T276
Test name
Test status
Simulation time 3520064900 ps
CPU time 591.06 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 01:14:29 PM PST 24
Peak memory 313896 kb
Host smart-2482c2a5-f414-40f0-a6f9-68dc26738ec1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931765336 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.2931765336
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.1381583513
Short name T977
Test name
Test status
Simulation time 4599443000 ps
CPU time 162.76 seconds
Started Feb 21 01:04:37 PM PST 24
Finished Feb 21 01:07:23 PM PST 24
Peak memory 293260 kb
Host smart-d5668897-afe2-4067-8056-b19739d48792
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381583513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.1381583513
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3472695453
Short name T594
Test name
Test status
Simulation time 18045014900 ps
CPU time 227.01 seconds
Started Feb 21 01:04:37 PM PST 24
Finished Feb 21 01:08:27 PM PST 24
Peak memory 283980 kb
Host smart-aa28e752-d98c-4e9e-9527-73ef4f1f25a7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472695453 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.3472695453
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.1582793182
Short name T79
Test name
Test status
Simulation time 3858055900 ps
CPU time 100.2 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 01:06:20 PM PST 24
Peak memory 264388 kb
Host smart-ceaf6c75-c24b-4fdd-be85-46f3aa86cf83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582793182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.1582793182
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.151895763
Short name T873
Test name
Test status
Simulation time 44261539300 ps
CPU time 334.79 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 01:10:15 PM PST 24
Peak memory 264360 kb
Host smart-a1de736f-0063-48a1-af24-9099c231894d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151
895763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.151895763
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.2308020978
Short name T582
Test name
Test status
Simulation time 2135983800 ps
CPU time 65.75 seconds
Started Feb 21 01:04:27 PM PST 24
Finished Feb 21 01:05:33 PM PST 24
Peak memory 259032 kb
Host smart-6c522ce5-602d-4a49-9426-1ddc36b94daf
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308020978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.2308020978
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.557028981
Short name T601
Test name
Test status
Simulation time 15289500 ps
CPU time 13.37 seconds
Started Feb 21 01:04:38 PM PST 24
Finished Feb 21 01:04:54 PM PST 24
Peak memory 264432 kb
Host smart-246a7086-c5b6-4532-b53f-754badafa9f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557028981 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.557028981
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.2323334816
Short name T124
Test name
Test status
Simulation time 11145756300 ps
CPU time 286.51 seconds
Started Feb 21 01:04:28 PM PST 24
Finished Feb 21 01:09:15 PM PST 24
Peak memory 273384 kb
Host smart-0e459214-ff90-4f8d-b019-8dcfc50ac30c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323334816 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.2323334816
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.2392956136
Short name T161
Test name
Test status
Simulation time 74799300 ps
CPU time 131.55 seconds
Started Feb 21 01:04:30 PM PST 24
Finished Feb 21 01:06:42 PM PST 24
Peak memory 263396 kb
Host smart-ddf61245-1c0b-4824-9b8e-3a7e728bfd38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392956136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.2392956136
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.1465062280
Short name T1012
Test name
Test status
Simulation time 4282502200 ps
CPU time 181.29 seconds
Started Feb 21 01:04:25 PM PST 24
Finished Feb 21 01:07:27 PM PST 24
Peak memory 281000 kb
Host smart-2be31236-c766-4263-95a5-2ad874fbe9b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465062280 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.1465062280
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.3838915583
Short name T222
Test name
Test status
Simulation time 15541700 ps
CPU time 13.81 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 01:04:51 PM PST 24
Peak memory 264704 kb
Host smart-1239963f-6608-41d3-bf36-c3c032628445
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3838915583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3838915583
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.1018121129
Short name T673
Test name
Test status
Simulation time 50633100 ps
CPU time 195.4 seconds
Started Feb 21 01:04:25 PM PST 24
Finished Feb 21 01:07:41 PM PST 24
Peak memory 264504 kb
Host smart-3abc379e-19e8-4347-8c39-24e2a0fbb89e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018121129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1018121129
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.394472078
Short name T761
Test name
Test status
Simulation time 704958500 ps
CPU time 41.06 seconds
Started Feb 21 01:04:39 PM PST 24
Finished Feb 21 01:05:21 PM PST 24
Peak memory 264640 kb
Host smart-71bb8c5a-aab0-4203-8e54-de465c4707ab
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394472078 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.394472078
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.1143995143
Short name T204
Test name
Test status
Simulation time 14705300 ps
CPU time 14.33 seconds
Started Feb 21 01:04:39 PM PST 24
Finished Feb 21 01:04:55 PM PST 24
Peak memory 264712 kb
Host smart-42770322-33c4-47f5-a069-4f725fed420c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143995143 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1143995143
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.1501463328
Short name T881
Test name
Test status
Simulation time 152298900 ps
CPU time 15.29 seconds
Started Feb 21 01:04:39 PM PST 24
Finished Feb 21 01:04:56 PM PST 24
Peak memory 263768 kb
Host smart-d7dce8d6-d386-4945-aaac-18b9b780e719
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501463328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.1501463328
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.1307808430
Short name T131
Test name
Test status
Simulation time 870380400 ps
CPU time 1112.64 seconds
Started Feb 21 01:04:13 PM PST 24
Finished Feb 21 01:22:46 PM PST 24
Peak memory 285736 kb
Host smart-312bd8f9-4445-472a-90db-bc8d63a14093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307808430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.1307808430
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.1021332800
Short name T599
Test name
Test status
Simulation time 928392000 ps
CPU time 118.45 seconds
Started Feb 21 01:04:26 PM PST 24
Finished Feb 21 01:06:25 PM PST 24
Peak memory 264472 kb
Host smart-607799e5-9d56-4c31-ad88-d00f732d5887
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1021332800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.1021332800
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.1865606361
Short name T797
Test name
Test status
Simulation time 2506448600 ps
CPU time 40.48 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 01:05:20 PM PST 24
Peak memory 271660 kb
Host smart-58748112-cc9b-4e01-9499-db05328ffc9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865606361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.1865606361
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.1744127726
Short name T1134
Test name
Test status
Simulation time 19350100 ps
CPU time 22.64 seconds
Started Feb 21 01:04:38 PM PST 24
Finished Feb 21 01:05:03 PM PST 24
Peak memory 264508 kb
Host smart-b2b54d28-7a2f-4143-87d3-bb371d353e8a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744127726 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.1744127726
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.672303415
Short name T1007
Test name
Test status
Simulation time 82535600 ps
CPU time 23.07 seconds
Started Feb 21 01:04:27 PM PST 24
Finished Feb 21 01:04:50 PM PST 24
Peak memory 264500 kb
Host smart-f471b612-f97e-483a-87c9-ba6fca3a62c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672303415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_read_word_sweep_serr.672303415
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.923421897
Short name T900
Test name
Test status
Simulation time 1816332400 ps
CPU time 105.65 seconds
Started Feb 21 01:04:30 PM PST 24
Finished Feb 21 01:06:16 PM PST 24
Peak memory 279984 kb
Host smart-f78d651f-6016-4c1c-b5b9-398f71017d34
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923421897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_ro.923421897
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.2449117564
Short name T572
Test name
Test status
Simulation time 7848812000 ps
CPU time 118.85 seconds
Started Feb 21 01:04:26 PM PST 24
Finished Feb 21 01:06:25 PM PST 24
Peak memory 281016 kb
Host smart-828f7520-eb26-4f07-9065-47b1149e1e13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2449117564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.2449117564
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.3269064973
Short name T1072
Test name
Test status
Simulation time 3966460200 ps
CPU time 118.51 seconds
Started Feb 21 01:04:27 PM PST 24
Finished Feb 21 01:06:26 PM PST 24
Peak memory 293624 kb
Host smart-2d874350-70af-4032-ad4f-17050c2aae54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269064973 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.3269064973
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.2885208952
Short name T1028
Test name
Test status
Simulation time 37097950500 ps
CPU time 423.32 seconds
Started Feb 21 01:04:26 PM PST 24
Finished Feb 21 01:11:30 PM PST 24
Peak memory 313716 kb
Host smart-83b2fa50-4ead-46b1-9487-5f2c95cf7d8b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885208952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_rw.2885208952
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.2150791969
Short name T746
Test name
Test status
Simulation time 28615785500 ps
CPU time 442.78 seconds
Started Feb 21 01:04:28 PM PST 24
Finished Feb 21 01:11:51 PM PST 24
Peak memory 328532 kb
Host smart-48a8561b-0aed-49be-b495-c654bb5cbf5d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150791969 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_rw_derr.2150791969
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.2563873938
Short name T920
Test name
Test status
Simulation time 87080700 ps
CPU time 32.96 seconds
Started Feb 21 01:04:41 PM PST 24
Finished Feb 21 01:05:15 PM PST 24
Peak memory 272720 kb
Host smart-4092bed2-a3e9-4f88-b4c0-a14575194ac9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563873938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.2563873938
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.2628340756
Short name T47
Test name
Test status
Simulation time 1226513300 ps
CPU time 35.25 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 01:05:15 PM PST 24
Peak memory 277340 kb
Host smart-2a8ce026-3a0f-4531-96f7-dac5ccdc607a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628340756 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.2628340756
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.3771206483
Short name T1051
Test name
Test status
Simulation time 2221793300 ps
CPU time 375.5 seconds
Started Feb 21 01:04:27 PM PST 24
Finished Feb 21 01:10:43 PM PST 24
Peak memory 319176 kb
Host smart-a3817093-d0a0-4211-af18-30d8103909e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771206483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s
err.3771206483
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.3463596405
Short name T139
Test name
Test status
Simulation time 3817950000 ps
CPU time 4780.04 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 02:24:20 PM PST 24
Peak memory 285992 kb
Host smart-339fdeca-a4d9-44c5-bf48-b2c4e1a9023e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463596405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3463596405
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.2152775634
Short name T402
Test name
Test status
Simulation time 532188300 ps
CPU time 60.72 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 01:05:41 PM PST 24
Peak memory 261996 kb
Host smart-93502e28-fb2a-4791-aad1-7600e6b4d66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152775634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2152775634
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.1139105169
Short name T470
Test name
Test status
Simulation time 4409598000 ps
CPU time 76.88 seconds
Started Feb 21 01:04:30 PM PST 24
Finished Feb 21 01:05:47 PM PST 24
Peak memory 264536 kb
Host smart-43e9e05f-1502-4fa5-8b92-b3c4e22ff66d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139105169 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.1139105169
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.2146587622
Short name T803
Test name
Test status
Simulation time 4954204400 ps
CPU time 49.61 seconds
Started Feb 21 01:04:28 PM PST 24
Finished Feb 21 01:05:18 PM PST 24
Peak memory 264604 kb
Host smart-f65ca505-8d75-4c15-8a2a-ce9c78c128d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146587622 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.2146587622
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.1060433810
Short name T658
Test name
Test status
Simulation time 31922500 ps
CPU time 142.61 seconds
Started Feb 21 01:04:12 PM PST 24
Finished Feb 21 01:06:35 PM PST 24
Peak memory 275192 kb
Host smart-c1e488f4-ea3e-4e5d-a0dd-e8b581a9138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060433810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.1060433810
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.2167892245
Short name T661
Test name
Test status
Simulation time 13449400 ps
CPU time 23.45 seconds
Started Feb 21 01:04:13 PM PST 24
Finished Feb 21 01:04:36 PM PST 24
Peak memory 258228 kb
Host smart-22056fc0-33f3-4e3f-9098-26004d780c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167892245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.2167892245
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.1558626223
Short name T686
Test name
Test status
Simulation time 1218988600 ps
CPU time 1332.71 seconds
Started Feb 21 01:04:35 PM PST 24
Finished Feb 21 01:26:48 PM PST 24
Peak memory 289084 kb
Host smart-1f0ea7f7-d8a4-4623-b0e9-48feda3aaecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558626223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.1558626223
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.3906992998
Short name T986
Test name
Test status
Simulation time 77256300 ps
CPU time 26.57 seconds
Started Feb 21 01:04:26 PM PST 24
Finished Feb 21 01:04:53 PM PST 24
Peak memory 258144 kb
Host smart-1c8cc70c-f007-4255-88b3-b98706b7b2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906992998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.3906992998
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.3755890988
Short name T115
Test name
Test status
Simulation time 3278271800 ps
CPU time 138.47 seconds
Started Feb 21 01:04:27 PM PST 24
Finished Feb 21 01:06:46 PM PST 24
Peak memory 264404 kb
Host smart-67b17a7c-a0f1-454a-b4b3-20b090dfe4c3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755890988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.flash_ctrl_wo.3755890988
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.49926139
Short name T691
Test name
Test status
Simulation time 319292100 ps
CPU time 13.51 seconds
Started Feb 21 01:10:02 PM PST 24
Finished Feb 21 01:10:16 PM PST 24
Peak memory 264152 kb
Host smart-6f7360e6-c36f-45b2-a03e-82f3191f7735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49926139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.49926139
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.1689304290
Short name T1125
Test name
Test status
Simulation time 30204200 ps
CPU time 16 seconds
Started Feb 21 01:10:02 PM PST 24
Finished Feb 21 01:10:18 PM PST 24
Peak memory 283160 kb
Host smart-73761371-4403-432f-9f27-527984f6172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689304290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.1689304290
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.2508976892
Short name T1110
Test name
Test status
Simulation time 13042900 ps
CPU time 22.05 seconds
Started Feb 21 01:10:01 PM PST 24
Finished Feb 21 01:10:24 PM PST 24
Peak memory 279544 kb
Host smart-c75ba1c3-8c4f-4ada-9e57-d1c7c5314c49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508976892 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.2508976892
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.3885759335
Short name T322
Test name
Test status
Simulation time 16187193500 ps
CPU time 113.74 seconds
Started Feb 21 01:10:09 PM PST 24
Finished Feb 21 01:12:03 PM PST 24
Peak memory 261172 kb
Host smart-dc5d2726-d24c-46b9-a973-348996aa575b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885759335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.3885759335
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.2458671723
Short name T271
Test name
Test status
Simulation time 2078733600 ps
CPU time 52.22 seconds
Started Feb 21 01:10:09 PM PST 24
Finished Feb 21 01:11:01 PM PST 24
Peak memory 263844 kb
Host smart-90447559-4a5a-4d48-83bb-fefe816bfc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458671723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2458671723
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.3141877496
Short name T273
Test name
Test status
Simulation time 61834300 ps
CPU time 51.78 seconds
Started Feb 21 01:10:09 PM PST 24
Finished Feb 21 01:11:01 PM PST 24
Peak memory 269692 kb
Host smart-30fb09f5-ef60-4502-93fb-94926e2af722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141877496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.3141877496
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.392694619
Short name T932
Test name
Test status
Simulation time 24852400 ps
CPU time 13.66 seconds
Started Feb 21 01:10:12 PM PST 24
Finished Feb 21 01:10:26 PM PST 24
Peak memory 264136 kb
Host smart-65628c73-d592-4d05-8c2e-fb2a780d4d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392694619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.392694619
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.3513932471
Short name T586
Test name
Test status
Simulation time 40687300 ps
CPU time 16.01 seconds
Started Feb 21 01:10:10 PM PST 24
Finished Feb 21 01:10:28 PM PST 24
Peak memory 274224 kb
Host smart-32310818-fe94-4a11-9f71-9a7df7c66dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513932471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.3513932471
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.829882214
Short name T374
Test name
Test status
Simulation time 32124900 ps
CPU time 21.77 seconds
Started Feb 21 01:10:10 PM PST 24
Finished Feb 21 01:10:34 PM PST 24
Peak memory 279820 kb
Host smart-17525707-d28f-4504-9e3e-627d035e3a29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829882214 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.829882214
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3316924863
Short name T857
Test name
Test status
Simulation time 10700448300 ps
CPU time 61.95 seconds
Started Feb 21 01:10:12 PM PST 24
Finished Feb 21 01:11:14 PM PST 24
Peak memory 258376 kb
Host smart-480e8a6d-51fe-48e3-b953-092c63c58817
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316924863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.3316924863
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.2060571803
Short name T111
Test name
Test status
Simulation time 41274500 ps
CPU time 132.64 seconds
Started Feb 21 01:10:14 PM PST 24
Finished Feb 21 01:12:26 PM PST 24
Peak memory 262420 kb
Host smart-655c2d0f-9fcd-4e15-b4ab-cee22c97b8b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060571803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.2060571803
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.308196164
Short name T180
Test name
Test status
Simulation time 1876416700 ps
CPU time 59.93 seconds
Started Feb 21 01:10:09 PM PST 24
Finished Feb 21 01:11:12 PM PST 24
Peak memory 262192 kb
Host smart-9861d10d-b5d0-4009-a2a2-8e6dd17d6e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308196164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.308196164
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.2861106008
Short name T509
Test name
Test status
Simulation time 72432700 ps
CPU time 145.09 seconds
Started Feb 21 01:10:12 PM PST 24
Finished Feb 21 01:12:37 PM PST 24
Peak memory 275272 kb
Host smart-cc617151-065e-48d2-85fa-31084a607e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861106008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2861106008
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.652913590
Short name T282
Test name
Test status
Simulation time 32222100 ps
CPU time 13.55 seconds
Started Feb 21 01:10:11 PM PST 24
Finished Feb 21 01:10:26 PM PST 24
Peak memory 264028 kb
Host smart-b1df9716-c8d9-4fe9-9a33-b88772935700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652913590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.652913590
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.1329440187
Short name T283
Test name
Test status
Simulation time 15693400 ps
CPU time 13.63 seconds
Started Feb 21 01:10:10 PM PST 24
Finished Feb 21 01:10:26 PM PST 24
Peak memory 273988 kb
Host smart-5766ff7b-76c3-49f5-b6d0-ca6662affe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329440187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1329440187
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.825279400
Short name T189
Test name
Test status
Simulation time 17477000 ps
CPU time 21.78 seconds
Started Feb 21 01:10:12 PM PST 24
Finished Feb 21 01:10:34 PM PST 24
Peak memory 279748 kb
Host smart-2a9dff11-3213-4b1b-92a8-55a58abc399f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825279400 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.825279400
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2582069639
Short name T324
Test name
Test status
Simulation time 22561373800 ps
CPU time 118.91 seconds
Started Feb 21 01:10:10 PM PST 24
Finished Feb 21 01:12:11 PM PST 24
Peak memory 261536 kb
Host smart-87c958d0-7ae1-4b4e-8de6-006755d2bd97
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582069639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.2582069639
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.1095114277
Short name T1022
Test name
Test status
Simulation time 40387200 ps
CPU time 114.63 seconds
Started Feb 21 01:10:10 PM PST 24
Finished Feb 21 01:12:07 PM PST 24
Peak memory 259156 kb
Host smart-e4488678-1ccf-4528-b989-020edd967ffb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095114277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.1095114277
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.1553939638
Short name T1046
Test name
Test status
Simulation time 1127310500 ps
CPU time 62.35 seconds
Started Feb 21 01:10:14 PM PST 24
Finished Feb 21 01:11:17 PM PST 24
Peak memory 263616 kb
Host smart-fbdf5183-5a2e-4753-9d52-742e17fefaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553939638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.1553939638
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.2351674505
Short name T866
Test name
Test status
Simulation time 25426800 ps
CPU time 96.91 seconds
Started Feb 21 01:10:11 PM PST 24
Finished Feb 21 01:11:49 PM PST 24
Peak memory 274288 kb
Host smart-16322db4-4456-4988-88f0-92788eee4b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351674505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.2351674505
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.3154155192
Short name T734
Test name
Test status
Simulation time 74054100 ps
CPU time 13.54 seconds
Started Feb 21 01:10:14 PM PST 24
Finished Feb 21 01:10:28 PM PST 24
Peak memory 264172 kb
Host smart-d9f1d0d3-a267-42f8-b212-4c0514f51b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154155192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
3154155192
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.1917283078
Short name T427
Test name
Test status
Simulation time 13381500 ps
CPU time 13.29 seconds
Started Feb 21 01:10:12 PM PST 24
Finished Feb 21 01:10:26 PM PST 24
Peak memory 273896 kb
Host smart-157d62d4-3112-4953-b496-54fc579834c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917283078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.1917283078
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.4081166898
Short name T663
Test name
Test status
Simulation time 147579500 ps
CPU time 137.72 seconds
Started Feb 21 01:10:13 PM PST 24
Finished Feb 21 01:12:31 PM PST 24
Peak memory 258936 kb
Host smart-2e9bf371-c34d-48bc-bf6f-d79f226f2338
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081166898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.4081166898
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.1412387879
Short name T438
Test name
Test status
Simulation time 49277600 ps
CPU time 75.86 seconds
Started Feb 21 01:10:12 PM PST 24
Finished Feb 21 01:11:28 PM PST 24
Peak memory 273924 kb
Host smart-e369f372-cf90-4765-ab86-3e180f7909e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412387879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1412387879
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.2537909944
Short name T688
Test name
Test status
Simulation time 44235800 ps
CPU time 13.61 seconds
Started Feb 21 01:10:10 PM PST 24
Finished Feb 21 01:10:26 PM PST 24
Peak memory 263468 kb
Host smart-acabd5c7-39a7-47e7-a273-f774184b46e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537909944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
2537909944
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.3731112322
Short name T1086
Test name
Test status
Simulation time 31892300 ps
CPU time 13.25 seconds
Started Feb 21 01:10:17 PM PST 24
Finished Feb 21 01:10:33 PM PST 24
Peak memory 273892 kb
Host smart-6f9f484d-d026-4b14-a812-e0662c6d5e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731112322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.3731112322
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.2661392858
Short name T1115
Test name
Test status
Simulation time 12561600 ps
CPU time 22.25 seconds
Started Feb 21 01:10:13 PM PST 24
Finished Feb 21 01:10:35 PM PST 24
Peak memory 279320 kb
Host smart-766819db-51b8-4d98-8b8a-88fea2c4f111
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661392858 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.2661392858
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1023400308
Short name T325
Test name
Test status
Simulation time 2655858700 ps
CPU time 102.66 seconds
Started Feb 21 01:10:14 PM PST 24
Finished Feb 21 01:11:57 PM PST 24
Peak memory 261128 kb
Host smart-15b2ca23-62ab-4c71-b518-4562cd6dc40e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023400308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.1023400308
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.947222891
Short name T159
Test name
Test status
Simulation time 37670800 ps
CPU time 114.07 seconds
Started Feb 21 01:10:14 PM PST 24
Finished Feb 21 01:12:08 PM PST 24
Peak memory 263088 kb
Host smart-f666255b-3dc9-4bfd-a369-68ac8876dcab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947222891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ot
p_reset.947222891
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.890889514
Short name T694
Test name
Test status
Simulation time 38209100 ps
CPU time 75.94 seconds
Started Feb 21 01:10:17 PM PST 24
Finished Feb 21 01:11:35 PM PST 24
Peak memory 273924 kb
Host smart-96cd5134-0e24-4d39-b6ae-c040abcddc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890889514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.890889514
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.4132259866
Short name T567
Test name
Test status
Simulation time 97118000 ps
CPU time 13.79 seconds
Started Feb 21 01:10:44 PM PST 24
Finished Feb 21 01:10:58 PM PST 24
Peak memory 264520 kb
Host smart-7fc9e665-7a0e-4414-91c1-a1ca0380fafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132259866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
4132259866
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.2363918770
Short name T648
Test name
Test status
Simulation time 34094000 ps
CPU time 15.9 seconds
Started Feb 21 01:10:45 PM PST 24
Finished Feb 21 01:11:02 PM PST 24
Peak memory 283308 kb
Host smart-901c5f21-e6c0-40cf-911b-ed93c84588b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363918770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2363918770
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.4079692847
Short name T551
Test name
Test status
Simulation time 10506100 ps
CPU time 20.42 seconds
Started Feb 21 01:10:43 PM PST 24
Finished Feb 21 01:11:04 PM PST 24
Peak memory 272772 kb
Host smart-54d47e52-e817-418d-a8f6-4e639b1f1b3a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079692847 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.4079692847
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.1687507046
Short name T606
Test name
Test status
Simulation time 3226536100 ps
CPU time 221.66 seconds
Started Feb 21 01:10:13 PM PST 24
Finished Feb 21 01:13:55 PM PST 24
Peak memory 261256 kb
Host smart-e4871473-a9a5-47a5-81ce-a52c18ee93cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687507046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.1687507046
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.899183640
Short name T703
Test name
Test status
Simulation time 37212800 ps
CPU time 113.23 seconds
Started Feb 21 01:10:44 PM PST 24
Finished Feb 21 01:12:38 PM PST 24
Peak memory 258616 kb
Host smart-359ef703-e5bf-4ec0-a866-2f56ef94ee6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899183640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_ot
p_reset.899183640
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.897933245
Short name T838
Test name
Test status
Simulation time 26528130500 ps
CPU time 99.76 seconds
Started Feb 21 01:10:46 PM PST 24
Finished Feb 21 01:12:27 PM PST 24
Peak memory 263296 kb
Host smart-8314319e-053a-478a-b2d1-c909f929ada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897933245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.897933245
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.484395333
Short name T506
Test name
Test status
Simulation time 24070500 ps
CPU time 73.37 seconds
Started Feb 21 01:10:17 PM PST 24
Finished Feb 21 01:11:31 PM PST 24
Peak memory 273896 kb
Host smart-36e29210-d16f-4e33-b5c7-f95e954ba82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484395333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.484395333
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1639939617
Short name T931
Test name
Test status
Simulation time 99346800 ps
CPU time 14.21 seconds
Started Feb 21 01:10:43 PM PST 24
Finished Feb 21 01:10:58 PM PST 24
Peak memory 264200 kb
Host smart-9edce567-08a9-4e8e-97c7-01f23a15f8fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639939617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1639939617
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.93739291
Short name T14
Test name
Test status
Simulation time 15058600 ps
CPU time 15.75 seconds
Started Feb 21 01:10:41 PM PST 24
Finished Feb 21 01:10:58 PM PST 24
Peak memory 273916 kb
Host smart-3ad88f99-fa00-4c47-9f68-d1d129f5316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93739291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.93739291
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.2056940774
Short name T969
Test name
Test status
Simulation time 28500800 ps
CPU time 21.66 seconds
Started Feb 21 01:10:44 PM PST 24
Finished Feb 21 01:11:06 PM PST 24
Peak memory 264720 kb
Host smart-7511be73-4f0a-40ef-82a5-96546c1fcbe3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056940774 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.2056940774
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.2237239958
Short name T923
Test name
Test status
Simulation time 4138911900 ps
CPU time 119.93 seconds
Started Feb 21 01:10:45 PM PST 24
Finished Feb 21 01:12:46 PM PST 24
Peak memory 261180 kb
Host smart-b401df54-1e40-4cf3-934e-c0a74aeebcc9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237239958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.2237239958
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.1620592287
Short name T653
Test name
Test status
Simulation time 49116100 ps
CPU time 135.47 seconds
Started Feb 21 01:10:46 PM PST 24
Finished Feb 21 01:13:02 PM PST 24
Peak memory 259068 kb
Host smart-00d389a8-c7fe-4c9a-8962-a4f5a9792044
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620592287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.1620592287
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.1669003959
Short name T674
Test name
Test status
Simulation time 24508000 ps
CPU time 98.35 seconds
Started Feb 21 01:10:46 PM PST 24
Finished Feb 21 01:12:25 PM PST 24
Peak memory 274052 kb
Host smart-6db0b72b-f058-4b43-a60a-c65182b8f51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669003959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1669003959
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.2167127185
Short name T455
Test name
Test status
Simulation time 20629700 ps
CPU time 13.4 seconds
Started Feb 21 01:10:46 PM PST 24
Finished Feb 21 01:11:00 PM PST 24
Peak memory 264460 kb
Host smart-30b69523-2d15-4297-8b64-2146c32fc6c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167127185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
2167127185
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.3003739385
Short name T132
Test name
Test status
Simulation time 24091000 ps
CPU time 13.19 seconds
Started Feb 21 01:10:41 PM PST 24
Finished Feb 21 01:10:54 PM PST 24
Peak memory 274192 kb
Host smart-56e0eb54-91ab-41c3-86f3-39f988aa3bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003739385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.3003739385
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.458679399
Short name T169
Test name
Test status
Simulation time 13989600 ps
CPU time 22.08 seconds
Started Feb 21 01:10:46 PM PST 24
Finished Feb 21 01:11:09 PM PST 24
Peak memory 272848 kb
Host smart-4ccce1ca-c0ef-44d9-a683-5e0e98ee8061
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458679399 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.458679399
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.172690261
Short name T457
Test name
Test status
Simulation time 6329274300 ps
CPU time 241.92 seconds
Started Feb 21 01:10:40 PM PST 24
Finished Feb 21 01:14:42 PM PST 24
Peak memory 261316 kb
Host smart-b1f6dbeb-5c8c-45e8-92e7-f72851219a90
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172690261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_h
w_sec_otp.172690261
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.58081223
Short name T1049
Test name
Test status
Simulation time 147909100 ps
CPU time 131.6 seconds
Started Feb 21 01:10:44 PM PST 24
Finished Feb 21 01:12:56 PM PST 24
Peak memory 258596 kb
Host smart-42e4cfb5-321e-4a9f-b5f4-0dfe4f134667
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58081223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp
_reset.58081223
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.2791187441
Short name T924
Test name
Test status
Simulation time 4293554400 ps
CPU time 70.93 seconds
Started Feb 21 01:10:42 PM PST 24
Finished Feb 21 01:11:54 PM PST 24
Peak memory 262744 kb
Host smart-42ba9f93-f48c-4f74-8c58-9a21e4bcee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791187441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2791187441
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.892663576
Short name T1065
Test name
Test status
Simulation time 72332400 ps
CPU time 99 seconds
Started Feb 21 01:10:43 PM PST 24
Finished Feb 21 01:12:22 PM PST 24
Peak memory 275452 kb
Host smart-4f61c38d-774e-4833-8445-6b33e6729a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892663576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.892663576
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.1318164289
Short name T538
Test name
Test status
Simulation time 18380900 ps
CPU time 13.64 seconds
Started Feb 21 01:10:46 PM PST 24
Finished Feb 21 01:11:00 PM PST 24
Peak memory 264680 kb
Host smart-61b9f01d-23ea-4da6-bab0-a54dbcd63090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318164289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
1318164289
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.3635933554
Short name T464
Test name
Test status
Simulation time 23854600 ps
CPU time 15.49 seconds
Started Feb 21 01:10:43 PM PST 24
Finished Feb 21 01:10:59 PM PST 24
Peak memory 274032 kb
Host smart-69b6a509-ad9e-494f-a429-e902e02d1a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635933554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3635933554
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.1327575103
Short name T243
Test name
Test status
Simulation time 11722000 ps
CPU time 22.09 seconds
Started Feb 21 01:10:42 PM PST 24
Finished Feb 21 01:11:05 PM PST 24
Peak memory 279592 kb
Host smart-e52e6e61-63a7-4b2b-8f8a-a4bc25f7612f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327575103 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.1327575103
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.2425200585
Short name T477
Test name
Test status
Simulation time 36324407600 ps
CPU time 120.52 seconds
Started Feb 21 01:10:44 PM PST 24
Finished Feb 21 01:12:45 PM PST 24
Peak memory 261572 kb
Host smart-59ec6d27-e958-4720-a291-f59ae181d097
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425200585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.2425200585
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.2706274380
Short name T820
Test name
Test status
Simulation time 38364700 ps
CPU time 129.53 seconds
Started Feb 21 01:10:47 PM PST 24
Finished Feb 21 01:12:57 PM PST 24
Peak memory 261632 kb
Host smart-6c2622e6-6497-4b43-87e5-faa2b4b4d70b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706274380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.2706274380
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.1403147880
Short name T394
Test name
Test status
Simulation time 1304749900 ps
CPU time 67.93 seconds
Started Feb 21 01:10:41 PM PST 24
Finished Feb 21 01:11:50 PM PST 24
Peak memory 263408 kb
Host smart-3938b7de-e5dd-4ae3-aeb6-2f810258531d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403147880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1403147880
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.4233853757
Short name T1059
Test name
Test status
Simulation time 126617000 ps
CPU time 145.67 seconds
Started Feb 21 01:10:42 PM PST 24
Finished Feb 21 01:13:08 PM PST 24
Peak memory 275044 kb
Host smart-4ce30857-cc71-4e98-903f-1b2ccf1e85e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233853757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.4233853757
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.1013804231
Short name T719
Test name
Test status
Simulation time 34195100 ps
CPU time 13.82 seconds
Started Feb 21 01:10:46 PM PST 24
Finished Feb 21 01:11:01 PM PST 24
Peak memory 264024 kb
Host smart-555ebc11-3aa2-4876-8c8d-50b6c2eafc06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013804231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
1013804231
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.1205969395
Short name T317
Test name
Test status
Simulation time 70261000 ps
CPU time 13.45 seconds
Started Feb 21 01:10:45 PM PST 24
Finished Feb 21 01:10:59 PM PST 24
Peak memory 274228 kb
Host smart-f9207fd7-8d6b-48b8-87c8-2becd8283413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205969395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.1205969395
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.333906705
Short name T1089
Test name
Test status
Simulation time 11842600 ps
CPU time 21.85 seconds
Started Feb 21 01:10:42 PM PST 24
Finished Feb 21 01:11:04 PM PST 24
Peak memory 279800 kb
Host smart-71648441-5522-456b-893a-27ee7bf6ac50
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333906705 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.333906705
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.3622283617
Short name T284
Test name
Test status
Simulation time 11866489200 ps
CPU time 250.1 seconds
Started Feb 21 01:10:44 PM PST 24
Finished Feb 21 01:14:55 PM PST 24
Peak memory 261276 kb
Host smart-d8633935-bfa1-4882-adf2-ce502cc8b1af
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622283617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.3622283617
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.3077506988
Short name T453
Test name
Test status
Simulation time 39996900 ps
CPU time 134.48 seconds
Started Feb 21 01:10:44 PM PST 24
Finished Feb 21 01:12:59 PM PST 24
Peak memory 261584 kb
Host smart-48b2fb67-7507-450c-bb35-b038aff0196b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077506988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.3077506988
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.2596175273
Short name T181
Test name
Test status
Simulation time 1811062000 ps
CPU time 70.95 seconds
Started Feb 21 01:10:41 PM PST 24
Finished Feb 21 01:11:53 PM PST 24
Peak memory 262460 kb
Host smart-3669dbf2-6ceb-47ee-b65f-bfd51118c980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596175273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.2596175273
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.3760337536
Short name T942
Test name
Test status
Simulation time 50880500 ps
CPU time 149.69 seconds
Started Feb 21 01:10:44 PM PST 24
Finished Feb 21 01:13:14 PM PST 24
Peak memory 276308 kb
Host smart-65ed2cdd-d9ab-47a0-a71d-cf2af0549270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760337536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.3760337536
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.3496204000
Short name T625
Test name
Test status
Simulation time 135442700 ps
CPU time 13.96 seconds
Started Feb 21 01:05:01 PM PST 24
Finished Feb 21 01:05:16 PM PST 24
Peak memory 264120 kb
Host smart-6c2d06e1-5e6c-439d-9b11-90588c7d1029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496204000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.3
496204000
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.1916207138
Short name T774
Test name
Test status
Simulation time 15712600 ps
CPU time 15.67 seconds
Started Feb 21 01:04:47 PM PST 24
Finished Feb 21 01:05:03 PM PST 24
Peak memory 274872 kb
Host smart-222fa238-3907-4c9c-9f06-c64316a19c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916207138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1916207138
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.2222888148
Short name T921
Test name
Test status
Simulation time 37393100 ps
CPU time 21.78 seconds
Started Feb 21 01:04:47 PM PST 24
Finished Feb 21 01:05:09 PM PST 24
Peak memory 272720 kb
Host smart-aef4f254-1418-4702-830a-629b8a6b5188
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222888148 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.2222888148
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.2294101733
Short name T72
Test name
Test status
Simulation time 4055838700 ps
CPU time 2177.68 seconds
Started Feb 21 01:05:06 PM PST 24
Finished Feb 21 01:41:24 PM PST 24
Peak memory 264320 kb
Host smart-a021d751-800c-4ad2-b50a-f892aefe28ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294101733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.2294101733
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.2455440594
Short name T913
Test name
Test status
Simulation time 9549882000 ps
CPU time 806.79 seconds
Started Feb 21 01:04:45 PM PST 24
Finished Feb 21 01:18:13 PM PST 24
Peak memory 272840 kb
Host smart-60349d50-64ac-4d4d-aced-fa8165f9df50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455440594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2455440594
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.210579176
Short name T43
Test name
Test status
Simulation time 1353415500 ps
CPU time 24.98 seconds
Started Feb 21 01:04:47 PM PST 24
Finished Feb 21 01:05:12 PM PST 24
Peak memory 264400 kb
Host smart-dc51fb1f-6285-4250-b055-5d5aeeb030f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210579176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.210579176
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3143039758
Short name T155
Test name
Test status
Simulation time 10018887000 ps
CPU time 77.48 seconds
Started Feb 21 01:04:49 PM PST 24
Finished Feb 21 01:06:07 PM PST 24
Peak memory 304296 kb
Host smart-cf7c7b62-8c7f-4f80-9726-be62c169d947
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143039758 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.3143039758
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.3393481923
Short name T347
Test name
Test status
Simulation time 15685100 ps
CPU time 13.52 seconds
Started Feb 21 01:04:45 PM PST 24
Finished Feb 21 01:04:59 PM PST 24
Peak memory 264348 kb
Host smart-3126da1a-e3b9-4012-b14e-234ed88ac15c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393481923 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.3393481923
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.1998870381
Short name T175
Test name
Test status
Simulation time 630468401000 ps
CPU time 1258.62 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 01:25:39 PM PST 24
Peak memory 258320 kb
Host smart-23a99a47-0c77-48db-933d-e4e974b815c4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998870381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.1998870381
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.3583162777
Short name T28
Test name
Test status
Simulation time 12044451000 ps
CPU time 122.17 seconds
Started Feb 21 01:04:38 PM PST 24
Finished Feb 21 01:06:42 PM PST 24
Peak memory 261488 kb
Host smart-7fb55530-4922-4489-98dd-6715bd7c5ce4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583162777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.3583162777
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.754994011
Short name T718
Test name
Test status
Simulation time 2182420800 ps
CPU time 180.12 seconds
Started Feb 21 01:05:05 PM PST 24
Finished Feb 21 01:08:05 PM PST 24
Peak memory 289084 kb
Host smart-8dd200c3-aac5-46f7-9925-e7eb94a3e537
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754994011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_intr_rd.754994011
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1561799713
Short name T1064
Test name
Test status
Simulation time 8808940100 ps
CPU time 240.8 seconds
Started Feb 21 01:05:04 PM PST 24
Finished Feb 21 01:09:06 PM PST 24
Peak memory 283888 kb
Host smart-7ce257b8-a8b7-42b0-9111-67316d7d65a0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561799713 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.1561799713
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.3004397747
Short name T907
Test name
Test status
Simulation time 4014392500 ps
CPU time 98.05 seconds
Started Feb 21 01:04:47 PM PST 24
Finished Feb 21 01:06:26 PM PST 24
Peak memory 264432 kb
Host smart-0e31447b-e864-4382-accb-92205626e0a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004397747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.3004397747
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.4030716279
Short name T629
Test name
Test status
Simulation time 1660115500 ps
CPU time 72 seconds
Started Feb 21 01:04:47 PM PST 24
Finished Feb 21 01:05:59 PM PST 24
Peak memory 259804 kb
Host smart-52a2e4dd-9b83-4ba9-afc6-4bc760d0b9aa
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030716279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.4030716279
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.3030308355
Short name T104
Test name
Test status
Simulation time 33089268600 ps
CPU time 240.31 seconds
Started Feb 21 01:04:45 PM PST 24
Finished Feb 21 01:08:46 PM PST 24
Peak memory 272904 kb
Host smart-c6e364a3-242c-423f-9296-69d0728c5b1f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030308355 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.3030308355
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.1447786049
Short name T1088
Test name
Test status
Simulation time 39420100 ps
CPU time 134.57 seconds
Started Feb 21 01:04:38 PM PST 24
Finished Feb 21 01:06:55 PM PST 24
Peak memory 258828 kb
Host smart-398b531f-079f-44ec-9d53-4c1136d060ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447786049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.1447786049
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.786295922
Short name T988
Test name
Test status
Simulation time 714324700 ps
CPU time 161.78 seconds
Started Feb 21 01:04:38 PM PST 24
Finished Feb 21 01:07:22 PM PST 24
Peak memory 260612 kb
Host smart-c2e69a76-362b-4645-877c-17ed4f8ae975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786295922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.786295922
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.849924872
Short name T768
Test name
Test status
Simulation time 81330300 ps
CPU time 13.99 seconds
Started Feb 21 01:04:48 PM PST 24
Finished Feb 21 01:05:03 PM PST 24
Peak memory 264352 kb
Host smart-94cb1538-d5fc-4bf3-aff2-ac5bd660b1cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849924872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_rese
t.849924872
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.2687659881
Short name T926
Test name
Test status
Simulation time 310255000 ps
CPU time 899.63 seconds
Started Feb 21 01:04:38 PM PST 24
Finished Feb 21 01:19:40 PM PST 24
Peak memory 281308 kb
Host smart-fdc8ef6c-e4e3-4deb-91d5-6e52282d1981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687659881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.2687659881
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.2870602461
Short name T827
Test name
Test status
Simulation time 97941300 ps
CPU time 36.8 seconds
Started Feb 21 01:04:48 PM PST 24
Finished Feb 21 01:05:26 PM PST 24
Peak memory 265612 kb
Host smart-f77193ea-47dd-4407-b464-96c2a1372266
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870602461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.2870602461
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.2343703821
Short name T711
Test name
Test status
Simulation time 489452200 ps
CPU time 103.81 seconds
Started Feb 21 01:05:06 PM PST 24
Finished Feb 21 01:06:50 PM PST 24
Peak memory 280120 kb
Host smart-d8c51278-f4d7-4151-93f0-16ec47d1111e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343703821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_ro.2343703821
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.227476043
Short name T205
Test name
Test status
Simulation time 514887400 ps
CPU time 106.69 seconds
Started Feb 21 01:04:56 PM PST 24
Finished Feb 21 01:06:44 PM PST 24
Peak memory 280952 kb
Host smart-348a832d-2607-435b-999a-d6929cf34155
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
227476043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.227476043
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.2436227715
Short name T995
Test name
Test status
Simulation time 7205124000 ps
CPU time 553.43 seconds
Started Feb 21 01:04:47 PM PST 24
Finished Feb 21 01:14:00 PM PST 24
Peak memory 313668 kb
Host smart-d83f2d71-e65e-45c9-8bec-6c1d488d1f8f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436227715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct
rl_rw.2436227715
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.706260383
Short name T911
Test name
Test status
Simulation time 10532519300 ps
CPU time 553.33 seconds
Started Feb 21 01:04:50 PM PST 24
Finished Feb 21 01:14:05 PM PST 24
Peak memory 330344 kb
Host smart-681b9cb2-8014-4d6c-a377-7808eb5bb441
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706260383 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.flash_ctrl_rw_derr.706260383
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.532005658
Short name T1047
Test name
Test status
Simulation time 50949100 ps
CPU time 33.02 seconds
Started Feb 21 01:04:46 PM PST 24
Finished Feb 21 01:05:20 PM PST 24
Peak memory 273796 kb
Host smart-3e92daa8-a4cf-40e5-9e62-20633570ac9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532005658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_rw_evict.532005658
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3252010814
Short name T982
Test name
Test status
Simulation time 42479800 ps
CPU time 30.61 seconds
Started Feb 21 01:04:48 PM PST 24
Finished Feb 21 01:05:19 PM PST 24
Peak memory 272776 kb
Host smart-d1bf8acb-695c-4783-88ea-fc39e01cb1a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252010814 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.3252010814
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.4198093873
Short name T886
Test name
Test status
Simulation time 3177427900 ps
CPU time 617.69 seconds
Started Feb 21 01:04:47 PM PST 24
Finished Feb 21 01:15:06 PM PST 24
Peak memory 311332 kb
Host smart-cc2b9c0b-1da3-416d-ac80-0bee8dda0deb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198093873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.4198093873
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.369860462
Short name T179
Test name
Test status
Simulation time 949630900 ps
CPU time 56.76 seconds
Started Feb 21 01:04:45 PM PST 24
Finished Feb 21 01:05:43 PM PST 24
Peak memory 258796 kb
Host smart-d9ce9097-81d9-4c99-bfe1-0625c2a960b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369860462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.369860462
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.879029382
Short name T1102
Test name
Test status
Simulation time 80527800 ps
CPU time 50.8 seconds
Started Feb 21 01:04:36 PM PST 24
Finished Feb 21 01:05:29 PM PST 24
Peak memory 269720 kb
Host smart-1868faa4-47cc-47e2-aed3-06c777e344ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879029382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.879029382
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.550220912
Short name T517
Test name
Test status
Simulation time 1867972900 ps
CPU time 157.84 seconds
Started Feb 21 01:04:48 PM PST 24
Finished Feb 21 01:07:26 PM PST 24
Peak memory 264376 kb
Host smart-69762daf-7d93-41da-84df-8f70b6533081
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550220912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_wo.550220912
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.1826327803
Short name T478
Test name
Test status
Simulation time 145417200 ps
CPU time 15.7 seconds
Started Feb 21 01:10:44 PM PST 24
Finished Feb 21 01:11:00 PM PST 24
Peak memory 273864 kb
Host smart-2c796cce-6bb0-4917-bf53-334d634b4880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826327803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1826327803
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.3556602935
Short name T974
Test name
Test status
Simulation time 78257500 ps
CPU time 137.95 seconds
Started Feb 21 01:10:45 PM PST 24
Finished Feb 21 01:13:04 PM PST 24
Peak memory 259988 kb
Host smart-5d549bbd-2392-4bac-8b53-b1db08889136
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556602935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.3556602935
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.3869041862
Short name T853
Test name
Test status
Simulation time 25566100 ps
CPU time 13.2 seconds
Started Feb 21 01:10:47 PM PST 24
Finished Feb 21 01:11:01 PM PST 24
Peak memory 274332 kb
Host smart-206ababe-0f5d-4d67-940a-da438b0044e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869041862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3869041862
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.3502996928
Short name T842
Test name
Test status
Simulation time 117427200 ps
CPU time 137.95 seconds
Started Feb 21 01:10:44 PM PST 24
Finished Feb 21 01:13:02 PM PST 24
Peak memory 258888 kb
Host smart-713362f7-684a-4d5a-8115-e02507bf5004
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502996928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.3502996928
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.4254183410
Short name T1113
Test name
Test status
Simulation time 15541600 ps
CPU time 15.6 seconds
Started Feb 21 01:10:47 PM PST 24
Finished Feb 21 01:11:04 PM PST 24
Peak memory 275136 kb
Host smart-42f543ac-64ae-45f3-8b6a-73adf5d25f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254183410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.4254183410
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.3083178328
Short name T389
Test name
Test status
Simulation time 144758500 ps
CPU time 135.16 seconds
Started Feb 21 01:10:43 PM PST 24
Finished Feb 21 01:12:59 PM PST 24
Peak memory 258912 kb
Host smart-a42a0445-a59a-4a50-9319-a8306feefbe9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083178328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.3083178328
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.475721342
Short name T1018
Test name
Test status
Simulation time 25136200 ps
CPU time 15.55 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:11:09 PM PST 24
Peak memory 274772 kb
Host smart-bf9ae850-a379-4110-863f-40543de5a4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475721342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.475721342
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.1095630061
Short name T390
Test name
Test status
Simulation time 154041200 ps
CPU time 133.76 seconds
Started Feb 21 01:10:54 PM PST 24
Finished Feb 21 01:13:08 PM PST 24
Peak memory 262352 kb
Host smart-e16ddd56-908d-4f96-b1f7-8728447a07d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095630061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.1095630061
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.1064871739
Short name T321
Test name
Test status
Simulation time 45889600 ps
CPU time 13.48 seconds
Started Feb 21 01:10:52 PM PST 24
Finished Feb 21 01:11:06 PM PST 24
Peak memory 275132 kb
Host smart-f4c068c8-b688-42db-97d2-78ed95bcf3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064871739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1064871739
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.4164930812
Short name T987
Test name
Test status
Simulation time 135073700 ps
CPU time 134.31 seconds
Started Feb 21 01:10:54 PM PST 24
Finished Feb 21 01:13:08 PM PST 24
Peak memory 258472 kb
Host smart-e79800b3-ee4d-413c-8c93-7e81683c1324
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164930812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.4164930812
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.2281291674
Short name T847
Test name
Test status
Simulation time 19516100 ps
CPU time 15.97 seconds
Started Feb 21 01:10:49 PM PST 24
Finished Feb 21 01:11:05 PM PST 24
Peak memory 273824 kb
Host smart-b1326f86-ed98-4b57-b9dd-359ca67cf520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281291674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2281291674
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.3875866629
Short name T62
Test name
Test status
Simulation time 39292000 ps
CPU time 134.5 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:13:08 PM PST 24
Peak memory 259048 kb
Host smart-180212ff-0bb9-46e9-83b7-33f5e899c549
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875866629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.3875866629
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.2754920517
Short name T918
Test name
Test status
Simulation time 22038300 ps
CPU time 15.41 seconds
Started Feb 21 01:10:49 PM PST 24
Finished Feb 21 01:11:05 PM PST 24
Peak memory 274856 kb
Host smart-fcef2c20-a310-4f98-9e8c-b37f7ab8d2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754920517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2754920517
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.922661202
Short name T618
Test name
Test status
Simulation time 92660700 ps
CPU time 132 seconds
Started Feb 21 01:10:51 PM PST 24
Finished Feb 21 01:13:03 PM PST 24
Peak memory 259976 kb
Host smart-d122783f-a42c-4034-8135-db0979f1acce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922661202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_ot
p_reset.922661202
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.438142319
Short name T622
Test name
Test status
Simulation time 14128400 ps
CPU time 15.65 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:11:09 PM PST 24
Peak memory 273984 kb
Host smart-d5435adc-2e9d-403b-8792-add841727026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438142319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.438142319
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.2299174990
Short name T96
Test name
Test status
Simulation time 66075000 ps
CPU time 136.64 seconds
Started Feb 21 01:10:54 PM PST 24
Finished Feb 21 01:13:11 PM PST 24
Peak memory 258596 kb
Host smart-fc89b55d-c963-4ace-b7a2-25a0e14f4f16
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299174990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.2299174990
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.3102836302
Short name T934
Test name
Test status
Simulation time 28154500 ps
CPU time 16.13 seconds
Started Feb 21 01:10:49 PM PST 24
Finished Feb 21 01:11:05 PM PST 24
Peak memory 274252 kb
Host smart-8cf8c5c9-ab4c-424a-88cc-bd8d8c069c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102836302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.3102836302
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.1070567453
Short name T1131
Test name
Test status
Simulation time 50946300 ps
CPU time 134.41 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:13:07 PM PST 24
Peak memory 260124 kb
Host smart-96aa2e5d-09d2-443e-8c79-ee964d200d44
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070567453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.1070567453
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.1348747532
Short name T845
Test name
Test status
Simulation time 14230000 ps
CPU time 15.8 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:11:10 PM PST 24
Peak memory 275092 kb
Host smart-fe1d853f-cf9c-438b-b30b-2b7f5b5f4b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348747532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.1348747532
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.2177400069
Short name T996
Test name
Test status
Simulation time 155802900 ps
CPU time 131.64 seconds
Started Feb 21 01:10:52 PM PST 24
Finished Feb 21 01:13:04 PM PST 24
Peak memory 258976 kb
Host smart-83bd4eb3-f024-445a-9f03-743a93842659
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177400069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.2177400069
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.1527664283
Short name T496
Test name
Test status
Simulation time 62052000 ps
CPU time 13.94 seconds
Started Feb 21 01:05:21 PM PST 24
Finished Feb 21 01:05:36 PM PST 24
Peak memory 264484 kb
Host smart-f66ebedb-0a1b-44a7-bab5-a31a8bdacda8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527664283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.1
527664283
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.1278858703
Short name T822
Test name
Test status
Simulation time 18157300 ps
CPU time 15.71 seconds
Started Feb 21 01:05:25 PM PST 24
Finished Feb 21 01:05:41 PM PST 24
Peak memory 273988 kb
Host smart-3c8e38f2-8805-4230-8d23-7e53f334d25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278858703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1278858703
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.1306799091
Short name T100
Test name
Test status
Simulation time 20528800 ps
CPU time 21.39 seconds
Started Feb 21 01:05:23 PM PST 24
Finished Feb 21 01:05:45 PM PST 24
Peak memory 272936 kb
Host smart-869f50ca-f0a1-4bc6-8d72-cb550ff27f32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306799091 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.1306799091
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.761836973
Short name T1122
Test name
Test status
Simulation time 5278126200 ps
CPU time 2269.62 seconds
Started Feb 21 01:05:03 PM PST 24
Finished Feb 21 01:42:54 PM PST 24
Peak memory 264428 kb
Host smart-6ce05f1a-dc68-49a8-9ed7-12afdc1b73e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761836973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_erro
r_mp.761836973
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.1500723834
Short name T854
Test name
Test status
Simulation time 1595457800 ps
CPU time 975.96 seconds
Started Feb 21 01:05:03 PM PST 24
Finished Feb 21 01:21:20 PM PST 24
Peak memory 264588 kb
Host smart-5491c0d4-7eeb-470e-b2e1-a2faa18b71d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500723834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.1500723834
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.647229732
Short name T862
Test name
Test status
Simulation time 333080900 ps
CPU time 22.38 seconds
Started Feb 21 01:05:04 PM PST 24
Finished Feb 21 01:05:27 PM PST 24
Peak memory 264444 kb
Host smart-4501675e-1827-4236-a86e-fcbbb8a835ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647229732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.647229732
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3881803310
Short name T867
Test name
Test status
Simulation time 10019783300 ps
CPU time 82.64 seconds
Started Feb 21 01:05:24 PM PST 24
Finished Feb 21 01:06:47 PM PST 24
Peak memory 312332 kb
Host smart-ec072f6b-e050-4062-8476-e62902f03c11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881803310 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3881803310
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.1513142401
Short name T292
Test name
Test status
Simulation time 15559400 ps
CPU time 13.45 seconds
Started Feb 21 01:05:21 PM PST 24
Finished Feb 21 01:05:36 PM PST 24
Peak memory 264516 kb
Host smart-34cf67e1-fb44-4ff8-8ffa-c928658bcc3b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513142401 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.1513142401
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.460879559
Short name T148
Test name
Test status
Simulation time 80140031800 ps
CPU time 696.22 seconds
Started Feb 21 01:05:04 PM PST 24
Finished Feb 21 01:16:41 PM PST 24
Peak memory 258300 kb
Host smart-13022003-a435-46a2-a2f8-c191e670b583
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460879559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.flash_ctrl_hw_rma_reset.460879559
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.2985538324
Short name T315
Test name
Test status
Simulation time 6366817600 ps
CPU time 96.55 seconds
Started Feb 21 01:05:02 PM PST 24
Finished Feb 21 01:06:39 PM PST 24
Peak memory 261504 kb
Host smart-c82f0054-b3dc-472c-823b-a8c02139bf06
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985538324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.2985538324
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.3168320301
Short name T487
Test name
Test status
Simulation time 975437300 ps
CPU time 141.69 seconds
Started Feb 21 01:05:03 PM PST 24
Finished Feb 21 01:07:26 PM PST 24
Peak memory 291876 kb
Host smart-488f2495-b024-432c-865c-d1a26548c40d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168320301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.3168320301
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1729453535
Short name T587
Test name
Test status
Simulation time 18400364500 ps
CPU time 231.75 seconds
Started Feb 21 01:05:03 PM PST 24
Finished Feb 21 01:08:56 PM PST 24
Peak memory 283740 kb
Host smart-41c4e953-c863-4147-b57b-6ea3d748864b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729453535 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.1729453535
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.655878047
Short name T637
Test name
Test status
Simulation time 4697787800 ps
CPU time 116.59 seconds
Started Feb 21 01:05:02 PM PST 24
Finished Feb 21 01:06:59 PM PST 24
Peak memory 264368 kb
Host smart-7f8bfcd8-f0eb-45d2-b8f7-017adef50992
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655878047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.flash_ctrl_intr_wr.655878047
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3446975812
Short name T792
Test name
Test status
Simulation time 180681741000 ps
CPU time 549.87 seconds
Started Feb 21 01:05:06 PM PST 24
Finished Feb 21 01:14:16 PM PST 24
Peak memory 264392 kb
Host smart-b08faee3-115d-4758-a561-cd937162e0f5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344
6975812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.3446975812
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.2539275248
Short name T898
Test name
Test status
Simulation time 8673009300 ps
CPU time 61.97 seconds
Started Feb 21 01:05:02 PM PST 24
Finished Feb 21 01:06:04 PM PST 24
Peak memory 259040 kb
Host smart-e4f6c288-1163-437d-9174-308a849725c3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539275248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.2539275248
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.1386449937
Short name T669
Test name
Test status
Simulation time 26396800 ps
CPU time 13.4 seconds
Started Feb 21 01:05:22 PM PST 24
Finished Feb 21 01:05:36 PM PST 24
Peak memory 264480 kb
Host smart-66737234-85b1-4c5b-a256-d1570d2a2dca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386449937 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.1386449937
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.3964685034
Short name T95
Test name
Test status
Simulation time 41093900 ps
CPU time 136.81 seconds
Started Feb 21 01:05:03 PM PST 24
Finished Feb 21 01:07:21 PM PST 24
Peak memory 258868 kb
Host smart-a7b49348-4bde-46a6-898c-51e574e6c639
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964685034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.3964685034
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.2054070159
Short name T946
Test name
Test status
Simulation time 104571300 ps
CPU time 66.65 seconds
Started Feb 21 01:05:02 PM PST 24
Finished Feb 21 01:06:09 PM PST 24
Peak memory 261496 kb
Host smart-b12e9898-5dd0-47b0-b41a-6f3f5b6de8f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054070159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.2054070159
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.1148290734
Short name T1027
Test name
Test status
Simulation time 38227000 ps
CPU time 13.78 seconds
Started Feb 21 01:05:04 PM PST 24
Finished Feb 21 01:05:18 PM PST 24
Peak memory 264284 kb
Host smart-4e5e438a-48da-4399-98aa-e46f2ddbda9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148290734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.1148290734
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.3153023246
Short name T102
Test name
Test status
Simulation time 51449100 ps
CPU time 76.79 seconds
Started Feb 21 01:05:02 PM PST 24
Finished Feb 21 01:06:20 PM PST 24
Peak memory 277852 kb
Host smart-2faad5df-e364-4011-bf84-59794ce84557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153023246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.3153023246
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.785782872
Short name T388
Test name
Test status
Simulation time 135839500 ps
CPU time 38.34 seconds
Started Feb 21 01:05:23 PM PST 24
Finished Feb 21 01:06:03 PM PST 24
Peak memory 276312 kb
Host smart-f57cdaea-fcbd-4106-b8ec-7e0f9f3ed9ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785782872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_re_evict.785782872
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.2950383743
Short name T795
Test name
Test status
Simulation time 852439800 ps
CPU time 106.34 seconds
Started Feb 21 01:05:04 PM PST 24
Finished Feb 21 01:06:51 PM PST 24
Peak memory 280908 kb
Host smart-cdb36678-5517-45ac-a945-f5c0392957c6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950383743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_ro.2950383743
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.1602430201
Short name T1077
Test name
Test status
Simulation time 1741234300 ps
CPU time 136.35 seconds
Started Feb 21 01:05:03 PM PST 24
Finished Feb 21 01:07:20 PM PST 24
Peak memory 281400 kb
Host smart-90266492-69d6-40a5-9bc2-00c4e31d66f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1602430201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.1602430201
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.1032562147
Short name T19
Test name
Test status
Simulation time 2449277500 ps
CPU time 131.02 seconds
Started Feb 21 01:05:04 PM PST 24
Finished Feb 21 01:07:16 PM PST 24
Peak memory 293488 kb
Host smart-0654485c-52e2-48e2-8eb8-49bc16ee662b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032562147 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.1032562147
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.572501253
Short name T85
Test name
Test status
Simulation time 7794627600 ps
CPU time 584.82 seconds
Started Feb 21 01:05:03 PM PST 24
Finished Feb 21 01:14:49 PM PST 24
Peak memory 313620 kb
Host smart-60030984-7023-4f3d-8c63-01b3802f18c0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572501253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctr
l_rw.572501253
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.126247330
Short name T83
Test name
Test status
Simulation time 5051955700 ps
CPU time 530.45 seconds
Started Feb 21 01:05:04 PM PST 24
Finished Feb 21 01:13:56 PM PST 24
Peak memory 325612 kb
Host smart-3df38e8b-95b6-4b08-8643-e6c91cb6ce12
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126247330 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_rw_derr.126247330
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.2249781397
Short name T884
Test name
Test status
Simulation time 50041800 ps
CPU time 32.51 seconds
Started Feb 21 01:05:23 PM PST 24
Finished Feb 21 01:05:57 PM PST 24
Peak memory 277388 kb
Host smart-f20e6a95-49e6-4b61-8af5-aba6d4df990c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249781397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.2249781397
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.244252688
Short name T708
Test name
Test status
Simulation time 30351200 ps
CPU time 31.38 seconds
Started Feb 21 01:05:29 PM PST 24
Finished Feb 21 01:06:01 PM PST 24
Peak memory 273712 kb
Host smart-3716ea0b-63b2-4aab-8701-0a30a577bdff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244252688 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.244252688
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.3136438498
Short name T603
Test name
Test status
Simulation time 31330789000 ps
CPU time 610.97 seconds
Started Feb 21 01:05:04 PM PST 24
Finished Feb 21 01:15:16 PM PST 24
Peak memory 319384 kb
Host smart-556bd866-69ec-47b8-95c7-569c736cd119
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136438498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.3136438498
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.862453307
Short name T782
Test name
Test status
Simulation time 753246500 ps
CPU time 54.25 seconds
Started Feb 21 01:05:24 PM PST 24
Finished Feb 21 01:06:19 PM PST 24
Peak memory 258776 kb
Host smart-45f0a43e-27a1-4ba4-81d5-ae521ae0e47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862453307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.862453307
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.1445218383
Short name T537
Test name
Test status
Simulation time 66171000 ps
CPU time 73.19 seconds
Started Feb 21 01:05:07 PM PST 24
Finished Feb 21 01:06:22 PM PST 24
Peak memory 274328 kb
Host smart-b9b12b89-fbb8-452d-ad9e-7fb9154fe18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445218383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.1445218383
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.1266037867
Short name T605
Test name
Test status
Simulation time 29352135400 ps
CPU time 152.08 seconds
Started Feb 21 01:05:03 PM PST 24
Finished Feb 21 01:07:36 PM PST 24
Peak memory 264416 kb
Host smart-52867b95-596a-470a-8883-c4b7837f6efc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266037867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.flash_ctrl_wo.1266037867
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.2059903492
Short name T741
Test name
Test status
Simulation time 91474500 ps
CPU time 15.58 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:11:09 PM PST 24
Peak memory 274256 kb
Host smart-4dd53301-7a74-4f23-ac8f-0349ba7896ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059903492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.2059903492
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.4099506053
Short name T1011
Test name
Test status
Simulation time 15153900 ps
CPU time 15.39 seconds
Started Feb 21 01:10:47 PM PST 24
Finished Feb 21 01:11:03 PM PST 24
Peak memory 275020 kb
Host smart-f2e1f950-a107-4098-8d08-a5ad0f1d5058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099506053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.4099506053
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.3408355491
Short name T555
Test name
Test status
Simulation time 424404500 ps
CPU time 136.62 seconds
Started Feb 21 01:10:49 PM PST 24
Finished Feb 21 01:13:06 PM PST 24
Peak memory 259072 kb
Host smart-9c2b6d96-8228-43fa-b67a-f24aa7b873fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408355491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.3408355491
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.1415628507
Short name T521
Test name
Test status
Simulation time 24189700 ps
CPU time 15.46 seconds
Started Feb 21 01:10:48 PM PST 24
Finished Feb 21 01:11:04 PM PST 24
Peak memory 274848 kb
Host smart-4b3cdf70-892e-43e4-baf4-86610fd9fe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415628507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.1415628507
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.4144840691
Short name T809
Test name
Test status
Simulation time 68140400 ps
CPU time 131.8 seconds
Started Feb 21 01:10:48 PM PST 24
Finished Feb 21 01:13:00 PM PST 24
Peak memory 258856 kb
Host smart-8cb49560-1388-49e5-9f3a-288f95cf0592
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144840691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.4144840691
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.1973112486
Short name T329
Test name
Test status
Simulation time 26011200 ps
CPU time 13.13 seconds
Started Feb 21 01:10:47 PM PST 24
Finished Feb 21 01:11:01 PM PST 24
Peak memory 273884 kb
Host smart-750f158d-747a-4bee-aa29-1c0fd1c3ca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973112486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1973112486
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.4194590064
Short name T834
Test name
Test status
Simulation time 283233200 ps
CPU time 110.49 seconds
Started Feb 21 01:10:50 PM PST 24
Finished Feb 21 01:12:41 PM PST 24
Peak memory 262904 kb
Host smart-3a26bc20-6f75-4b48-ab81-342a6b6b9633
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194590064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.4194590064
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.2540525779
Short name T715
Test name
Test status
Simulation time 43951500 ps
CPU time 15.66 seconds
Started Feb 21 01:10:50 PM PST 24
Finished Feb 21 01:11:06 PM PST 24
Peak memory 274816 kb
Host smart-62ddc45c-ec83-4911-9dc5-96d592b05eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540525779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.2540525779
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.3850828770
Short name T756
Test name
Test status
Simulation time 319584300 ps
CPU time 114.21 seconds
Started Feb 21 01:10:54 PM PST 24
Finished Feb 21 01:12:49 PM PST 24
Peak memory 258800 kb
Host smart-112581cb-5817-4140-a5bb-59e7820dd107
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850828770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.3850828770
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.3453300572
Short name T443
Test name
Test status
Simulation time 21933400 ps
CPU time 13.31 seconds
Started Feb 21 01:10:50 PM PST 24
Finished Feb 21 01:11:04 PM PST 24
Peak memory 274292 kb
Host smart-7c112869-255a-4804-9c8d-5aa3eebeed24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453300572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.3453300572
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.136502484
Short name T480
Test name
Test status
Simulation time 40416500 ps
CPU time 111.47 seconds
Started Feb 21 01:10:50 PM PST 24
Finished Feb 21 01:12:42 PM PST 24
Peak memory 258960 kb
Host smart-eac141fc-383b-4cf2-924a-16bb0dc46e96
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136502484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_ot
p_reset.136502484
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.3136932185
Short name T707
Test name
Test status
Simulation time 48864500 ps
CPU time 15.82 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:11:09 PM PST 24
Peak memory 273976 kb
Host smart-15dd2345-3db2-4fbb-98bf-597bd3cf314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136932185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.3136932185
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.3169849801
Short name T564
Test name
Test status
Simulation time 180079400 ps
CPU time 133.14 seconds
Started Feb 21 01:10:46 PM PST 24
Finished Feb 21 01:13:00 PM PST 24
Peak memory 259096 kb
Host smart-9e7ae1fe-451e-424f-9d81-92e6aeb7ee3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169849801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.3169849801
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.606641331
Short name T446
Test name
Test status
Simulation time 16956800 ps
CPU time 15.78 seconds
Started Feb 21 01:10:50 PM PST 24
Finished Feb 21 01:11:06 PM PST 24
Peak memory 274004 kb
Host smart-da604fc3-e855-4d67-be5b-f51de08badfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606641331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.606641331
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.1881165616
Short name T819
Test name
Test status
Simulation time 141900100 ps
CPU time 134.15 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:13:08 PM PST 24
Peak memory 258716 kb
Host smart-37adf8b9-6a42-455b-8210-be01f9be1630
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881165616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.1881165616
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.4251759822
Short name T955
Test name
Test status
Simulation time 13730700 ps
CPU time 15.61 seconds
Started Feb 21 01:10:50 PM PST 24
Finished Feb 21 01:11:06 PM PST 24
Peak memory 274224 kb
Host smart-1a985af4-15d8-484e-bf10-59b5da468345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251759822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.4251759822
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.2542116759
Short name T194
Test name
Test status
Simulation time 42336100 ps
CPU time 112.03 seconds
Started Feb 21 01:10:50 PM PST 24
Finished Feb 21 01:12:42 PM PST 24
Peak memory 259912 kb
Host smart-606acb68-c89d-44ef-9dd3-44182791311c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542116759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.2542116759
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.3887728285
Short name T705
Test name
Test status
Simulation time 59103500 ps
CPU time 16.18 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:11:10 PM PST 24
Peak memory 273868 kb
Host smart-dfac1215-d36e-4833-927a-d9b09195cdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887728285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3887728285
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.1431481226
Short name T1008
Test name
Test status
Simulation time 145398400 ps
CPU time 133.95 seconds
Started Feb 21 01:10:52 PM PST 24
Finished Feb 21 01:13:07 PM PST 24
Peak memory 258840 kb
Host smart-0e9def13-e108-4014-b1ef-225f112ba92c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431481226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.1431481226
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.4270038266
Short name T758
Test name
Test status
Simulation time 17516900 ps
CPU time 13.54 seconds
Started Feb 21 01:05:44 PM PST 24
Finished Feb 21 01:05:58 PM PST 24
Peak memory 264424 kb
Host smart-e3829808-e3fe-4a4f-a4c3-3d6919804514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270038266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.4
270038266
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.472157053
Short name T489
Test name
Test status
Simulation time 18859400 ps
CPU time 13.47 seconds
Started Feb 21 01:05:46 PM PST 24
Finished Feb 21 01:05:59 PM PST 24
Peak memory 274764 kb
Host smart-7e52887a-50ac-45a4-be59-3071040cbbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472157053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.472157053
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.2178286757
Short name T376
Test name
Test status
Simulation time 12824400 ps
CPU time 21.15 seconds
Started Feb 21 01:05:21 PM PST 24
Finished Feb 21 01:05:43 PM PST 24
Peak memory 272748 kb
Host smart-145da34f-bc4e-4a64-85a7-f1cbe8b6abdf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178286757 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.2178286757
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.3548945307
Short name T228
Test name
Test status
Simulation time 5803829800 ps
CPU time 2178.91 seconds
Started Feb 21 01:05:22 PM PST 24
Finished Feb 21 01:41:42 PM PST 24
Peak memory 264156 kb
Host smart-c6bea0a9-d510-41d9-abf6-8f30b145341e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548945307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.3548945307
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.3450620112
Short name T185
Test name
Test status
Simulation time 303670400 ps
CPU time 798.77 seconds
Started Feb 21 01:05:23 PM PST 24
Finished Feb 21 01:18:43 PM PST 24
Peak memory 263132 kb
Host smart-ce0e063e-37ec-4bd4-a22b-2e70876a06d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450620112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3450620112
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.3064187300
Short name T958
Test name
Test status
Simulation time 689599500 ps
CPU time 25.39 seconds
Started Feb 21 01:05:21 PM PST 24
Finished Feb 21 01:05:48 PM PST 24
Peak memory 264412 kb
Host smart-8143a0f9-03c2-4379-bdaa-a1af59da44d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064187300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.3064187300
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2248857974
Short name T858
Test name
Test status
Simulation time 10012450400 ps
CPU time 119.16 seconds
Started Feb 21 01:05:40 PM PST 24
Finished Feb 21 01:07:40 PM PST 24
Peak memory 311804 kb
Host smart-9fb0d21a-0bdf-4b15-ad2e-2ec74c248e81
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248857974 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2248857974
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.4261940095
Short name T293
Test name
Test status
Simulation time 48260500 ps
CPU time 13.35 seconds
Started Feb 21 01:05:41 PM PST 24
Finished Feb 21 01:05:55 PM PST 24
Peak memory 263656 kb
Host smart-86f5f601-76c8-4002-ae0e-afc9991f0044
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261940095 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.4261940095
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.250026681
Short name T1114
Test name
Test status
Simulation time 40121768700 ps
CPU time 683.5 seconds
Started Feb 21 01:05:27 PM PST 24
Finished Feb 21 01:16:51 PM PST 24
Peak memory 261688 kb
Host smart-af29bfdb-a45b-4357-b8a9-190676be4308
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250026681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.flash_ctrl_hw_rma_reset.250026681
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.620308917
Short name T764
Test name
Test status
Simulation time 605669000 ps
CPU time 32.38 seconds
Started Feb 21 01:05:23 PM PST 24
Finished Feb 21 01:05:57 PM PST 24
Peak memory 258384 kb
Host smart-b2cb7876-e183-4ac0-97ce-d992c59fc0e4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620308917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw
_sec_otp.620308917
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.2852116777
Short name T7
Test name
Test status
Simulation time 5203435100 ps
CPU time 164.74 seconds
Started Feb 21 01:05:23 PM PST 24
Finished Feb 21 01:08:08 PM PST 24
Peak memory 292236 kb
Host smart-82e6172e-0e63-4f9a-b9a5-2b0db7fea66e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852116777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.2852116777
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1987871213
Short name T585
Test name
Test status
Simulation time 8963397100 ps
CPU time 234.87 seconds
Started Feb 21 01:05:25 PM PST 24
Finished Feb 21 01:09:20 PM PST 24
Peak memory 292916 kb
Host smart-e51a8996-e9f7-49f0-b83e-c881a46d5698
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987871213 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.1987871213
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.498648008
Short name T945
Test name
Test status
Simulation time 8732448200 ps
CPU time 108.48 seconds
Started Feb 21 01:05:22 PM PST 24
Finished Feb 21 01:07:11 PM PST 24
Peak memory 264420 kb
Host smart-a5465dec-3930-47aa-940a-cea1fbf65b48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498648008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.flash_ctrl_intr_wr.498648008
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2808401838
Short name T771
Test name
Test status
Simulation time 90529170700 ps
CPU time 348.91 seconds
Started Feb 21 01:05:29 PM PST 24
Finished Feb 21 01:11:19 PM PST 24
Peak memory 264308 kb
Host smart-21225c49-a987-44b8-8d60-43072926c326
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280
8401838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.2808401838
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.2927855609
Short name T1043
Test name
Test status
Simulation time 18030856300 ps
CPU time 68.38 seconds
Started Feb 21 01:05:22 PM PST 24
Finished Feb 21 01:06:31 PM PST 24
Peak memory 259628 kb
Host smart-3a940c50-a90b-41b0-b2f7-c2946c8ad0ba
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927855609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2927855609
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.4079127215
Short name T608
Test name
Test status
Simulation time 26537600 ps
CPU time 13.25 seconds
Started Feb 21 01:05:47 PM PST 24
Finished Feb 21 01:06:01 PM PST 24
Peak memory 264436 kb
Host smart-44b98ddb-09f1-40e0-9c59-889e1a25dbad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079127215 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.4079127215
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.3114722678
Short name T105
Test name
Test status
Simulation time 8713559400 ps
CPU time 667.59 seconds
Started Feb 21 01:05:21 PM PST 24
Finished Feb 21 01:16:29 PM PST 24
Peak memory 272640 kb
Host smart-cd32a2b9-e8be-4792-b7c4-fd5338ba0df1
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114722678 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.3114722678
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.435781530
Short name T167
Test name
Test status
Simulation time 95731300 ps
CPU time 135.08 seconds
Started Feb 21 01:05:23 PM PST 24
Finished Feb 21 01:07:39 PM PST 24
Peak memory 260012 kb
Host smart-82724f99-df94-44b5-a459-544c4450ccbb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435781530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp
_reset.435781530
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.603503191
Short name T961
Test name
Test status
Simulation time 737472000 ps
CPU time 336.88 seconds
Started Feb 21 01:05:29 PM PST 24
Finished Feb 21 01:11:07 PM PST 24
Peak memory 260684 kb
Host smart-d7dea750-0684-4f26-802d-86c84ae9c9e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603503191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.603503191
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.556753364
Short name T76
Test name
Test status
Simulation time 26797900 ps
CPU time 13.83 seconds
Started Feb 21 01:05:22 PM PST 24
Finished Feb 21 01:05:37 PM PST 24
Peak memory 264360 kb
Host smart-7c1d784f-3e8f-4935-a79b-f58ab2eb554f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556753364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_rese
t.556753364
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.2972166245
Short name T760
Test name
Test status
Simulation time 1884905800 ps
CPU time 555.42 seconds
Started Feb 21 01:05:22 PM PST 24
Finished Feb 21 01:14:39 PM PST 24
Peak memory 281836 kb
Host smart-41b48358-d0cf-4d82-9a89-cff89dead293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972166245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.2972166245
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.3659674378
Short name T735
Test name
Test status
Simulation time 648743200 ps
CPU time 41.09 seconds
Started Feb 21 01:05:22 PM PST 24
Finished Feb 21 01:06:04 PM PST 24
Peak memory 265560 kb
Host smart-93ca8720-ef37-422e-8323-5ab95c5f3fe2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659674378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.3659674378
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.1254547211
Short name T710
Test name
Test status
Simulation time 891300900 ps
CPU time 97.9 seconds
Started Feb 21 01:05:23 PM PST 24
Finished Feb 21 01:07:01 PM PST 24
Peak memory 280292 kb
Host smart-d072c764-d46b-444a-a004-e9af69fecccd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254547211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_ro.1254547211
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.2508844691
Short name T214
Test name
Test status
Simulation time 1096185300 ps
CPU time 129.48 seconds
Started Feb 21 01:05:27 PM PST 24
Finished Feb 21 01:07:37 PM PST 24
Peak memory 281056 kb
Host smart-4d4a283f-1ef0-4f8d-baf2-6d1331e3388d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2508844691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.2508844691
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.2767242920
Short name T1107
Test name
Test status
Simulation time 1247877500 ps
CPU time 132.3 seconds
Started Feb 21 01:05:23 PM PST 24
Finished Feb 21 01:07:36 PM PST 24
Peak memory 293252 kb
Host smart-b6960a19-2122-4d05-b306-f7ca9e1d23fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767242920 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.2767242920
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.1100240467
Short name T569
Test name
Test status
Simulation time 3664191400 ps
CPU time 502.51 seconds
Started Feb 21 01:05:27 PM PST 24
Finished Feb 21 01:13:50 PM PST 24
Peak memory 313140 kb
Host smart-da9cf7ca-b356-4d48-91fb-3c21884b2f03
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100240467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_rw.1100240467
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.1059295864
Short name T39
Test name
Test status
Simulation time 4042042200 ps
CPU time 608.9 seconds
Started Feb 21 01:05:23 PM PST 24
Finished Feb 21 01:15:32 PM PST 24
Peak memory 313784 kb
Host smart-d737d02f-7b22-404a-b989-87fcafcaaf9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059295864 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_rw_derr.1059295864
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.279723691
Short name T970
Test name
Test status
Simulation time 112965300 ps
CPU time 31.63 seconds
Started Feb 21 01:05:24 PM PST 24
Finished Feb 21 01:05:56 PM PST 24
Peak memory 276500 kb
Host smart-e7ef4faa-246c-46f3-a205-605fb4bc6a76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279723691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_rw_evict.279723691
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.3960728298
Short name T846
Test name
Test status
Simulation time 6591055900 ps
CPU time 619.28 seconds
Started Feb 21 01:05:21 PM PST 24
Finished Feb 21 01:15:41 PM PST 24
Peak memory 313720 kb
Host smart-fa21708f-da0b-434a-afb8-34fb90859613
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960728298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s
err.3960728298
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.1668832545
Short name T399
Test name
Test status
Simulation time 3462353600 ps
CPU time 61.17 seconds
Started Feb 21 01:05:38 PM PST 24
Finished Feb 21 01:06:40 PM PST 24
Peak memory 263920 kb
Host smart-c1a07e96-c472-46ed-bd29-df25bdb15253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668832545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.1668832545
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.3189877414
Short name T536
Test name
Test status
Simulation time 81425700 ps
CPU time 100.46 seconds
Started Feb 21 01:05:24 PM PST 24
Finished Feb 21 01:07:05 PM PST 24
Peak memory 274524 kb
Host smart-d6506c8a-a112-440d-a22f-eade5f8ce1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189877414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.3189877414
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.3728168630
Short name T580
Test name
Test status
Simulation time 6429450700 ps
CPU time 128.56 seconds
Started Feb 21 01:05:27 PM PST 24
Finished Feb 21 01:07:36 PM PST 24
Peak memory 264396 kb
Host smart-d8e1c5bf-9cbf-4f27-a60a-d48194b79eea
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728168630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.flash_ctrl_wo.3728168630
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.3247184337
Short name T1054
Test name
Test status
Simulation time 44596100 ps
CPU time 15.67 seconds
Started Feb 21 01:10:54 PM PST 24
Finished Feb 21 01:11:10 PM PST 24
Peak memory 273892 kb
Host smart-72a1511a-3215-4849-ad74-bb61a5a210ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247184337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.3247184337
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.3170738704
Short name T939
Test name
Test status
Simulation time 150784200 ps
CPU time 111.52 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:12:45 PM PST 24
Peak memory 258684 kb
Host smart-409e91df-e1b4-4fd5-9ae3-43128a0b70d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170738704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.3170738704
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.407028541
Short name T953
Test name
Test status
Simulation time 32577000 ps
CPU time 13.25 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:11:07 PM PST 24
Peak memory 273760 kb
Host smart-d46cb447-387f-46a2-869b-8df385f952ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407028541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.407028541
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.720332626
Short name T1042
Test name
Test status
Simulation time 130388800 ps
CPU time 130.1 seconds
Started Feb 21 01:10:50 PM PST 24
Finished Feb 21 01:13:00 PM PST 24
Peak memory 263836 kb
Host smart-b16c9c51-5d47-4f8d-a840-46ec0095b979
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720332626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_ot
p_reset.720332626
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.1931161665
Short name T776
Test name
Test status
Simulation time 16663900 ps
CPU time 13.36 seconds
Started Feb 21 01:10:52 PM PST 24
Finished Feb 21 01:11:06 PM PST 24
Peak memory 273904 kb
Host smart-1b96cd4c-54d3-4999-a8f1-244553466247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931161665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1931161665
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.1954158257
Short name T709
Test name
Test status
Simulation time 66478100 ps
CPU time 132.1 seconds
Started Feb 21 01:10:49 PM PST 24
Finished Feb 21 01:13:02 PM PST 24
Peak memory 263024 kb
Host smart-3eea9c29-a73c-4bcf-bdf0-84ea50cdb16b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954158257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.1954158257
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.323886047
Short name T1085
Test name
Test status
Simulation time 20542600 ps
CPU time 15.82 seconds
Started Feb 21 01:10:51 PM PST 24
Finished Feb 21 01:11:07 PM PST 24
Peak memory 273876 kb
Host smart-c16d4c2a-2ddf-43f7-90fb-bfa994927e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323886047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.323886047
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.3985779462
Short name T1021
Test name
Test status
Simulation time 77494800 ps
CPU time 135.09 seconds
Started Feb 21 01:10:53 PM PST 24
Finished Feb 21 01:13:08 PM PST 24
Peak memory 258856 kb
Host smart-9274712e-8480-4d53-bd5d-f86225ebf757
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985779462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.3985779462
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.2383935076
Short name T577
Test name
Test status
Simulation time 50558300 ps
CPU time 15.88 seconds
Started Feb 21 01:10:51 PM PST 24
Finished Feb 21 01:11:07 PM PST 24
Peak memory 274008 kb
Host smart-ba41d216-462d-4f6f-be0f-509ac29dc9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383935076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2383935076
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.461753200
Short name T1080
Test name
Test status
Simulation time 37581000 ps
CPU time 111.27 seconds
Started Feb 21 01:10:51 PM PST 24
Finished Feb 21 01:12:42 PM PST 24
Peak memory 260048 kb
Host smart-88457087-84fc-4ca6-9fd9-8707f8d43339
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461753200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_ot
p_reset.461753200
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.599631162
Short name T482
Test name
Test status
Simulation time 79618900 ps
CPU time 13.39 seconds
Started Feb 21 01:10:48 PM PST 24
Finished Feb 21 01:11:02 PM PST 24
Peak memory 274828 kb
Host smart-c1998872-896b-4050-a2db-e0b3a01417f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599631162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.599631162
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.4072241999
Short name T615
Test name
Test status
Simulation time 413606900 ps
CPU time 114.02 seconds
Started Feb 21 01:10:49 PM PST 24
Finished Feb 21 01:12:44 PM PST 24
Peak memory 258660 kb
Host smart-beb0620a-acce-4bd8-9832-993dc6c349d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072241999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.4072241999
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.2254278800
Short name T835
Test name
Test status
Simulation time 49505000 ps
CPU time 15.46 seconds
Started Feb 21 01:10:49 PM PST 24
Finished Feb 21 01:11:04 PM PST 24
Peak memory 273684 kb
Host smart-8da5882b-77f7-42cc-9165-e37b27b75911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254278800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.2254278800
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.682305589
Short name T144
Test name
Test status
Simulation time 96482300 ps
CPU time 133.34 seconds
Started Feb 21 01:10:48 PM PST 24
Finished Feb 21 01:13:02 PM PST 24
Peak memory 263268 kb
Host smart-fe39720c-7a64-484a-834b-9b76b1786ca8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682305589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_ot
p_reset.682305589
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.257059594
Short name T702
Test name
Test status
Simulation time 216459800 ps
CPU time 15.42 seconds
Started Feb 21 01:10:49 PM PST 24
Finished Feb 21 01:11:05 PM PST 24
Peak memory 275120 kb
Host smart-70d64cbe-b9e6-40f2-ba20-38549484af8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257059594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.257059594
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.3312520569
Short name T956
Test name
Test status
Simulation time 385838500 ps
CPU time 130.88 seconds
Started Feb 21 01:10:49 PM PST 24
Finished Feb 21 01:13:00 PM PST 24
Peak memory 259812 kb
Host smart-66cbc20c-7028-4447-9bb9-c3af360f1a61
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312520569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.3312520569
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.3642257079
Short name T466
Test name
Test status
Simulation time 16962400 ps
CPU time 15.93 seconds
Started Feb 21 01:11:04 PM PST 24
Finished Feb 21 01:11:22 PM PST 24
Peak memory 274768 kb
Host smart-87d7b413-d2be-4930-b36d-06c8898c8458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642257079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.3642257079
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.4221447326
Short name T392
Test name
Test status
Simulation time 70007400 ps
CPU time 110.12 seconds
Started Feb 21 01:10:49 PM PST 24
Finished Feb 21 01:12:40 PM PST 24
Peak memory 262820 kb
Host smart-7fb97711-65e2-48d3-a0c6-ced5afb862c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221447326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.4221447326
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.982084575
Short name T196
Test name
Test status
Simulation time 14463700 ps
CPU time 13.36 seconds
Started Feb 21 01:11:06 PM PST 24
Finished Feb 21 01:11:21 PM PST 24
Peak memory 274760 kb
Host smart-648fb727-b0ae-412a-b0ec-48381a172960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982084575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.982084575
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.2221717887
Short name T158
Test name
Test status
Simulation time 128430000 ps
CPU time 110.14 seconds
Started Feb 21 01:11:02 PM PST 24
Finished Feb 21 01:12:53 PM PST 24
Peak memory 262612 kb
Host smart-f1addf23-5efc-4e87-bb28-35a3d4b466b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221717887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.2221717887
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.118879638
Short name T430
Test name
Test status
Simulation time 41479400 ps
CPU time 14.05 seconds
Started Feb 21 01:05:50 PM PST 24
Finished Feb 21 01:06:04 PM PST 24
Peak memory 264424 kb
Host smart-910d3094-50a2-43c2-b37d-6f8c797fb3e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118879638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.118879638
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.1531000336
Short name T628
Test name
Test status
Simulation time 34233700 ps
CPU time 13.33 seconds
Started Feb 21 01:05:52 PM PST 24
Finished Feb 21 01:06:05 PM PST 24
Peak memory 274040 kb
Host smart-47dc43f7-2802-4ecd-af04-b5ccaea06dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531000336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.1531000336
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.4105625643
Short name T1082
Test name
Test status
Simulation time 17091500 ps
CPU time 20.66 seconds
Started Feb 21 01:05:58 PM PST 24
Finished Feb 21 01:06:19 PM PST 24
Peak memory 272784 kb
Host smart-86ed2674-835f-4446-af8f-72bb21e1d0bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105625643 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.4105625643
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.893133897
Short name T825
Test name
Test status
Simulation time 3028178900 ps
CPU time 2244.57 seconds
Started Feb 21 01:05:37 PM PST 24
Finished Feb 21 01:43:03 PM PST 24
Peak memory 263716 kb
Host smart-a64acff2-5a33-4ddb-8d3f-f75630b481c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893133897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_erro
r_mp.893133897
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.563942548
Short name T301
Test name
Test status
Simulation time 8766689000 ps
CPU time 859.79 seconds
Started Feb 21 01:05:40 PM PST 24
Finished Feb 21 01:20:01 PM PST 24
Peak memory 264440 kb
Host smart-bdfa7d8d-04a8-445c-85b1-c9ed0b5ab7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563942548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.563942548
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.4289187100
Short name T37
Test name
Test status
Simulation time 2078224900 ps
CPU time 29.91 seconds
Started Feb 21 01:05:39 PM PST 24
Finished Feb 21 01:06:10 PM PST 24
Peak memory 264420 kb
Host smart-39a89696-fa5c-4737-8512-91a069155ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289187100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.4289187100
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.824767628
Short name T110
Test name
Test status
Simulation time 10019494500 ps
CPU time 69.82 seconds
Started Feb 21 01:05:51 PM PST 24
Finished Feb 21 01:07:01 PM PST 24
Peak memory 279576 kb
Host smart-31a29074-f0a3-4757-81f6-a7d884c401e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824767628 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.824767628
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.2747970995
Short name T539
Test name
Test status
Simulation time 15556900 ps
CPU time 13.37 seconds
Started Feb 21 01:05:52 PM PST 24
Finished Feb 21 01:06:06 PM PST 24
Peak memory 263612 kb
Host smart-8fd6dde8-96ea-4276-8bc5-05b5aebd1e40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747970995 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.2747970995
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.888967081
Short name T176
Test name
Test status
Simulation time 40120620200 ps
CPU time 717.24 seconds
Started Feb 21 01:05:39 PM PST 24
Finished Feb 21 01:17:37 PM PST 24
Peak memory 262256 kb
Host smart-592aa78a-f3fb-49c1-bf31-591a652a9f02
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888967081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.flash_ctrl_hw_rma_reset.888967081
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.1858093682
Short name T528
Test name
Test status
Simulation time 2100996800 ps
CPU time 84.49 seconds
Started Feb 21 01:05:38 PM PST 24
Finished Feb 21 01:07:03 PM PST 24
Peak memory 261504 kb
Host smart-45e432a5-7b1c-4c9f-85c5-3dbcd610d68c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858093682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.1858093682
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.1922331084
Short name T1035
Test name
Test status
Simulation time 2415881700 ps
CPU time 153.4 seconds
Started Feb 21 01:05:40 PM PST 24
Finished Feb 21 01:08:15 PM PST 24
Peak memory 293244 kb
Host smart-8dd0a2c3-1732-42cc-bf0a-b1b8297114d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922331084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.1922331084
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.798749165
Short name T1095
Test name
Test status
Simulation time 7825327800 ps
CPU time 178.44 seconds
Started Feb 21 01:05:49 PM PST 24
Finished Feb 21 01:08:48 PM PST 24
Peak memory 283964 kb
Host smart-ecbe7d8c-a643-4de8-a29b-e1444d28711f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798749165 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.798749165
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.2843492478
Short name T80
Test name
Test status
Simulation time 20310554700 ps
CPU time 126.97 seconds
Started Feb 21 01:05:38 PM PST 24
Finished Feb 21 01:07:46 PM PST 24
Peak memory 264400 kb
Host smart-76d01152-580f-4754-a4a7-e001c347be93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843492478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.2843492478
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1456568101
Short name T554
Test name
Test status
Simulation time 182512354000 ps
CPU time 385.26 seconds
Started Feb 21 01:05:58 PM PST 24
Finished Feb 21 01:12:23 PM PST 24
Peak memory 264292 kb
Host smart-0ef142ae-5079-40a3-bff1-9e82a2d73f93
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145
6568101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.1456568101
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.3177901826
Short name T118
Test name
Test status
Simulation time 1684013500 ps
CPU time 63.46 seconds
Started Feb 21 01:05:39 PM PST 24
Finished Feb 21 01:06:44 PM PST 24
Peak memory 258860 kb
Host smart-29c0e052-719e-45b5-b3a4-e7dffed23659
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177901826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3177901826
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.3745577865
Short name T299
Test name
Test status
Simulation time 26002600 ps
CPU time 13.84 seconds
Started Feb 21 01:05:50 PM PST 24
Finished Feb 21 01:06:04 PM PST 24
Peak memory 264400 kb
Host smart-44fc8a46-6b0a-4990-aea4-44827dcee5ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745577865 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.3745577865
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.736693985
Short name T1118
Test name
Test status
Simulation time 7452350500 ps
CPU time 172.09 seconds
Started Feb 21 01:05:38 PM PST 24
Finished Feb 21 01:08:31 PM PST 24
Peak memory 264420 kb
Host smart-dc07c2ad-5bb0-4802-935c-1a7cf4234b7b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736693985 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_mp_regions.736693985
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.2499861004
Short name T725
Test name
Test status
Simulation time 2113622200 ps
CPU time 554.25 seconds
Started Feb 21 01:05:39 PM PST 24
Finished Feb 21 01:14:54 PM PST 24
Peak memory 260744 kb
Host smart-7238b5c6-bb4a-4a8f-80f0-18e0ea84b1f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499861004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.2499861004
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.3554113223
Short name T841
Test name
Test status
Simulation time 226503600 ps
CPU time 19.93 seconds
Started Feb 21 01:05:52 PM PST 24
Finished Feb 21 01:06:12 PM PST 24
Peak memory 264388 kb
Host smart-09e94055-bb94-448d-b9b3-b68ba654b728
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554113223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.3554113223
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.3287368108
Short name T127
Test name
Test status
Simulation time 180506600 ps
CPU time 1046.3 seconds
Started Feb 21 01:05:46 PM PST 24
Finished Feb 21 01:23:12 PM PST 24
Peak memory 284244 kb
Host smart-c304d69c-9308-4911-978b-7b9f86a14530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287368108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3287368108
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.4085708824
Short name T912
Test name
Test status
Simulation time 572096800 ps
CPU time 128.25 seconds
Started Feb 21 01:05:40 PM PST 24
Finished Feb 21 01:07:50 PM PST 24
Peak memory 280796 kb
Host smart-871aac8a-8191-4ae8-9469-d6a9f64e1d5e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085708824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_ro.4085708824
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.395731918
Short name T804
Test name
Test status
Simulation time 641720800 ps
CPU time 121.23 seconds
Started Feb 21 01:05:41 PM PST 24
Finished Feb 21 01:07:43 PM PST 24
Peak memory 280980 kb
Host smart-19ef5c3b-c4e6-4701-825e-308ccead1dcd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
395731918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.395731918
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.2824323827
Short name T382
Test name
Test status
Simulation time 1446955100 ps
CPU time 118.71 seconds
Started Feb 21 01:05:42 PM PST 24
Finished Feb 21 01:07:41 PM PST 24
Peak memory 293372 kb
Host smart-d775ff68-c243-451f-a1dc-12567c967cf2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824323827 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.2824323827
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.1335638000
Short name T493
Test name
Test status
Simulation time 5415850500 ps
CPU time 465.18 seconds
Started Feb 21 01:05:37 PM PST 24
Finished Feb 21 01:13:23 PM PST 24
Peak memory 313600 kb
Host smart-d9d632df-f27d-4903-af7f-c5b62ffb7bb2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335638000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_rw.1335638000
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.862436540
Short name T277
Test name
Test status
Simulation time 3295120700 ps
CPU time 550.09 seconds
Started Feb 21 01:05:48 PM PST 24
Finished Feb 21 01:14:58 PM PST 24
Peak memory 324780 kb
Host smart-606f1435-b5fd-452b-b5eb-caab23be22c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862436540 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.flash_ctrl_rw_derr.862436540
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.796242572
Short name T41
Test name
Test status
Simulation time 42669900 ps
CPU time 31.05 seconds
Started Feb 21 01:05:50 PM PST 24
Finished Feb 21 01:06:22 PM PST 24
Peak memory 274900 kb
Host smart-6cb85713-0ff6-4a1c-9441-47786447af60
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796242572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_rw_evict.796242572
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.3563228936
Short name T490
Test name
Test status
Simulation time 108242100 ps
CPU time 31.47 seconds
Started Feb 21 01:05:57 PM PST 24
Finished Feb 21 01:06:29 PM PST 24
Peak memory 274924 kb
Host smart-53903a67-9baf-4a1f-8d52-8ba5b22ff0fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563228936 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.3563228936
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.3764533499
Short name T999
Test name
Test status
Simulation time 15790619500 ps
CPU time 535.16 seconds
Started Feb 21 01:05:41 PM PST 24
Finished Feb 21 01:14:37 PM PST 24
Peak memory 319100 kb
Host smart-d41904b2-2bc9-45ac-a8bf-f7702d15964a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764533499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.3764533499
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.236226373
Short name T818
Test name
Test status
Simulation time 1280414000 ps
CPU time 68.43 seconds
Started Feb 21 01:05:54 PM PST 24
Finished Feb 21 01:07:03 PM PST 24
Peak memory 263368 kb
Host smart-80ebe343-e164-40a7-ac6e-124860617adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236226373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.236226373
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.1838262920
Short name T379
Test name
Test status
Simulation time 41079500 ps
CPU time 123.89 seconds
Started Feb 21 01:05:40 PM PST 24
Finished Feb 21 01:07:45 PM PST 24
Peak memory 275984 kb
Host smart-debf97ee-4d23-4379-8b08-264ef0b822d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838262920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1838262920
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.574170898
Short name T527
Test name
Test status
Simulation time 2003527200 ps
CPU time 177.64 seconds
Started Feb 21 01:05:38 PM PST 24
Finished Feb 21 01:08:37 PM PST 24
Peak memory 264380 kb
Host smart-2202c3a2-ed4e-4eed-aed8-e18f8d957806
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574170898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_wo.574170898
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2911707767
Short name T1038
Test name
Test status
Simulation time 98998300 ps
CPU time 13.86 seconds
Started Feb 21 01:06:11 PM PST 24
Finished Feb 21 01:06:26 PM PST 24
Peak memory 264160 kb
Host smart-8d562a7a-4e73-4ca7-a1b3-0e2045c04da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911707767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
911707767
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.4010801667
Short name T929
Test name
Test status
Simulation time 150192000 ps
CPU time 15.97 seconds
Started Feb 21 01:06:20 PM PST 24
Finished Feb 21 01:06:36 PM PST 24
Peak memory 274092 kb
Host smart-74ce45ee-5f3d-455a-ac35-dee28af6d9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010801667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.4010801667
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.977078626
Short name T377
Test name
Test status
Simulation time 26539200 ps
CPU time 21.7 seconds
Started Feb 21 01:06:20 PM PST 24
Finished Feb 21 01:06:42 PM PST 24
Peak memory 264672 kb
Host smart-fce01d37-113e-46ac-8c84-0c3b048659a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977078626 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.977078626
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.3697417123
Short name T959
Test name
Test status
Simulation time 23224693900 ps
CPU time 2279.14 seconds
Started Feb 21 01:06:13 PM PST 24
Finished Feb 21 01:44:13 PM PST 24
Peak memory 264496 kb
Host smart-93b32f65-cb7d-4206-9b9b-4eaef928178c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697417123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.3697417123
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.2489992509
Short name T917
Test name
Test status
Simulation time 3961933000 ps
CPU time 986.11 seconds
Started Feb 21 01:05:52 PM PST 24
Finished Feb 21 01:22:18 PM PST 24
Peak memory 272532 kb
Host smart-37bec07b-2d43-4e2b-9ab6-5c1a204f3a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489992509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2489992509
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.2270160425
Short name T642
Test name
Test status
Simulation time 647561400 ps
CPU time 23.04 seconds
Started Feb 21 01:05:58 PM PST 24
Finished Feb 21 01:06:21 PM PST 24
Peak memory 264360 kb
Host smart-ffbfff21-ec11-4681-85a2-eeded0b1830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270160425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.2270160425
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2156413898
Short name T296
Test name
Test status
Simulation time 10032566700 ps
CPU time 55.15 seconds
Started Feb 21 01:06:16 PM PST 24
Finished Feb 21 01:07:12 PM PST 24
Peak memory 270476 kb
Host smart-1d942f36-272d-479c-b1c0-b0f87930c5c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156413898 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.2156413898
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.2130326610
Short name T291
Test name
Test status
Simulation time 45644800 ps
CPU time 13.24 seconds
Started Feb 21 01:06:18 PM PST 24
Finished Feb 21 01:06:31 PM PST 24
Peak memory 264548 kb
Host smart-8e546f1c-175f-4b61-afde-b1f08d0918da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130326610 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.2130326610
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.512489896
Short name T824
Test name
Test status
Simulation time 240239400800 ps
CPU time 811.48 seconds
Started Feb 21 01:05:52 PM PST 24
Finished Feb 21 01:19:24 PM PST 24
Peak memory 258312 kb
Host smart-1589f357-c973-4d0c-b4b2-3aadee0d324c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512489896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.flash_ctrl_hw_rma_reset.512489896
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1637737108
Short name T656
Test name
Test status
Simulation time 761396800 ps
CPU time 54.04 seconds
Started Feb 21 01:05:54 PM PST 24
Finished Feb 21 01:06:48 PM PST 24
Peak memory 261588 kb
Host smart-ffbbaa59-df6f-4cdb-bd6e-7437e59390cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637737108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.1637737108
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.886942959
Short name T542
Test name
Test status
Simulation time 2512479900 ps
CPU time 168.91 seconds
Started Feb 21 01:06:12 PM PST 24
Finished Feb 21 01:09:02 PM PST 24
Peak memory 293300 kb
Host smart-207467bf-e784-4db6-b5f9-5081044d7506
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886942959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash
_ctrl_intr_rd.886942959
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1662407961
Short name T837
Test name
Test status
Simulation time 8820916700 ps
CPU time 214.48 seconds
Started Feb 21 01:06:20 PM PST 24
Finished Feb 21 01:09:55 PM PST 24
Peak memory 289116 kb
Host smart-f23a3ede-d152-4edb-adfc-49e221ee0c7f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662407961 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.1662407961
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.2833624436
Short name T630
Test name
Test status
Simulation time 12547311000 ps
CPU time 118.3 seconds
Started Feb 21 01:06:19 PM PST 24
Finished Feb 21 01:08:18 PM PST 24
Peak memory 264412 kb
Host smart-f7f452ef-778f-4229-beac-40c6dd06b52b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833624436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.2833624436
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2079306884
Short name T865
Test name
Test status
Simulation time 44258482300 ps
CPU time 303.23 seconds
Started Feb 21 01:06:09 PM PST 24
Finished Feb 21 01:11:13 PM PST 24
Peak memory 264384 kb
Host smart-f2f9d7c7-803a-4bda-9a79-5dd22359ba49
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207
9306884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.2079306884
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.2503727788
Short name T1023
Test name
Test status
Simulation time 4262091700 ps
CPU time 69.5 seconds
Started Feb 21 01:06:09 PM PST 24
Finished Feb 21 01:07:20 PM PST 24
Peak memory 258944 kb
Host smart-a29b81d9-5fd5-4298-9dcb-af77f2be4e7c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503727788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2503727788
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.310909088
Short name T1045
Test name
Test status
Simulation time 48212600 ps
CPU time 13.72 seconds
Started Feb 21 01:06:19 PM PST 24
Finished Feb 21 01:06:33 PM PST 24
Peak memory 264444 kb
Host smart-ddeca971-af5c-4248-9df8-e12bda69347e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310909088 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.310909088
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.2773572885
Short name T1010
Test name
Test status
Simulation time 38804018300 ps
CPU time 682.9 seconds
Started Feb 21 01:05:51 PM PST 24
Finished Feb 21 01:17:15 PM PST 24
Peak memory 273132 kb
Host smart-d2573225-cd77-44d0-a29d-8fa19d6af544
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773572885 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.2773572885
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.3724845991
Short name T156
Test name
Test status
Simulation time 37357000 ps
CPU time 135.67 seconds
Started Feb 21 01:05:50 PM PST 24
Finished Feb 21 01:08:07 PM PST 24
Peak memory 259060 kb
Host smart-5c959a3a-4f8e-4178-a9ca-e75845b08a25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724845991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.3724845991
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.3583181781
Short name T556
Test name
Test status
Simulation time 44599000 ps
CPU time 151.84 seconds
Started Feb 21 01:05:52 PM PST 24
Finished Feb 21 01:08:25 PM PST 24
Peak memory 264496 kb
Host smart-2367333a-df0a-41f3-8fa6-60f6b12544d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583181781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.3583181781
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.3793091088
Short name T1076
Test name
Test status
Simulation time 4581331400 ps
CPU time 378.88 seconds
Started Feb 21 01:06:11 PM PST 24
Finished Feb 21 01:12:32 PM PST 24
Peak memory 264464 kb
Host smart-91dfcd17-48f1-40e8-bd17-06e28e2d2272
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793091088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.3793091088
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.2848618125
Short name T699
Test name
Test status
Simulation time 53528000 ps
CPU time 502.21 seconds
Started Feb 21 01:05:56 PM PST 24
Finished Feb 21 01:14:18 PM PST 24
Peak memory 280756 kb
Host smart-e19e8c25-1e74-4ccb-8cc0-7b3b8c1714a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848618125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.2848618125
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.3447261870
Short name T49
Test name
Test status
Simulation time 122751200 ps
CPU time 38.35 seconds
Started Feb 21 01:06:22 PM PST 24
Finished Feb 21 01:07:00 PM PST 24
Peak memory 276228 kb
Host smart-5b586536-0717-48b6-b26b-ac8a28e9f3e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447261870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.3447261870
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.4248155677
Short name T200
Test name
Test status
Simulation time 2006380300 ps
CPU time 100.18 seconds
Started Feb 21 01:06:09 PM PST 24
Finished Feb 21 01:07:50 PM PST 24
Peak memory 280008 kb
Host smart-2bc6196d-2c58-4d46-85d8-6a55fade870e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248155677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_ro.4248155677
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.2882833502
Short name T202
Test name
Test status
Simulation time 943805400 ps
CPU time 122.94 seconds
Started Feb 21 01:06:11 PM PST 24
Finished Feb 21 01:08:15 PM PST 24
Peak memory 281024 kb
Host smart-a3672472-e514-4ebc-af7e-3642992a5f1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2882833502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2882833502
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.4172955735
Short name T740
Test name
Test status
Simulation time 588710000 ps
CPU time 120.93 seconds
Started Feb 21 01:06:12 PM PST 24
Finished Feb 21 01:08:14 PM PST 24
Peak memory 281004 kb
Host smart-6bb42bb2-82d1-460a-9600-a9a63c140013
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172955735 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.4172955735
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.3575892931
Short name T547
Test name
Test status
Simulation time 14651881500 ps
CPU time 499.76 seconds
Started Feb 21 01:06:17 PM PST 24
Finished Feb 21 01:14:37 PM PST 24
Peak memory 313604 kb
Host smart-b4e3249d-e591-4416-9e46-0174ace8bd8c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575892931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct
rl_rw.3575892931
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.2573351732
Short name T201
Test name
Test status
Simulation time 22145447200 ps
CPU time 537.11 seconds
Started Feb 21 01:06:09 PM PST 24
Finished Feb 21 01:15:07 PM PST 24
Peak memory 327776 kb
Host smart-ac53298e-6dee-4079-a046-d5bd771970d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573351732 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_rw_derr.2573351732
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.3626927245
Short name T947
Test name
Test status
Simulation time 32279700 ps
CPU time 29.22 seconds
Started Feb 21 01:06:15 PM PST 24
Finished Feb 21 01:06:45 PM PST 24
Peak memory 274800 kb
Host smart-3ae3b836-2fb2-42dd-a63b-fdb7c9d674d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626927245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.3626927245
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3729256254
Short name T114
Test name
Test status
Simulation time 180637700 ps
CPU time 36.46 seconds
Started Feb 21 01:06:16 PM PST 24
Finished Feb 21 01:06:53 PM PST 24
Peak memory 265548 kb
Host smart-06ba95c9-8046-42a0-8576-429845f57bd7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729256254 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.3729256254
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.146906717
Short name T253
Test name
Test status
Simulation time 2569430700 ps
CPU time 66.61 seconds
Started Feb 21 01:06:16 PM PST 24
Finished Feb 21 01:07:23 PM PST 24
Peak memory 258812 kb
Host smart-8fe61f20-a203-4a98-bc6f-8f8f5807512a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146906717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.146906717
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.3678389791
Short name T887
Test name
Test status
Simulation time 68047600 ps
CPU time 122.2 seconds
Started Feb 21 01:05:53 PM PST 24
Finished Feb 21 01:07:55 PM PST 24
Peak memory 277900 kb
Host smart-b47958ab-fae4-4836-bf09-5894e0d70f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678389791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.3678389791
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.4132665437
Short name T631
Test name
Test status
Simulation time 2195072000 ps
CPU time 146.62 seconds
Started Feb 21 01:06:11 PM PST 24
Finished Feb 21 01:08:39 PM PST 24
Peak memory 264460 kb
Host smart-a2b928d7-73ab-4515-b8d5-f7d51819c72b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132665437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.flash_ctrl_wo.4132665437
Directory /workspace/9.flash_ctrl_wo/latest
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