Module Definition
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Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.63 99.17 92.71 89.47 96.81 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
72.41 88.24 83.33 57.14 83.33 50.00 u_prog_tl_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
72.29 86.27 88.89 57.14 79.17 50.00 u_tl_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.26 97.67 85.11 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

SCORELINE
100.00 100.00
tb.dut.u_lc_seed_hw_rd_en_sync

SCORELINE
100.00 100.00
tb.dut.u_lc_escalation_en_sync

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prog_tl_gate.u_err_en_sync

SCORELINE
100.00 100.00
tb.dut.u_tl_gate.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync

Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 5 5


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 10610 10610 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.OutputDelay_A 2147483647 2147483647 0 22026
gen_no_flops.OutputDelay_A 820036390 818326240 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10610 10610 0 0
T1 10 10 0 0
T2 10 10 0 0
T3 10 10 0 0
T4 10 10 0 0
T5 10 10 0 0
T6 10 10 0 0
T7 10 10 0 0
T16 10 10 0 0
T17 10 10 0 0
T18 10 10 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1369510 1369460 0 0
T2 891670 857810 0 0
T3 3854550 3854390 0 0
T4 6009 5309 0 0
T5 16250 14840 0 0
T6 6802 5872 0 0
T7 8167490 8166020 0 0
T16 25770 25060 0 0
T17 965490 964520 0 0
T18 274930 274130 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 22026
T1 1095608 1095568 0 24
T2 713336 685168 0 24
T3 3083640 3083504 0 24
T4 4775 4194 0 21
T5 13000 11824 0 24
T6 5398 4633 0 21
T7 6533992 6532768 0 24
T8 0 0 0 3
T9 0 0 0 3
T16 20616 20024 0 24
T17 772392 771592 0 24
T18 219944 219280 0 24

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 820036390 818326240 0 0
T1 273902 273892 0 0
T2 178334 171562 0 0
T3 770910 770878 0 0
T4 1234 1094 0 0
T5 3250 2968 0 0
T6 1404 1218 0 0
T7 1633498 1633204 0 0
T16 5154 5012 0 0
T17 193098 192904 0 0
T18 54986 54826 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 1061 1061 0 0
OutputsKnown_A 410018267 409163192 0 0
gen_flops.OutputDelay_A 410018267 409129715 0 2772


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409163192 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 617 547 0 0
T5 1625 1484 0 0
T6 702 609 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409129715 0 2772
T1 136951 136946 0 3
T2 89167 85646 0 3
T3 385455 385438 0 3
T4 617 544 0 3
T5 1625 1478 0 3
T6 702 606 0 3
T7 816749 816596 0 3
T16 2577 2503 0 3
T17 96549 96449 0 3
T18 27493 27410 0 3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 1061 1061 0 0
OutputsKnown_A 410018267 409163192 0 0
gen_flops.OutputDelay_A 410018267 409129715 0 2772


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409163192 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 617 547 0 0
T5 1625 1484 0 0
T6 702 609 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409129715 0 2772
T1 136951 136946 0 3
T2 89167 85646 0 3
T3 385455 385438 0 3
T4 617 544 0 3
T5 1625 1478 0 3
T6 702 606 0 3
T7 816749 816596 0 3
T16 2577 2503 0 3
T17 96549 96449 0 3
T18 27493 27410 0 3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 1061 1061 0 0
OutputsKnown_A 410018267 409163192 0 0
gen_flops.OutputDelay_A 410018267 409129715 0 2772


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409163192 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 617 547 0 0
T5 1625 1484 0 0
T6 702 609 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409129715 0 2772
T1 136951 136946 0 3
T2 89167 85646 0 3
T3 385455 385438 0 3
T4 617 544 0 3
T5 1625 1478 0 3
T6 702 606 0 3
T7 816749 816596 0 3
T16 2577 2503 0 3
T17 96549 96449 0 3
T18 27493 27410 0 3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 1061 1061 0 0
OutputsKnown_A 410018267 409163192 0 0
gen_flops.OutputDelay_A 410018267 409129715 0 2772


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409163192 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 617 547 0 0
T5 1625 1484 0 0
T6 702 609 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409129715 0 2772
T1 136951 136946 0 3
T2 89167 85646 0 3
T3 385455 385438 0 3
T4 617 544 0 3
T5 1625 1478 0 3
T6 702 606 0 3
T7 816749 816596 0 3
T16 2577 2503 0 3
T17 96549 96449 0 3
T18 27493 27410 0 3

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 1061 1061 0 0
OutputsKnown_A 410018267 409163192 0 0
gen_flops.OutputDelay_A 410018267 409129715 0 2772


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409163192 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 617 547 0 0
T5 1625 1484 0 0
T6 702 609 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409129715 0 2772
T1 136951 136946 0 3
T2 89167 85646 0 3
T3 385455 385438 0 3
T4 617 544 0 3
T5 1625 1478 0 3
T6 702 606 0 3
T7 816749 816596 0 3
T16 2577 2503 0 3
T17 96549 96449 0 3
T18 27493 27410 0 3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 1061 1061 0 0
OutputsKnown_A 410018267 409163192 0 0
gen_flops.OutputDelay_A 410018267 409129715 0 2772


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409163192 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 617 547 0 0
T5 1625 1484 0 0
T6 702 609 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018267 409129715 0 2772
T1 136951 136946 0 3
T2 89167 85646 0 3
T3 385455 385438 0 3
T4 617 544 0 3
T5 1625 1478 0 3
T6 702 606 0 3
T7 816749 816596 0 3
T16 2577 2503 0 3
T17 96549 96449 0 3
T18 27493 27410 0 3

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 1061 1061 0 0
OutputsKnown_A 410018195 409163120 0 0
gen_no_flops.OutputDelay_A 410018195 409163120 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018195 409163120 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 617 547 0 0
T5 1625 1484 0 0
T6 702 609 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018195 409163120 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 617 547 0 0
T5 1625 1484 0 0
T6 702 609 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_lc_escalation_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 1061 1061 0 0
OutputsKnown_A 409997818 409142743 0 0
gen_flops.OutputDelay_A 409997818 409109416 0 2622


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 409997818 409142743 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 456 386 0 0
T5 1625 1484 0 0
T6 484 391 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 409997818 409109416 0 2622
T1 136951 136946 0 3
T2 89167 85646 0 3
T3 385455 385438 0 3
T4 456 386 0 0
T5 1625 1478 0 3
T6 484 391 0 0
T7 816749 816596 0 3
T8 0 0 0 3
T9 0 0 0 3
T16 2577 2503 0 3
T17 96549 96449 0 3
T18 27493 27410 0 3

Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 1061 1061 0 0
OutputsKnown_A 410018195 409163120 0 0
gen_no_flops.OutputDelay_A 410018195 409163120 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018195 409163120 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 617 547 0 0
T5 1625 1484 0 0
T6 702 609 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018195 409163120 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 617 547 0 0
T5 1625 1484 0 0
T6 702 609 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 5 5


Assert Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 1061 1061 0 0
OutputsKnown_A 410018195 409163120 0 0
gen_flops.OutputDelay_A 410018195 409129658 0 2772


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1061 1061 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018195 409163120 0 0
T1 136951 136946 0 0
T2 89167 85781 0 0
T3 385455 385439 0 0
T4 617 547 0 0
T5 1625 1484 0 0
T6 702 609 0 0
T7 816749 816602 0 0
T16 2577 2506 0 0
T17 96549 96452 0 0
T18 27493 27413 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410018195 409129658 0 2772
T1 136951 136946 0 3
T2 89167 85646 0 3
T3 385455 385438 0 3
T4 617 544 0 3
T5 1625 1478 0 3
T6 702 606 0 3
T7 816749 816596 0 3
T16 2577 2503 0 3
T17 96549 96449 0 3
T18 27493 27410 0 3