SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.63 | 99.17 | 92.71 | 89.47 | 96.81 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
72.41 | 88.24 | 83.33 | 57.14 | 83.33 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
72.29 | 86.27 | 88.89 | 57.14 | 79.17 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.26 | 97.67 | 85.11 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10610 | 10610 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 22026 |
gen_no_flops.OutputDelay_A | 820036390 | 818326240 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10610 | 10610 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T5 | 10 | 10 | 0 | 0 |
T6 | 10 | 10 | 0 | 0 |
T7 | 10 | 10 | 0 | 0 |
T16 | 10 | 10 | 0 | 0 |
T17 | 10 | 10 | 0 | 0 |
T18 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 1369510 | 1369460 | 0 | 0 |
T2 | 891670 | 857810 | 0 | 0 |
T3 | 3854550 | 3854390 | 0 | 0 |
T4 | 6009 | 5309 | 0 | 0 |
T5 | 16250 | 14840 | 0 | 0 |
T6 | 6802 | 5872 | 0 | 0 |
T7 | 8167490 | 8166020 | 0 | 0 |
T16 | 25770 | 25060 | 0 | 0 |
T17 | 965490 | 964520 | 0 | 0 |
T18 | 274930 | 274130 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 22026 |
T1 | 1095608 | 1095568 | 0 | 24 |
T2 | 713336 | 685168 | 0 | 24 |
T3 | 3083640 | 3083504 | 0 | 24 |
T4 | 4775 | 4194 | 0 | 21 |
T5 | 13000 | 11824 | 0 | 24 |
T6 | 5398 | 4633 | 0 | 21 |
T7 | 6533992 | 6532768 | 0 | 24 |
T8 | 0 | 0 | 0 | 3 |
T9 | 0 | 0 | 0 | 3 |
T16 | 20616 | 20024 | 0 | 24 |
T17 | 772392 | 771592 | 0 | 24 |
T18 | 219944 | 219280 | 0 | 24 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 820036390 | 818326240 | 0 | 0 |
T1 | 273902 | 273892 | 0 | 0 |
T2 | 178334 | 171562 | 0 | 0 |
T3 | 770910 | 770878 | 0 | 0 |
T4 | 1234 | 1094 | 0 | 0 |
T5 | 3250 | 2968 | 0 | 0 |
T6 | 1404 | 1218 | 0 | 0 |
T7 | 1633498 | 1633204 | 0 | 0 |
T16 | 5154 | 5012 | 0 | 0 |
T17 | 193098 | 192904 | 0 | 0 |
T18 | 54986 | 54826 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1061 | 1061 | 0 | 0 |
OutputsKnown_A | 410018267 | 409163192 | 0 | 0 |
gen_flops.OutputDelay_A | 410018267 | 409129715 | 0 | 2772 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1061 | 1061 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409163192 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 617 | 547 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 702 | 609 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409129715 | 0 | 2772 |
T1 | 136951 | 136946 | 0 | 3 |
T2 | 89167 | 85646 | 0 | 3 |
T3 | 385455 | 385438 | 0 | 3 |
T4 | 617 | 544 | 0 | 3 |
T5 | 1625 | 1478 | 0 | 3 |
T6 | 702 | 606 | 0 | 3 |
T7 | 816749 | 816596 | 0 | 3 |
T16 | 2577 | 2503 | 0 | 3 |
T17 | 96549 | 96449 | 0 | 3 |
T18 | 27493 | 27410 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1061 | 1061 | 0 | 0 |
OutputsKnown_A | 410018267 | 409163192 | 0 | 0 |
gen_flops.OutputDelay_A | 410018267 | 409129715 | 0 | 2772 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1061 | 1061 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409163192 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 617 | 547 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 702 | 609 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409129715 | 0 | 2772 |
T1 | 136951 | 136946 | 0 | 3 |
T2 | 89167 | 85646 | 0 | 3 |
T3 | 385455 | 385438 | 0 | 3 |
T4 | 617 | 544 | 0 | 3 |
T5 | 1625 | 1478 | 0 | 3 |
T6 | 702 | 606 | 0 | 3 |
T7 | 816749 | 816596 | 0 | 3 |
T16 | 2577 | 2503 | 0 | 3 |
T17 | 96549 | 96449 | 0 | 3 |
T18 | 27493 | 27410 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1061 | 1061 | 0 | 0 |
OutputsKnown_A | 410018267 | 409163192 | 0 | 0 |
gen_flops.OutputDelay_A | 410018267 | 409129715 | 0 | 2772 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1061 | 1061 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409163192 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 617 | 547 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 702 | 609 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409129715 | 0 | 2772 |
T1 | 136951 | 136946 | 0 | 3 |
T2 | 89167 | 85646 | 0 | 3 |
T3 | 385455 | 385438 | 0 | 3 |
T4 | 617 | 544 | 0 | 3 |
T5 | 1625 | 1478 | 0 | 3 |
T6 | 702 | 606 | 0 | 3 |
T7 | 816749 | 816596 | 0 | 3 |
T16 | 2577 | 2503 | 0 | 3 |
T17 | 96549 | 96449 | 0 | 3 |
T18 | 27493 | 27410 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1061 | 1061 | 0 | 0 |
OutputsKnown_A | 410018267 | 409163192 | 0 | 0 |
gen_flops.OutputDelay_A | 410018267 | 409129715 | 0 | 2772 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1061 | 1061 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409163192 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 617 | 547 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 702 | 609 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409129715 | 0 | 2772 |
T1 | 136951 | 136946 | 0 | 3 |
T2 | 89167 | 85646 | 0 | 3 |
T3 | 385455 | 385438 | 0 | 3 |
T4 | 617 | 544 | 0 | 3 |
T5 | 1625 | 1478 | 0 | 3 |
T6 | 702 | 606 | 0 | 3 |
T7 | 816749 | 816596 | 0 | 3 |
T16 | 2577 | 2503 | 0 | 3 |
T17 | 96549 | 96449 | 0 | 3 |
T18 | 27493 | 27410 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1061 | 1061 | 0 | 0 |
OutputsKnown_A | 410018267 | 409163192 | 0 | 0 |
gen_flops.OutputDelay_A | 410018267 | 409129715 | 0 | 2772 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1061 | 1061 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409163192 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 617 | 547 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 702 | 609 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409129715 | 0 | 2772 |
T1 | 136951 | 136946 | 0 | 3 |
T2 | 89167 | 85646 | 0 | 3 |
T3 | 385455 | 385438 | 0 | 3 |
T4 | 617 | 544 | 0 | 3 |
T5 | 1625 | 1478 | 0 | 3 |
T6 | 702 | 606 | 0 | 3 |
T7 | 816749 | 816596 | 0 | 3 |
T16 | 2577 | 2503 | 0 | 3 |
T17 | 96549 | 96449 | 0 | 3 |
T18 | 27493 | 27410 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1061 | 1061 | 0 | 0 |
OutputsKnown_A | 410018267 | 409163192 | 0 | 0 |
gen_flops.OutputDelay_A | 410018267 | 409129715 | 0 | 2772 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1061 | 1061 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409163192 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 617 | 547 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 702 | 609 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018267 | 409129715 | 0 | 2772 |
T1 | 136951 | 136946 | 0 | 3 |
T2 | 89167 | 85646 | 0 | 3 |
T3 | 385455 | 385438 | 0 | 3 |
T4 | 617 | 544 | 0 | 3 |
T5 | 1625 | 1478 | 0 | 3 |
T6 | 702 | 606 | 0 | 3 |
T7 | 816749 | 816596 | 0 | 3 |
T16 | 2577 | 2503 | 0 | 3 |
T17 | 96549 | 96449 | 0 | 3 |
T18 | 27493 | 27410 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1061 | 1061 | 0 | 0 |
OutputsKnown_A | 410018195 | 409163120 | 0 | 0 |
gen_no_flops.OutputDelay_A | 410018195 | 409163120 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1061 | 1061 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018195 | 409163120 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 617 | 547 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 702 | 609 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018195 | 409163120 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 617 | 547 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 702 | 609 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1061 | 1061 | 0 | 0 |
OutputsKnown_A | 409997818 | 409142743 | 0 | 0 |
gen_flops.OutputDelay_A | 409997818 | 409109416 | 0 | 2622 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1061 | 1061 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 409997818 | 409142743 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 456 | 386 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 484 | 391 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 409997818 | 409109416 | 0 | 2622 |
T1 | 136951 | 136946 | 0 | 3 |
T2 | 89167 | 85646 | 0 | 3 |
T3 | 385455 | 385438 | 0 | 3 |
T4 | 456 | 386 | 0 | 0 |
T5 | 1625 | 1478 | 0 | 3 |
T6 | 484 | 391 | 0 | 0 |
T7 | 816749 | 816596 | 0 | 3 |
T8 | 0 | 0 | 0 | 3 |
T9 | 0 | 0 | 0 | 3 |
T16 | 2577 | 2503 | 0 | 3 |
T17 | 96549 | 96449 | 0 | 3 |
T18 | 27493 | 27410 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1061 | 1061 | 0 | 0 |
OutputsKnown_A | 410018195 | 409163120 | 0 | 0 |
gen_no_flops.OutputDelay_A | 410018195 | 409163120 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1061 | 1061 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018195 | 409163120 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 617 | 547 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 702 | 609 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018195 | 409163120 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 617 | 547 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 702 | 609 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1061 | 1061 | 0 | 0 |
OutputsKnown_A | 410018195 | 409163120 | 0 | 0 |
gen_flops.OutputDelay_A | 410018195 | 409129658 | 0 | 2772 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1061 | 1061 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018195 | 409163120 | 0 | 0 |
T1 | 136951 | 136946 | 0 | 0 |
T2 | 89167 | 85781 | 0 | 0 |
T3 | 385455 | 385439 | 0 | 0 |
T4 | 617 | 547 | 0 | 0 |
T5 | 1625 | 1484 | 0 | 0 |
T6 | 702 | 609 | 0 | 0 |
T7 | 816749 | 816602 | 0 | 0 |
T16 | 2577 | 2506 | 0 | 0 |
T17 | 96549 | 96452 | 0 | 0 |
T18 | 27493 | 27413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410018195 | 409129658 | 0 | 2772 |
T1 | 136951 | 136946 | 0 | 3 |
T2 | 89167 | 85646 | 0 | 3 |
T3 | 385455 | 385438 | 0 | 3 |
T4 | 617 | 544 | 0 | 3 |
T5 | 1625 | 1478 | 0 | 3 |
T6 | 702 | 606 | 0 | 3 |
T7 | 816749 | 816596 | 0 | 3 |
T16 | 2577 | 2503 | 0 | 3 |
T17 | 96549 | 96449 | 0 | 3 |
T18 | 27493 | 27410 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |