Unified Coverage Report :: Module :: tlul_lc_gate

Module : tlul_lc_gate

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.63	88.24	94.44		57.14	83.33	50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tl_gate	72.29	86.27	88.89		57.14	79.17	50.00
tb.dut.u_prog_tl_gate	72.41	88.24	83.33		57.14	83.33	50.00

---

Module Instance : tb.dut.u_tl_gate

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.29	86.27	88.89		57.14	79.17	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.15	93.94	80.00		57.14	77.14	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d	100.00	100.00
u_err_en_sync	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00
u_tlul_err_resp	84.34	97.96	72.73			66.67	100.00

---

Module Instance : tb.dut.u_prog_tl_gate

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.41	88.24	83.33		57.14	83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.73	95.45	90.00		57.14	88.57	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	97.14	92.91	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d	100.00	100.00
u_err_en_sync	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00
u_tlul_err_resp	98.86	100.00	95.45			100.00	100.00

Line Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
TOTAL		51	45	88.24
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	144	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	153	6	6	100.00
ALWAYS	164	28	22	78.57
ALWAYS	230	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	1	1
85	1	1
144	3	3
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
186	1	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
			==> MISSING_ELSE
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : tlul_lc_gate

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T4

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T10,T11,T12
1	Covered	T3,T4,T6

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

FSM Coverage for Module : tlul_lc_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	7	4	57.14
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Covered	T1,T2,T3
StError	184	Covered	T1,T2,T3
StErrorOutstanding	203	Covered	T1,T2,T3
StFlush	184	Not Covered
StOutstanding	174	Covered	T3,T4,T6

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Covered	T3,T4,T6
StError->StErrorOutstanding	203	Covered	T1,T2,T3
StErrorOutstanding->StActive	211	Covered	T1,T2,T3
StFlush->StActive	196	Not Covered
StFlush->StError	194	Not Covered
StOutstanding->StError	184	Covered	T3,T4,T6
StOutstanding->StFlush	184	Not Covered

---

Branch Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
Branches		24	20	83.33
IF	144	2	2	100.00
IF	153	4	4	100.00
CASE	171	14	10	71.43
IF	234	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Covered	T3,T4,T6
StActive	0	-	-	-	-	-	-	Covered	T1,T2,T3
StActive	-	1	-	-	-	-	-	Covered	T1,T2,T4
StActive	-	0	-	-	-	-	-	Covered	T1,T2,T3
StOutstanding	-	-	1	-	-	-	-	Covered	T3,T4,T6
StOutstanding	-	-	0	-	-	-	-	Covered	T10,T11,T12
StFlush	-	-	-	1	-	-	-	Not Covered
StFlush	-	-	-	0	1	-	-	Not Covered
StFlush	-	-	-	0	0	-	-	Not Covered
StError	-	-	-	-	-	1	-	Covered	T2,T3,T4
StError	-	-	-	-	-	0	-	Covered	T3,T4,T6
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T1,T2,T3
StErrorOutstanding	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_lc_gate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	832327816	0	0	0
u_state_regs_A	832327816	830617666	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	832327816	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	832327816	830617666	0	0
T1	273902	273892	0	0
T2	178334	171562	0	0
T3	770910	770878	0	0
T4	1234	1094	0	0
T5	3250	2968	0	0
T6	1404	1218	0	0
T7	1633498	1633204	0	0
T16	5154	5012	0	0
T17	193098	192904	0	0
T18	54986	54826	0	0

Line Coverage for Instance : tb.dut.u_tl_gate

	Line No.	Total	Covered	Percent
TOTAL		51	44	86.27
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	144	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	153	6	6	100.00
ALWAYS	164	28	21	75.00
ALWAYS	230	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	1	1
85	1	1
144	3	3
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
186	0	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
			==> MISSING_ELSE
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_tl_gate

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T18,T8

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T9,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T18,T8

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T18,T8

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T18,T8

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T18,T8

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T4,T6

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_tl_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	7	4	57.14
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Covered	T1,T2,T3
StError	184	Covered	T1,T2,T3
StErrorOutstanding	203	Covered	T1,T2,T3
StFlush	184	Not Covered
StOutstanding	174	Covered	T3,T4,T6

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Covered	T3,T4,T6
StError->StErrorOutstanding	203	Covered	T1,T2,T3
StErrorOutstanding->StActive	211	Covered	T1,T2,T3
StFlush->StActive	196	Not Covered
StFlush->StError	194	Not Covered
StOutstanding->StError	184	Covered	T3,T4,T6
StOutstanding->StFlush	184	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tl_gate

	Line No.	Total	Covered	Percent
Branches		24	19	79.17
IF	144	2	2	100.00
IF	153	4	4	100.00
CASE	171	14	9	64.29
IF	234	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T18,T8
0	0	1	Covered	T7,T18,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Covered	T3,T4,T6
StActive	0	-	-	-	-	-	-	Covered	T1,T2,T3
StActive	-	1	-	-	-	-	-	Covered	T7,T18,T8
StActive	-	0	-	-	-	-	-	Covered	T1,T2,T3
StOutstanding	-	-	1	-	-	-	-	Covered	T3,T4,T6
StOutstanding	-	-	0	-	-	-	-	Not Covered
StFlush	-	-	-	1	-	-	-	Not Covered
StFlush	-	-	-	0	1	-	-	Not Covered
StFlush	-	-	-	0	0	-	-	Not Covered
StError	-	-	-	-	-	1	-	Covered	T2,T3,T4
StError	-	-	-	-	-	0	-	Covered	T3,T4,T6
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T1,T2,T3
StErrorOutstanding	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_gate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	416163908	0	0	0
u_state_regs_A	416163908	415308833	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0

Line Coverage for Instance : tb.dut.u_prog_tl_gate

	Line No.	Total	Covered	Percent
TOTAL		51	45	88.24
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	144	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	153	6	6	100.00
ALWAYS	164	28	22	78.57
ALWAYS	230	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84	1	1
85	1	1
144	3	3
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
182	1	1
183	1	1
184	1	1
186	1	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
196	0	1
			==> MISSING_ELSE
201	1	1
202	1	1
203	1	1
			MISSING_ELSE
208	1	1
209	1	1
210	1	1
211	1	1
			==> MISSING_ELSE
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_prog_tl_gate

	Total	Covered	Percent
Conditions	18	15	83.33
Logical	18	15	83.33
Non-Logical	0	0
Event	0	0

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T10,T11,T12
1	Covered	T3,T4,T6

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_prog_tl_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	7	4	57.14
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	196	Covered	T1,T2,T3
StError	184	Covered	T1,T2,T3
StErrorOutstanding	203	Covered	T1,T2,T3
StFlush	184	Not Covered
StOutstanding	174	Covered	T3,T4,T6

transitions	Line No.	Covered	Tests
StActive->StOutstanding	174	Covered	T3,T4,T6
StError->StErrorOutstanding	203	Covered	T1,T2,T3
StErrorOutstanding->StActive	211	Covered	T1,T2,T3
StFlush->StActive	196	Not Covered
StFlush->StError	194	Not Covered
StOutstanding->StError	184	Covered	T3,T4,T6
StOutstanding->StFlush	184	Not Covered

---

Branch Coverage for Instance : tb.dut.u_prog_tl_gate

	Line No.	Total	Covered	Percent
Branches		24	20	83.33
IF	144	2	2	100.00
IF	153	4	4	100.00
CASE	171	14	10	71.43
IF	234	2	2	100.00
IF	239	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((!rst_ni))
-2-:	155	if ((a_ack && (!d_ack)))
-3-:	157	if ((d_ack && (!a_ack)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	case (state_q)
-2-:	173	if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-:	176	if ((outstanding_txn != '0))
-4-:	183	if ((outstanding_txn == '0))
-5-:	193	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-:	195	if ((!flush_req_i))
-7-:	202	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-:	210	if ((outstanding_txn == '0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Covered	T3,T4,T6
StActive	0	-	-	-	-	-	-	Covered	T1,T2,T3
StActive	-	1	-	-	-	-	-	Covered	T1,T2,T4
StActive	-	0	-	-	-	-	-	Covered	T1,T2,T3
StOutstanding	-	-	1	-	-	-	-	Covered	T3,T4,T6
StOutstanding	-	-	0	-	-	-	-	Covered	T10,T11,T12
StFlush	-	-	-	1	-	-	-	Not Covered
StFlush	-	-	-	0	1	-	-	Not Covered
StFlush	-	-	-	0	0	-	-	Not Covered
StError	-	-	-	-	-	1	-	Covered	T2,T3,T4
StError	-	-	-	-	-	0	-	Covered	T3,T4,T6
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T1,T2,T3
StErrorOutstanding	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	234	if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	239	if (block_cmd)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prog_tl_gate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	416163908	0	0	0
u_state_regs_A	416163908	415308833	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416163908	415308833	0	0
T1	136951	136946	0	0
T2	89167	85781	0	0
T3	385455	385439	0	0
T4	617	547	0	0
T5	1625	1484	0	0
T6	702	609	0	0
T7	816749	816602	0	0
T16	2577	2506	0	0
T17	96549	96452	0	0
T18	27493	27413	0	0