Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22198	1		T53	8		T54	8		T195	13
full_word	4335852	1		T1	16568		T3	10		T5	376

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4357790	1		T1	16568		T3	10		T5	376
auto[TlIntgErrCmd]	69	1		T53	3		T54	2		T195	9
auto[TlIntgErrData]	95	1		T53	4		T54	2		T195	3
auto[TlIntgErrBoth]	96	1		T53	2		T54	5		T195	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4329520	1		T1	16568		T3	10		T5	376
auto[1]	28530	1		T53	5		T54	7		T195	12

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1577	1		T217	7		T218	104		T219	12
auto[TlIntgErrNone]	partial	auto[1]	20384	1		T217	105		T218	800		T219	175
auto[TlIntgErrNone]	full_word	auto[0]	4327846	1		T1	16568		T3	10		T5	376
auto[TlIntgErrNone]	full_word	auto[1]	7983	1		T217	19		T218	452		T219	48
auto[TlIntgErrCmd]	partial	auto[0]	18	1		T53	1		T195	2		T227	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T53	2		T54	2		T195	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T195	1		T220	1		T356	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T195	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1		T53	2		T54	1		T195	1
auto[TlIntgErrData]	partial	auto[1]	39	1		T53	1		T54	1		T195	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T53	1		T357	1		T353	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T195	1		T220	1		T231	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1		T54	1		T195	2		T227	1
auto[TlIntgErrBoth]	partial	auto[1]	64	1		T53	2		T54	3		T195	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T54	1		T195	2		T354	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23276452	1		T1	8875		T2	9775		T3	380
full_word	7599446	1		T1	6606		T2	334		T3	154

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30875618	1		T1	15481		T2	10109		T3	534
auto[TlIntgErrCmd]	96	1		T53	3		T54	2		T195	7
auto[TlIntgErrData]	81	1		T53	4		T54	1		T195	5
auto[TlIntgErrBoth]	103	1		T53	3		T54	7		T195	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26575599	1		T1	13242		T2	9848		T3	445
auto[1]	4300299	1		T1	2239		T2	261		T3	89

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22660839	1		T1	8281		T2	9755		T3	361
auto[TlIntgErrNone]	partial	auto[1]	615360	1		T1	594		T2	20		T3	19
auto[TlIntgErrNone]	full_word	auto[0]	3914648	1		T1	4961		T2	93		T3	84
auto[TlIntgErrNone]	full_word	auto[1]	3684771	1		T1	1645		T2	241		T3	70
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T54	1		T195	4		T220	5
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T53	3		T54	1		T195	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T357	1		T358	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T220	1		T352	1		T359	1
auto[TlIntgErrData]	partial	auto[0]	34	1		T53	3		T195	2		T220	4
auto[TlIntgErrData]	partial	auto[1]	37	1		T53	1		T54	1		T195	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T231	1		T354	2		T353	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T195	1		T359	1		T266	2
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T53	1		T54	1		T195	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T53	2		T54	4		T195	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T54	1		T231	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T54	1		T352	1		T353	3