Unified Coverage Report :: Module :: flash_ctrl_prim_reg_top

Module : flash_ctrl_prim_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.94	99.31	95.82	100.00		99.56	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	80.00						gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_chk	100.00	100.00		100.00			100.00
u_csr0_regwen	100.00	100.00	100.00			100.00
u_csr10	100.00	100.00	100.00			100.00
u_csr11	100.00	100.00	100.00			100.00
u_csr12	100.00	100.00	100.00			100.00
u_csr13_field0	100.00	100.00	100.00			100.00
u_csr13_field1	100.00	100.00	100.00			100.00
u_csr14_field0	100.00	100.00	100.00			100.00
u_csr14_field1	100.00	100.00	100.00			100.00
u_csr15_field0	100.00	100.00	100.00			100.00
u_csr15_field1	100.00	100.00	100.00			100.00
u_csr16_field0	100.00	100.00	100.00			100.00
u_csr16_field1	100.00	100.00	100.00			100.00
u_csr17_field0	100.00	100.00	100.00			100.00
u_csr17_field1	100.00	100.00	100.00			100.00
u_csr18	100.00	100.00	100.00			100.00
u_csr19	100.00	100.00	100.00			100.00
u_csr1_field0	100.00	100.00	100.00			100.00
u_csr1_field1	100.00	100.00	100.00			100.00
u_csr20_field0	88.89	100.00	66.67			100.00
u_csr20_field1	88.89	100.00	66.67			100.00
u_csr20_field2	55.19	55.56	50.00			60.00
u_csr2_field0	88.89	100.00	66.67			100.00
u_csr2_field1	88.89	100.00	66.67			100.00
u_csr2_field2	88.89	100.00	66.67			100.00
u_csr2_field3	96.30	100.00	88.89			100.00
u_csr2_field4	88.89	100.00	66.67			100.00
u_csr2_field5	88.89	100.00	66.67			100.00
u_csr2_field6	88.89	100.00	66.67			100.00
u_csr2_field7	96.30	100.00	88.89			100.00
u_csr3_field0	100.00	100.00	100.00			100.00
u_csr3_field1	100.00	100.00	100.00			100.00
u_csr3_field2	100.00	100.00	100.00			100.00
u_csr3_field3	100.00	100.00	100.00			100.00
u_csr3_field4	100.00	100.00	100.00			100.00
u_csr3_field5	100.00	100.00	100.00			100.00
u_csr3_field6	100.00	100.00	100.00			100.00
u_csr3_field7	100.00	100.00	100.00			100.00
u_csr3_field8	100.00	100.00	100.00			100.00
u_csr3_field9	100.00	100.00	100.00			100.00
u_csr4_field0	100.00	100.00	100.00			100.00
u_csr4_field1	100.00	100.00	100.00			100.00
u_csr4_field2	100.00	100.00	100.00			100.00
u_csr4_field3	100.00	100.00	100.00			100.00
u_csr5_field0	100.00	100.00	100.00			100.00
u_csr5_field1	100.00	100.00	100.00			100.00
u_csr5_field2	100.00	100.00	100.00			100.00
u_csr5_field3	100.00	100.00	100.00			100.00
u_csr5_field4	100.00	100.00	100.00			100.00
u_csr6_field0	100.00	100.00	100.00			100.00
u_csr6_field1	100.00	100.00	100.00			100.00
u_csr6_field2	100.00	100.00	100.00			100.00
u_csr6_field3	100.00	100.00	100.00			100.00
u_csr6_field4	100.00	100.00	100.00			100.00
u_csr6_field5	100.00	100.00	100.00			100.00
u_csr6_field6	100.00	100.00	100.00			100.00
u_csr6_field7	100.00	100.00	100.00			100.00
u_csr6_field8	100.00	100.00	100.00			100.00
u_csr7_field0	100.00	100.00	100.00			100.00
u_csr7_field1	100.00	100.00	100.00			100.00
u_csr8	100.00	100.00	100.00			100.00
u_csr9	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_prim_reg_top

	Line No.	Total	Covered	Percent
TOTAL		219	219	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	851	1	1	100.00
CONT_ASSIGN	964	1	1	100.00
CONT_ASSIGN	1104	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1411	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1473	1	1	100.00
CONT_ASSIGN	1504	1	1	100.00
CONT_ASSIGN	1535	1	1	100.00
CONT_ASSIGN	1566	1	1	100.00
CONT_ASSIGN	1625	1	1	100.00
CONT_ASSIGN	1684	1	1	100.00
CONT_ASSIGN	1743	1	1	100.00
CONT_ASSIGN	1802	1	1	100.00
CONT_ASSIGN	1861	1	1	100.00
CONT_ASSIGN	1892	1	1	100.00
ALWAYS	2006	22	22	100.00
CONT_ASSIGN	2030	1	1	100.00
ALWAYS	2034	1	1	100.00
CONT_ASSIGN	2059	1	1	100.00
CONT_ASSIGN	2061	1	1	100.00
CONT_ASSIGN	2062	1	1	100.00
CONT_ASSIGN	2064	1	1	100.00
CONT_ASSIGN	2066	1	1	100.00
CONT_ASSIGN	2067	1	1	100.00
CONT_ASSIGN	2069	1	1	100.00
CONT_ASSIGN	2071	1	1	100.00
CONT_ASSIGN	2073	1	1	100.00
CONT_ASSIGN	2075	1	1	100.00
CONT_ASSIGN	2077	1	1	100.00
CONT_ASSIGN	2079	1	1	100.00
CONT_ASSIGN	2081	1	1	100.00
CONT_ASSIGN	2083	1	1	100.00
CONT_ASSIGN	2084	1	1	100.00
CONT_ASSIGN	2086	1	1	100.00
CONT_ASSIGN	2088	1	1	100.00
CONT_ASSIGN	2090	1	1	100.00
CONT_ASSIGN	2092	1	1	100.00
CONT_ASSIGN	2094	1	1	100.00
CONT_ASSIGN	2096	1	1	100.00
CONT_ASSIGN	2098	1	1	100.00
CONT_ASSIGN	2100	1	1	100.00
CONT_ASSIGN	2102	1	1	100.00
CONT_ASSIGN	2104	1	1	100.00
CONT_ASSIGN	2105	1	1	100.00
CONT_ASSIGN	2107	1	1	100.00
CONT_ASSIGN	2109	1	1	100.00
CONT_ASSIGN	2111	1	1	100.00
CONT_ASSIGN	2113	1	1	100.00
CONT_ASSIGN	2114	1	1	100.00
CONT_ASSIGN	2116	1	1	100.00
CONT_ASSIGN	2118	1	1	100.00
CONT_ASSIGN	2120	1	1	100.00
CONT_ASSIGN	2122	1	1	100.00
CONT_ASSIGN	2124	1	1	100.00
CONT_ASSIGN	2125	1	1	100.00
CONT_ASSIGN	2127	1	1	100.00
CONT_ASSIGN	2129	1	1	100.00
CONT_ASSIGN	2131	1	1	100.00
CONT_ASSIGN	2133	1	1	100.00
CONT_ASSIGN	2135	1	1	100.00
CONT_ASSIGN	2137	1	1	100.00
CONT_ASSIGN	2139	1	1	100.00
CONT_ASSIGN	2141	1	1	100.00
CONT_ASSIGN	2143	1	1	100.00
CONT_ASSIGN	2144	1	1	100.00
CONT_ASSIGN	2146	1	1	100.00
CONT_ASSIGN	2148	1	1	100.00
CONT_ASSIGN	2149	1	1	100.00
CONT_ASSIGN	2151	1	1	100.00
CONT_ASSIGN	2152	1	1	100.00
CONT_ASSIGN	2154	1	1	100.00
CONT_ASSIGN	2155	1	1	100.00
CONT_ASSIGN	2157	1	1	100.00
CONT_ASSIGN	2158	1	1	100.00
CONT_ASSIGN	2160	1	1	100.00
CONT_ASSIGN	2161	1	1	100.00
CONT_ASSIGN	2163	1	1	100.00
CONT_ASSIGN	2164	1	1	100.00
CONT_ASSIGN	2166	1	1	100.00
CONT_ASSIGN	2168	1	1	100.00
CONT_ASSIGN	2169	1	1	100.00
CONT_ASSIGN	2171	1	1	100.00
CONT_ASSIGN	2173	1	1	100.00
CONT_ASSIGN	2174	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2179	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2183	1	1	100.00
CONT_ASSIGN	2184	1	1	100.00
CONT_ASSIGN	2186	1	1	100.00
CONT_ASSIGN	2188	1	1	100.00
CONT_ASSIGN	2189	1	1	100.00
CONT_ASSIGN	2191	1	1	100.00
CONT_ASSIGN	2192	1	1	100.00
CONT_ASSIGN	2194	1	1	100.00
CONT_ASSIGN	2195	1	1	100.00
CONT_ASSIGN	2197	1	1	100.00
CONT_ASSIGN	2199	1	1	100.00
ALWAYS	2203	22	22	100.00
ALWAYS	2229	63	63	100.00
CONT_ASSIGN	2366	0	0
CONT_ASSIGN	2374	1	1	100.00
CONT_ASSIGN	2375	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
299	1	1
576	1	1
851	1	1
964	1	1
1104	1	1
1352	1	1
1411	1	1
1442	1	1
1473	1	1
1504	1	1
1535	1	1
1566	1	1
1625	1	1
1684	1	1
1743	1	1
1802	1	1
1861	1	1
1892	1	1
2006	1	1
2007	1	1
2008	1	1
2009	1	1
2010	1	1
2011	1	1
2012	1	1
2013	1	1
2014	1	1
2015	1	1
2016	1	1
2017	1	1
2018	1	1
2019	1	1
2020	1	1
2021	1	1
2022	1	1
2023	1	1
2024	1	1
2025	1	1
2026	1	1
2027	1	1
2030	1	1
2034	1	1
2059	1	1
2061	1	1
2062	1	1
2064	1	1
2066	1	1
2067	1	1
2069	1	1
2071	1	1
2073	1	1
2075	1	1
2077	1	1
2079	1	1
2081	1	1
2083	1	1
2084	1	1
2086	1	1
2088	1	1
2090	1	1
2092	1	1
2094	1	1
2096	1	1
2098	1	1
2100	1	1
2102	1	1
2104	1	1
2105	1	1
2107	1	1
2109	1	1
2111	1	1
2113	1	1
2114	1	1
2116	1	1
2118	1	1
2120	1	1
2122	1	1
2124	1	1
2125	1	1
2127	1	1
2129	1	1
2131	1	1
2133	1	1
2135	1	1
2137	1	1
2139	1	1
2141	1	1
2143	1	1
2144	1	1
2146	1	1
2148	1	1
2149	1	1
2151	1	1
2152	1	1
2154	1	1
2155	1	1
2157	1	1
2158	1	1
2160	1	1
2161	1	1
2163	1	1
2164	1	1
2166	1	1
2168	1	1
2169	1	1
2171	1	1
2173	1	1
2174	1	1
2176	1	1
2178	1	1
2179	1	1
2181	1	1
2183	1	1
2184	1	1
2186	1	1
2188	1	1
2189	1	1
2191	1	1
2192	1	1
2194	1	1
2195	1	1
2197	1	1
2199	1	1
2203	1	1
2204	1	1
2205	1	1
2206	1	1
2207	1	1
2208	1	1
2209	1	1
2210	1	1
2211	1	1
2212	1	1
2213	1	1
2214	1	1
2215	1	1
2216	1	1
2217	1	1
2218	1	1
2219	1	1
2220	1	1
2221	1	1
2222	1	1
2223	1	1
2224	1	1
2229	1	1
2230	1	1
2232	1	1
2236	1	1
2237	1	1
2241	1	1
2242	1	1
2243	1	1
2244	1	1
2245	1	1
2246	1	1
2247	1	1
2248	1	1
2252	1	1
2253	1	1
2254	1	1
2255	1	1
2256	1	1
2257	1	1
2258	1	1
2259	1	1
2260	1	1
2261	1	1
2265	1	1
2266	1	1
2267	1	1
2268	1	1
2272	1	1
2273	1	1
2274	1	1
2275	1	1
2276	1	1
2280	1	1
2281	1	1
2282	1	1
2283	1	1
2284	1	1
2285	1	1
2286	1	1
2287	1	1
2288	1	1
2292	1	1
2293	1	1
2297	1	1
2301	1	1
2305	1	1
2309	1	1
2313	1	1
2317	1	1
2318	1	1
2322	1	1
2323	1	1
2327	1	1
2328	1	1
2332	1	1
2333	1	1
2337	1	1
2338	1	1
2342	1	1
2346	1	1
2350	1	1
2351	1	1
2352	1	1
2366		unreachable
2374	1	1
2375	1	1

---

Cond Coverage for Module : flash_ctrl_prim_reg_top

	Total	Covered	Percent
Conditions	287	287	100.00
Logical	287	287	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T217,T220
1	1	Covered	T53,T54,T55

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T14,T15
1	0	Covered	T53,T54,T195

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T11,T14,T15
0	1	0	Covered	T53,T54,T195
1	0	0	Covered	T11,T14,T15

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T53,T54,T195
0	1	0	Covered	T217,T218,T219
1	0	0	Covered	T217,T218,T225

 LINE       299
 EXPRESSION (csr1_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T54,T221,T253
1	1	Covered	T53,T54,T55

 LINE       576
 EXPRESSION (csr3_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T221
1	1	Covered	T53,T54,T55

 LINE       851
 EXPRESSION (csr4_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T221
1	1	Covered	T53,T54,T55

 LINE       964
 EXPRESSION (csr5_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T55
1	1	Covered	T53,T54,T195

 LINE       1104
 EXPRESSION (csr6_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T55
1	1	Covered	T53,T54,T195

 LINE       1352
 EXPRESSION (csr7_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T221
1	1	Covered	T53,T54,T55

 LINE       1411
 EXPRESSION (csr8_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T221
1	1	Covered	T53,T54,T55

 LINE       1442
 EXPRESSION (csr9_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T221
1	1	Covered	T53,T54,T55

 LINE       1473
 EXPRESSION (csr10_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T54,T55,T221
1	1	Covered	T53,T54,T195

 LINE       1504
 EXPRESSION (csr11_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T221
1	1	Covered	T53,T54,T55

 LINE       1535
 EXPRESSION (csr12_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T55
1	1	Covered	T53,T54,T253

 LINE       1566
 EXPRESSION (csr13_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T221
1	1	Covered	T53,T54,T55

 LINE       1625
 EXPRESSION (csr14_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T55
1	1	Covered	T53,T54,T195

 LINE       1684
 EXPRESSION (csr15_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T221
1	1	Covered	T53,T54,T55

 LINE       1743
 EXPRESSION (csr16_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T55
1	1	Covered	T53,T54,T253

 LINE       1802
 EXPRESSION (csr17_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T221
1	1	Covered	T53,T54,T55

 LINE       1861
 EXPRESSION (csr18_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T55
1	1	Covered	T53,T54,T221

 LINE       1892
 EXPRESSION (csr19_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T54,T221
1	1	Covered	T53,T54,T55

 LINE       2007
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR0_REGWEN_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T6,T124,T145

 LINE       2008
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR1_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T124,T149,T184

 LINE       2009
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR2_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T36,T124,T60

 LINE       2010
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR3_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T124,T317,T149

 LINE       2011
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR4_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T124,T151,T318

 LINE       2012
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR5_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T124,T60,T184

 LINE       2013
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR6_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T48,T105,T94

 LINE       2014
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR7_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T124,T60,T318

 LINE       2015
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR8_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T26,T124,T60

 LINE       2016
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR9_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T46,T124,T60

 LINE       2017
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR10_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T6,T29
1	Covered	T16,T29,T194

 LINE       2018
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR11_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T124,T151,T302

 LINE       2019
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR12_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T124,T61,T151

 LINE       2020
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR13_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T124,T143,T156

 LINE       2021
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR14_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T120,T124,T151

 LINE       2022
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR15_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T124,T149,T151

 LINE       2023
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR16_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T124,T319,T149

 LINE       2024
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR17_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T48,T124,T145

 LINE       2025
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR18_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T124,T149,T291

 LINE       2026
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR19_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T29,T124,T320

 LINE       2027
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR20_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T6,T16
1	Covered	T120,T124,T127

 LINE       2030
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T53,T54,T55

 LINE       2030
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T54,T55
1	0	Covered	T53,T54,T55

 LINE       2034
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T46
1	0	Covered	T53,T54,T55
1	1	Covered	T53,T54,T195

 LINE       2034
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T2,T6,T16
21 (addr_hit[20] & ((|(4'...	Covered	T124,T127,T184
20 (addr_hit[19] & ((|(4'...	Covered	T124,T320,T318
19 (addr_hit[18] & ((|(4'...	Covered	T124,T149,T291
18 (addr_hit[17] & ((|(4'...	Covered	T124,T145,T93
17 (addr_hit[16] & ((|(4'...	Covered	T319,T149,T166
16 (addr_hit[15] & ((|(4'...	Covered	T124,T151,T156
15 (addr_hit[14] & ((|(4'...	Covered	T120,T124,T151
14 (addr_hit[13] & ((|(4'...	Covered	T124,T143,T156
13 (addr_hit[12] & ((|(4'...	Covered	T124,T184,T99
12 (addr_hit[11] & ((|(4'...	Covered	T26,T124,T151
11 (addr_hit[10] & ((|(4'...	Covered	T29,T194,T36
10 (addr_hit[9] & ((|(4'b...	Covered	T46,T124,T60
9 (addr_hit[8] & ((|(4'b...	Covered	T26,T124,T60
8 (addr_hit[7] & ((|(4'b...	Covered	T124,T60,T318
7 (addr_hit[6] & ((|(4'b...	Covered	T48,T94,T151
6 (addr_hit[5] & ((|(4'b...	Covered	T124,T60,T166
5 (addr_hit[4] & ((|(4'b...	Covered	T124,T318,T321
4 (addr_hit[3] & ((|(4'b...	Covered	T124,T317,T149
3 (addr_hit[2] & ((|(4'b...	Covered	T124,T318,T321
2 (addr_hit[1] & ((|(4'b...	Covered	T124,T149,T184
1 (addr_hit[0] & ((|(4'b...	Covered	T6,T124,T318

 LINE       2034
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T124,T145,T94
1	1	Covered	T6,T124,T318

 LINE       2034
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T124,T322,T321
1	1	Covered	T124,T149,T184

 LINE       2034
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T36,T124,T60
1	1	Covered	T124,T318,T321

 LINE       2034
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T321,T323,T324
1	1	Covered	T124,T317,T149

 LINE       2034
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T124,T151,T318
1	1	Covered	T124,T318,T321

 LINE       2034
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T184,T158,T321
1	1	Covered	T124,T60,T166

 LINE       2034
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T105,T302,T318
1	1	Covered	T48,T94,T151

 LINE       2034
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T321,T325,T323
1	1	Covered	T124,T60,T318

 LINE       2034
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T60,T318,T326
1	1	Covered	T26,T124,T60

 LINE       2034
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T124,T321,T327
1	1	Covered	T46,T124,T60

 LINE       2034
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T16,T318,T321
1	1	Covered	T29,T194,T36

 LINE       2034
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T318,T328,T329
1	1	Covered	T26,T124,T151

 LINE       2034
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T61,T151,T318
1	1	Covered	T124,T184,T99

 LINE       2034
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T321,T323,T330
1	1	Covered	T124,T143,T156

 LINE       2034
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T184,T318,T326
1	1	Covered	T120,T124,T151

 LINE       2034
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T124,T149,T318
1	1	Covered	T124,T151,T156

 LINE       2034
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T124,T318,T321
1	1	Covered	T319,T149,T166

 LINE       2034
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T48,T60,T149
1	1	Covered	T124,T145,T93

 LINE       2034
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T124,T318,T321
1	1	Covered	T124,T149,T291

 LINE       2034
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T29,T124,T166
1	1	Covered	T124,T320,T318

 LINE       2034
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T29
1	0	Covered	T120,T60,T318
1	1	Covered	T124,T127,T184

 LINE       2059
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T6,T48,T124
1	1	0	Covered	T217,T218,T230
1	1	1	Covered	T53,T54,T55

 LINE       2062
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T31,T124,T145
1	1	0	Covered	T217,T218,T226
1	1	1	Covered	T53,T54,T55

 LINE       2067
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T16,T36,T124
1	1	0	Covered	T195,T218,T225
1	1	1	Covered	T53,T54,T55

 LINE       2084
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T124,T317,T149
1	1	0	Covered	T218,T225,T228
1	1	1	Covered	T53,T54,T55

 LINE       2105
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T29,T124,T151
1	1	0	Covered	T218,T225,T228
1	1	1	Covered	T53,T54,T55

 LINE       2114
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T124,T60,T184
1	1	0	Covered	T225,T228,T259
1	1	1	Covered	T53,T54,T55

 LINE       2125
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T194,T48,T105
1	1	0	Covered	T195,T217,T220
1	1	1	Covered	T53,T54,T55

 LINE       2144
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T124,T60,T331
1	1	0	Covered	T53,T217,T218
1	1	1	Covered	T53,T54,T55

 LINE       2149
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T26,T124,T60
1	1	0	Covered	T217,T219,T228
1	1	1	Covered	T53,T54,T55

 LINE       2152
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T46,T124,T25
1	1	0	Covered	T217,T220,T218
1	1	1	Covered	T53,T54,T55

 LINE       2155
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T16,T29,T194
1	1	0	Covered	T218,T228,T259
1	1	1	Covered	T53,T54,T55

 LINE       2158
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T46,T26,T124
1	1	0	Covered	T53,T218,T225
1	1	1	Covered	T53,T54,T55

 LINE       2161
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T124,T61,T151
1	1	0	Covered	T54,T225,T228
1	1	1	Covered	T53,T54,T55

 LINE       2164
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T124,T60,T143
1	1	0	Covered	T220,T218,T225
1	1	1	Covered	T53,T54,T55

 LINE       2169
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T120,T124,T151
1	1	0	Covered	T54,T218,T228
1	1	1	Covered	T53,T54,T55

 LINE       2174
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T169,T124,T149
1	1	0	Covered	T218,T219,T225
1	1	1	Covered	T53,T54,T55

 LINE       2179
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T124,T319,T149
1	1	0	Covered	T220,T218,T226
1	1	1	Covered	T53,T54,T55

 LINE       2184
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T48,T36,T21
1	1	0	Covered	T217,T218,T228
1	1	1	Covered	T53,T54,T55

 LINE       2189
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T124,T61,T149
1	1	0	Covered	T218,T227,T228
1	1	1	Covered	T53,T54,T55

 LINE       2192
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T29,T124,T320
1	1	0	Covered	T54,T218,T225
1	1	1	Covered	T53,T54,T55

 LINE       2195
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T54,T55
1	0	1	Covered	T120,T124,T127
1	1	0	Covered	T218,T226,T228
1	1	1	Covered	T53,T54,T55

---

Branch Coverage for Module : flash_ctrl_prim_reg_top

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	2030	2	2	100.00
IF	68	3	3	100.00
CASE	2230	22	22	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2030	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T53,T54,T55
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T14,T15
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	2230	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T3,T4
addr_hit[1]	Covered	T1,T3,T4
addr_hit[2]	Covered	T1,T3,T4
addr_hit[3]	Covered	T1,T3,T4
addr_hit[4]	Covered	T1,T3,T4
addr_hit[5]	Covered	T1,T3,T4
addr_hit[6]	Covered	T1,T3,T4
addr_hit[7]	Covered	T1,T3,T4
addr_hit[8]	Covered	T1,T3,T4
addr_hit[9]	Covered	T1,T3,T4
addr_hit[10]	Covered	T1,T3,T4
addr_hit[11]	Covered	T1,T3,T4
addr_hit[12]	Covered	T1,T3,T4
addr_hit[13]	Covered	T1,T3,T4
addr_hit[14]	Covered	T1,T3,T4
addr_hit[15]	Covered	T1,T3,T4
addr_hit[16]	Covered	T1,T3,T4
addr_hit[17]	Covered	T1,T3,T4
addr_hit[18]	Covered	T1,T3,T4
addr_hit[19]	Covered	T1,T3,T4
addr_hit[20]	Covered	T1,T3,T4
default	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_ctrl_prim_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	442382185	56661	0	0
reAfterRv	442382185	56661	0	0
rePulse	442382185	37728	0	0
wePulse	442382185	18933	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	56661	0	0
T53	16285	643	0	0
T54	41806	613	0	0
T55	31909	2688	0	0
T195	66642	1256	0	0
T217	4848	75	0	0
T218	4270	210	0	0
T220	69905	1212	0	0
T221	2485	129	0	0
T253	3377	61	0	0
T308	84719	2112	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	56661	0	0
T53	16285	643	0	0
T54	41806	613	0	0
T55	31909	2688	0	0
T195	66642	1256	0	0
T217	4848	75	0	0
T218	4270	210	0	0
T220	69905	1212	0	0
T221	2485	129	0	0
T253	3377	61	0	0
T308	84719	2112	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	37728	0	0
T53	16285	431	0	0
T54	41806	400	0	0
T55	31909	1344	0	0
T195	66642	833	0	0
T217	4848	45	0	0
T218	4270	131	0	0
T220	69905	786	0	0
T221	2485	87	0	0
T253	3377	40	0	0
T308	84719	2091	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	18933	0	0
T53	16285	212	0	0
T54	41806	213	0	0
T55	31909	1344	0	0
T195	66642	423	0	0
T217	4848	30	0	0
T218	4270	79	0	0
T220	69905	426	0	0
T221	2485	42	0	0
T253	3377	21	0	0
T308	84719	21	0	0