Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.49	97.47	91.51		100.00	93.48	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	94.29	96.20	83.96		100.00	91.30	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	96.49	97.47	91.51		100.00	93.48	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	96.20	83.96		100.00	91.30	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	97.65	92.31	98.97	100.00	96.91	97.98

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.26	97.67	85.11			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	97.77	100.00	95.24	95.00	100.00	96.36	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	92.22	100.00	88.89		100.00	80.00
u_host_arb	91.95	75.93	91.89			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.53	99.15	93.05	100.00		99.25	96.23
u_scramble	98.18	100.00	90.91	100.00		100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.49	97.47	91.51		100.00	93.48	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.74	97.77	93.45	100.00	100.00	97.25	97.98

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.26	97.67	85.11			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.60	100.00	95.24	100.00	100.00	96.36	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	92.22	100.00	88.89		100.00	80.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.62	99.15	93.49	100.00		99.25	96.23
u_scramble	98.18	100.00	90.91	100.00		100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		79	77	97.47
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	5	83.33
ALWAYS	232	6	5	83.33
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	328	29	29	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	605	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	0	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	0	1
			MISSING_ELSE
280	1	1
283	1	1
284	1	1
285	1	1
290	1	1
320	1	1
324	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
334	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
378	1	1
391	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
401	1	1
418	1	1
431	1	1
551	1	1
579	1	1
586	1	1
603	1	1
604	1	1
605	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T61,T176,T63

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T61,T176,T63

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T7
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T103
1	1	1	Covered	T1,T3,T5

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T7,T40
1	1	Covered	T1,T3,T5

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T177,T178,T179
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T47

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T22,T23
1	1	Covered	T2,T3,T4

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T103
1	0	Covered	T180,T181,T182

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T180,T181,T182

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T103

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T24

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T20,T21
1	0	Covered	T22,T23,T24

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Not Covered
1	1	Not Covered

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T16

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T16

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T16

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T16

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T14,T15
1	0	Covered	T11,T14,T15

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Covered	T2,T22,T23
StCtrlProg	342	Covered	T2,T3,T4
StCtrlRead	340	Covered	T1,T2,T3
StDisable	338	Covered	T11,T12,T13
StIdle	352	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Covered	T2,T22,T23
StCtrlProg->StIdle	362	Covered	T2,T3,T4
StCtrlRead->StIdle	352	Covered	T1,T2,T3
StIdle->StCtrl	344	Covered	T2,T22,T23
StIdle->StCtrlProg	342	Covered	T2,T3,T4
StIdle->StCtrlRead	340	Covered	T1,T2,T3
StIdle->StDisable	338	Covered	T11,T12,T13

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	43	93.48
TERNARY	320	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	398	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	434	2	1	50.00
TERNARY	557	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	3	75.00
IF	232	4	3	75.00
CASE	334	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T47
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T61,T176,T63
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T11,T12,T13
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	0	1	-	-	-	Covered	T2,T22,T23
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T2,T3,T4
StCtrlProg	-	-	-	-	-	0	-	Covered	T2,T3,T4
StCtrl	-	-	-	-	-	-	1	Covered	T2,T22,T24
StCtrl	-	-	-	-	-	-	0	Covered	T2,T22,T23
StDisable	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	Covered	T11,T14,T15

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	879405004	4373900	0	0
CtrlPrio_A	879405004	4373895	0	0
HostTransIdleChk_A	879405004	46130375	0	0
NoRemainder_A	2122	2122	0	0
OneHotReqs_A	879405004	877637750	0	0
Pow2Multiple_A	2122	2122	0	0
RdTxnCheck_A	878968916	877201662	0	0
u_state_regs_A	879405004	877637750	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879405004	4373900	0	0
T1	82032	3405	0	0
T2	144452	0	0	0
T3	3508	0	0	0
T4	399584	0	0	0
T5	75780	0	0	0
T6	5524	0	0	0
T7	130094	4782	0	0
T11	328274	0	0	0
T16	2412	0	0	0
T17	3534	0	0	0
T18	0	74675	0	0
T41	0	5001	0	0
T42	0	1878	0	0
T47	0	4	0	0
T48	0	84357	0	0
T58	0	68701	0	0
T73	0	5895	0	0
T120	0	82194	0	0
T126	0	38522	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879405004	4373895	0	0
T1	82032	3405	0	0
T2	144452	0	0	0
T3	3508	0	0	0
T4	399584	0	0	0
T5	75780	0	0	0
T6	5524	0	0	0
T7	130094	4782	0	0
T11	328274	0	0	0
T16	2412	0	0	0
T17	3534	0	0	0
T18	0	74675	0	0
T41	0	5001	0	0
T42	0	1878	0	0
T47	0	4	0	0
T48	0	84357	0	0
T58	0	68701	0	0
T73	0	5895	0	0
T120	0	82194	0	0
T126	0	38522	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879405004	46130375	0	0
T1	82032	33136	0	0
T2	144452	0	0	0
T3	3508	28	0	0
T4	399584	0	0	0
T5	75780	510	0	0
T6	5524	20	0	0
T7	130094	53766	0	0
T11	328274	103	0	0
T16	2412	0	0	0
T17	3534	0	0	0
T18	0	459408	0	0
T28	0	32	0	0
T36	0	24	0	0
T40	0	203	0	0
T46	0	14	0	0
T47	0	273	0	0
T48	0	845129	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2122	2122	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T11	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879405004	877637750	0	0
T1	82032	81864	0	0
T2	144452	144332	0	0
T3	3508	3254	0	0
T4	399584	399430	0	0
T5	75780	75636	0	0
T6	5524	5254	0	0
T7	130094	129912	0	0
T11	328274	276660	0	0
T16	2412	2306	0	0
T17	3534	3342	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2122	2122	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T11	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878968916	877201662	0	0
T1	82032	81864	0	0
T2	144452	144332	0	0
T3	3508	3254	0	0
T4	399584	399430	0	0
T5	75780	75636	0	0
T6	5524	5254	0	0
T7	130094	129912	0	0
T11	200616	149002	0	0
T16	2412	2306	0	0
T17	3534	3342	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879405004	877637750	0	0
T1	82032	81864	0	0
T2	144452	144332	0	0
T3	3508	3254	0	0
T4	399584	399430	0	0
T5	75780	75636	0	0
T6	5524	5254	0	0
T7	130094	129912	0	0
T11	328274	276660	0	0
T16	2412	2306	0	0
T17	3534	3342	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	76	96.20
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	3	75.00
ALWAYS	218	6	5	83.33
ALWAYS	232	6	5	83.33
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	328	29	29	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	605	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	0	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	0	1
			MISSING_ELSE
280	1	1
283	1	1
284	1	1
285	1	1
290	1	1
320	1	1
324	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
334	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
378	1	1
391	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
401	1	1
418	1	1
431	1	1
551	1	1
579	1	1
586	1	1
603	1	1
604	1	1
605	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	89	83.96
Logical	106	89	83.96
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Not Covered

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T7
1	0	1	Covered	T1,T3,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T7,T40
1	1	Covered	T1,T3,T5

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T47

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T17
1	1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T26,T27,T20
1	1	Covered	T2,T3,T17

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T17
1	1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T17

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T26,T27,T20

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T20,T21
1	0	Covered	T22,T23,T24

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Not Covered
1	1	Not Covered

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T17
1	1	Covered	T1,T2,T3

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T47,T36

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T28
1	0	Covered	T28,T47,T36

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T28
1	0	Covered	T28,T47,T36

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T47,T36

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T14,T15
1	0	Covered	T11,T14,T15

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Covered	T26,T27,T20
StCtrlProg	342	Covered	T2,T3,T17
StCtrlRead	340	Covered	T1,T2,T3
StDisable	338	Covered	T11,T12,T13
StIdle	352	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Covered	T26,T27,T20
StCtrlProg->StIdle	362	Covered	T2,T3,T17
StCtrlRead->StIdle	352	Covered	T1,T2,T3
StIdle->StCtrl	344	Covered	T26,T27,T20
StIdle->StCtrlProg	342	Covered	T2,T3,T17
StIdle->StCtrlRead	340	Covered	T1,T2,T3
StIdle->StDisable	338	Covered	T11,T12,T13

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	42	91.30
TERNARY	320	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	398	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	434	2	1	50.00
TERNARY	557	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	2	66.67
IF	218	4	3	75.00
IF	232	4	3	75.00
CASE	334	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T47,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T47,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T47
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T11,T12,T13
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T2,T3,T17
StIdle	0	0	0	1	-	-	-	Covered	T26,T27,T20
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T2,T3,T17
StCtrlProg	-	-	-	-	-	0	-	Covered	T2,T3,T17
StCtrl	-	-	-	-	-	-	1	Covered	T26,T27,T20
StCtrl	-	-	-	-	-	-	0	Covered	T26,T27,T20
StDisable	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	Covered	T11,T14,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	439702502	1997410	0	0
CtrlPrio_A	439702502	1997405	0	0
HostTransIdleChk_A	439702502	22682128	0	0
NoRemainder_A	1061	1061	0	0
OneHotReqs_A	439702502	438818875	0	0
Pow2Multiple_A	1061	1061	0	0
RdTxnCheck_A	439484458	438600831	0	0
u_state_regs_A	439702502	438818875	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	1997410	0	0
T1	41016	1585	0	0
T2	72226	0	0	0
T3	1754	0	0	0
T4	199792	0	0	0
T5	37890	0	0	0
T6	2762	0	0	0
T7	65047	2577	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	0	0	0
T18	0	36359	0	0
T41	0	3096	0	0
T42	0	1075	0	0
T47	0	4	0	0
T48	0	53560	0	0
T58	0	37492	0	0
T73	0	3114	0	0
T120	0	11124	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	1997405	0	0
T1	41016	1585	0	0
T2	72226	0	0	0
T3	1754	0	0	0
T4	199792	0	0	0
T5	37890	0	0	0
T6	2762	0	0	0
T7	65047	2577	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	0	0	0
T18	0	36359	0	0
T41	0	3096	0	0
T42	0	1075	0	0
T47	0	4	0	0
T48	0	53560	0	0
T58	0	37492	0	0
T73	0	3114	0	0
T120	0	11124	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	22682128	0	0
T1	41016	16040	0	0
T2	72226	0	0	0
T3	1754	28	0	0
T4	199792	0	0	0
T5	37890	277	0	0
T6	2762	0	0	0
T7	65047	27012	0	0
T11	164137	55	0	0
T16	1206	0	0	0
T17	1767	0	0	0
T28	0	32	0	0
T36	0	24	0	0
T40	0	165	0	0
T47	0	186	0	0
T48	0	428867	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439484458	438600831	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	100308	74501	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	77	97.47
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	5	83.33
ALWAYS	232	6	5	83.33
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	328	29	29	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	605	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	0	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	0	1
			MISSING_ELSE
280	1	1
283	1	1
284	1	1
285	1	1
290	1	1
320	1	1
324	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
334	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
378	1	1
391	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
401	1	1
418	1	1
431	1	1
551	1	1
579	1	1
586	1	1
603	1	1
604	1	1
605	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T61,T176,T63

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T61,T176,T63

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T6

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T7
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T103
1	1	1	Covered	T1,T5,T6

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T7,T40
1	1	Covered	T1,T5,T6

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T177,T178,T179
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T48

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T2,T22,T23
1	1	Covered	T2,T4,T6

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T103
1	0	Covered	T180,T181,T182

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T180,T181,T182

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T103

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T24

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T20,T21
1	0	Covered	T22,T23,T24

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T16

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T16

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T16

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T16

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T14,T15
1	0	Covered	T11,T14,T15

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Covered	T2,T22,T23
StCtrlProg	342	Covered	T2,T4,T6
StCtrlRead	340	Covered	T1,T2,T3
StDisable	338	Covered	T11,T13,T26
StIdle	352	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Covered	T2,T22,T23
StCtrlProg->StIdle	362	Covered	T2,T4,T6
StCtrlRead->StIdle	352	Covered	T1,T2,T3
StIdle->StCtrl	344	Covered	T2,T22,T23
StIdle->StCtrlProg	342	Covered	T2,T4,T6
StIdle->StCtrlRead	340	Covered	T1,T2,T3
StIdle->StDisable	338	Covered	T11,T13,T26

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	43	93.48
TERNARY	320	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	398	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	434	2	1	50.00
TERNARY	557	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	3	75.00
IF	232	4	3	75.00
CASE	334	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T48
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T61,T176,T63
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T11,T12,T13
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T2,T4,T6
StIdle	0	0	0	1	-	-	-	Covered	T2,T22,T23
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T2,T4,T6
StCtrlProg	-	-	-	-	-	0	-	Covered	T2,T4,T6
StCtrl	-	-	-	-	-	-	1	Covered	T2,T22,T24
StCtrl	-	-	-	-	-	-	0	Covered	T2,T22,T23
StDisable	-	-	-	-	-	-	-	Covered	T11,T13,T26
default	-	-	-	-	-	-	-	Covered	T11,T14,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	439702502	2376490	0	0
CtrlPrio_A	439702502	2376490	0	0
HostTransIdleChk_A	439702502	23448247	0	0
NoRemainder_A	1061	1061	0	0
OneHotReqs_A	439702502	438818875	0	0
Pow2Multiple_A	1061	1061	0	0
RdTxnCheck_A	439484458	438600831	0	0
u_state_regs_A	439702502	438818875	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	2376490	0	0
T1	41016	1820	0	0
T2	72226	0	0	0
T3	1754	0	0	0
T4	199792	0	0	0
T5	37890	0	0	0
T6	2762	0	0	0
T7	65047	2205	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	0	0	0
T18	0	38316	0	0
T41	0	1905	0	0
T42	0	803	0	0
T48	0	30797	0	0
T58	0	31209	0	0
T73	0	2781	0	0
T120	0	71070	0	0
T126	0	38522	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	2376490	0	0
T1	41016	1820	0	0
T2	72226	0	0	0
T3	1754	0	0	0
T4	199792	0	0	0
T5	37890	0	0	0
T6	2762	0	0	0
T7	65047	2205	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	0	0	0
T18	0	38316	0	0
T41	0	1905	0	0
T42	0	803	0	0
T48	0	30797	0	0
T58	0	31209	0	0
T73	0	2781	0	0
T120	0	71070	0	0
T126	0	38522	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	23448247	0	0
T1	41016	17096	0	0
T2	72226	0	0	0
T3	1754	0	0	0
T4	199792	0	0	0
T5	37890	233	0	0
T6	2762	20	0	0
T7	65047	26754	0	0
T11	164137	48	0	0
T16	1206	0	0	0
T17	1767	0	0	0
T18	0	459408	0	0
T40	0	38	0	0
T46	0	14	0	0
T47	0	87	0	0
T48	0	416262	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439484458	438600831	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	100308	74501	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0