Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T40
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1758810008	1755275500	0	0
CheckNGreaterZero_A	4244	4244	0	0
GntImpliesReady_A	1758810008	446787238	0	0
GntImpliesValid_A	1758810008	446787238	0	0
GrantKnown_A	1758810008	1755275500	0	0
IdxKnown_A	1758810008	1755275500	0	0
IndexIsCorrect_A	1758810008	446787238	0	0
NoReadyValidNoGrant_A	1758810008	181072682	0	0
Priority_A	1758810008	471088214	0	0
ReadyAndValidImplyGrant_A	1758810008	446787238	0	0
ReqAndReadyImplyGrant_A	1758810008	446787238	0	0
ReqImpliesValid_A	1758810008	471088214	0	0
ValidKnown_A	1758810008	1755275500	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	1755275500	0	0
T1	164064	163728	0	0
T2	288904	288664	0	0
T3	7016	6508	0	0
T4	799168	798860	0	0
T5	151560	151272	0	0
T6	11048	10508	0	0
T7	260188	259824	0	0
T11	656548	553320	0	0
T16	4824	4612	0	0
T17	7068	6684	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4244	4244	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	446787238	0	0
T1	164064	42378	0	0
T2	288904	137426	0	0
T3	7016	430	0	0
T4	799168	85550	0	0
T5	151560	1878	0	0
T6	11048	1266	0	0
T7	260188	42716	0	0
T11	656548	0	0	0
T16	4824	844	0	0
T17	7068	442	0	0
T22	0	288034	0	0
T24	0	4	0	0
T28	0	458	0	0
T31	0	18	0	0
T45	0	29170	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	446787238	0	0
T1	164064	42378	0	0
T2	288904	137426	0	0
T3	7016	430	0	0
T4	799168	85550	0	0
T5	151560	1878	0	0
T6	11048	1266	0	0
T7	260188	42716	0	0
T11	656548	0	0	0
T16	4824	844	0	0
T17	7068	442	0	0
T22	0	288034	0	0
T24	0	4	0	0
T28	0	458	0	0
T31	0	18	0	0
T45	0	29170	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	1755275500	0	0
T1	164064	163728	0	0
T2	288904	288664	0	0
T3	7016	6508	0	0
T4	799168	798860	0	0
T5	151560	151272	0	0
T6	11048	10508	0	0
T7	260188	259824	0	0
T11	656548	553320	0	0
T16	4824	4612	0	0
T17	7068	6684	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	1755275500	0	0
T1	164064	163728	0	0
T2	288904	288664	0	0
T3	7016	6508	0	0
T4	799168	798860	0	0
T5	151560	151272	0	0
T6	11048	10508	0	0
T7	260188	259824	0	0
T11	656548	553320	0	0
T16	4824	4612	0	0
T17	7068	6684	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	446787238	0	0
T1	164064	42378	0	0
T2	288904	137426	0	0
T3	7016	430	0	0
T4	799168	85550	0	0
T5	151560	1878	0	0
T6	11048	1266	0	0
T7	260188	42716	0	0
T11	656548	0	0	0
T16	4824	844	0	0
T17	7068	442	0	0
T22	0	288034	0	0
T24	0	4	0	0
T28	0	458	0	0
T31	0	18	0	0
T45	0	29170	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	181072682	0	0
T1	164064	52938	0	0
T2	288904	506	0	0
T3	7016	970	0	0
T4	799168	5760	0	0
T5	151560	3010	0	0
T6	11048	1048	0	0
T7	260188	117422	0	0
T11	656548	12564	0	0
T16	4824	256	0	0
T17	7068	318	0	0
T24	0	8	0	0
T28	0	312	0	0
T31	0	28	0	0
T40	0	290	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	471088214	0	0
T1	164064	54380	0	0
T2	288904	137426	0	0
T3	7016	430	0	0
T4	799168	85550	0	0
T5	151560	1878	0	0
T6	11048	1266	0	0
T7	260188	44732	0	0
T11	656548	0	0	0
T16	4824	844	0	0
T17	7068	442	0	0
T22	0	288034	0	0
T24	0	4	0	0
T28	0	458	0	0
T31	0	18	0	0
T45	0	29170	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	446787238	0	0
T1	164064	42378	0	0
T2	288904	137426	0	0
T3	7016	430	0	0
T4	799168	85550	0	0
T5	151560	1878	0	0
T6	11048	1266	0	0
T7	260188	42716	0	0
T11	656548	0	0	0
T16	4824	844	0	0
T17	7068	442	0	0
T22	0	288034	0	0
T24	0	4	0	0
T28	0	458	0	0
T31	0	18	0	0
T45	0	29170	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	446787238	0	0
T1	164064	42378	0	0
T2	288904	137426	0	0
T3	7016	430	0	0
T4	799168	85550	0	0
T5	151560	1878	0	0
T6	11048	1266	0	0
T7	260188	42716	0	0
T11	656548	0	0	0
T16	4824	844	0	0
T17	7068	442	0	0
T22	0	288034	0	0
T24	0	4	0	0
T28	0	458	0	0
T31	0	18	0	0
T45	0	29170	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	471088214	0	0
T1	164064	54380	0	0
T2	288904	137426	0	0
T3	7016	430	0	0
T4	799168	85550	0	0
T5	151560	1878	0	0
T6	11048	1266	0	0
T7	260188	44732	0	0
T11	656548	0	0	0
T16	4824	844	0	0
T17	7068	442	0	0
T22	0	288034	0	0
T24	0	4	0	0
T28	0	458	0	0
T31	0	18	0	0
T45	0	29170	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1758810008	1755275500	0	0
T1	164064	163728	0	0
T2	288904	288664	0	0
T3	7016	6508	0	0
T4	799168	798860	0	0
T5	151560	151272	0	0
T6	11048	10508	0	0
T7	260188	259824	0	0
T11	656548	553320	0	0
T16	4824	4612	0	0
T17	7068	6684	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T40
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439702502	438818875	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	439702502	121762903	0	0
GntImpliesValid_A	439702502	121762903	0	0
GrantKnown_A	439702502	438818875	0	0
IdxKnown_A	439702502	438818875	0	0
IndexIsCorrect_A	439702502	121762903	0	0
NoReadyValidNoGrant_A	439702502	47224648	0	0
Priority_A	439702502	128118363	0	0
ReadyAndValidImplyGrant_A	439702502	121762903	0	0
ReqAndReadyImplyGrant_A	439702502	121762903	0	0
ReqImpliesValid_A	439702502	128118363	0	0
ValidKnown_A	439702502	438818875	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	121762903	0	0
T1	41016	10270	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	10565	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	121762903	0	0
T1	41016	10270	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	10565	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	121762903	0	0
T1	41016	10270	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	10565	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	47224648	0	0
T1	41016	12465	0	0
T2	72226	155	0	0
T3	1754	256	0	0
T4	199792	2880	0	0
T5	37890	745	0	0
T6	2762	524	0	0
T7	65047	29145	0	0
T11	164137	2395	0	0
T16	1206	128	0	0
T17	1767	159	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	128118363	0	0
T1	41016	13481	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	11059	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	121762903	0	0
T1	41016	10270	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	10565	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	121762903	0	0
T1	41016	10270	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	10565	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	128118363	0	0
T1	41016	13481	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	11059	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T40
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439702502	438818875	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	439702502	121516329	0	0
GntImpliesValid_A	439702502	121516329	0	0
GrantKnown_A	439702502	438818875	0	0
IdxKnown_A	439702502	438818875	0	0
IndexIsCorrect_A	439702502	121516329	0	0
NoReadyValidNoGrant_A	439702502	47224648	0	0
Priority_A	439702502	127871789	0	0
ReadyAndValidImplyGrant_A	439702502	121516329	0	0
ReqAndReadyImplyGrant_A	439702502	121516329	0	0
ReqImpliesValid_A	439702502	127871789	0	0
ValidKnown_A	439702502	438818875	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	121516329	0	0
T1	41016	10270	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	10565	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	121516329	0	0
T1	41016	10270	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	10565	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	121516329	0	0
T1	41016	10270	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	10565	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	47224648	0	0
T1	41016	12465	0	0
T2	72226	155	0	0
T3	1754	256	0	0
T4	199792	2880	0	0
T5	37890	745	0	0
T6	2762	524	0	0
T7	65047	29145	0	0
T11	164137	2395	0	0
T16	1206	128	0	0
T17	1767	159	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	127871789	0	0
T1	41016	13481	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	11059	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	121516329	0	0
T1	41016	10270	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	10565	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	121516329	0	0
T1	41016	10270	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	10565	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	127871789	0	0
T1	41016	13481	0	0
T2	72226	66302	0	0
T3	1754	64	0	0
T4	199792	42775	0	0
T5	37890	442	0	0
T6	2762	633	0	0
T7	65047	11059	0	0
T11	164137	0	0	0
T16	1206	422	0	0
T17	1767	52	0	0
T22	0	144017	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T40
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439702502	438818875	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	439702502	101754003	0	0
GntImpliesValid_A	439702502	101754003	0	0
GrantKnown_A	439702502	438818875	0	0
IdxKnown_A	439702502	438818875	0	0
IndexIsCorrect_A	439702502	101754003	0	0
NoReadyValidNoGrant_A	439702502	43311693	0	0
Priority_A	439702502	107549031	0	0
ReadyAndValidImplyGrant_A	439702502	101754003	0	0
ReqAndReadyImplyGrant_A	439702502	101754003	0	0
ReqImpliesValid_A	439702502	107549031	0	0
ValidKnown_A	439702502	438818875	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	101754003	0	0
T1	41016	10919	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	10793	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	101754003	0	0
T1	41016	10919	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	10793	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	101754003	0	0
T1	41016	10919	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	10793	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	43311693	0	0
T1	41016	14004	0	0
T2	72226	98	0	0
T3	1754	229	0	0
T4	199792	0	0	0
T5	37890	760	0	0
T6	2762	0	0	0
T7	65047	29566	0	0
T11	164137	3887	0	0
T16	1206	0	0	0
T17	1767	0	0	0
T24	0	4	0	0
T28	0	156	0	0
T31	0	14	0	0
T40	0	145	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	107549031	0	0
T1	41016	13709	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	11307	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	101754003	0	0
T1	41016	10919	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	10793	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	101754003	0	0
T1	41016	10919	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	10793	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	107549031	0	0
T1	41016	13709	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	11307	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T40
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439702502	438818875	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	439702502	101754003	0	0
GntImpliesValid_A	439702502	101754003	0	0
GrantKnown_A	439702502	438818875	0	0
IdxKnown_A	439702502	438818875	0	0
IndexIsCorrect_A	439702502	101754003	0	0
NoReadyValidNoGrant_A	439702502	43311693	0	0
Priority_A	439702502	107549031	0	0
ReadyAndValidImplyGrant_A	439702502	101754003	0	0
ReqAndReadyImplyGrant_A	439702502	101754003	0	0
ReqImpliesValid_A	439702502	107549031	0	0
ValidKnown_A	439702502	438818875	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	101754003	0	0
T1	41016	10919	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	10793	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	101754003	0	0
T1	41016	10919	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	10793	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	101754003	0	0
T1	41016	10919	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	10793	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	43311693	0	0
T1	41016	14004	0	0
T2	72226	98	0	0
T3	1754	229	0	0
T4	199792	0	0	0
T5	37890	760	0	0
T6	2762	0	0	0
T7	65047	29566	0	0
T11	164137	3887	0	0
T16	1206	0	0	0
T17	1767	0	0	0
T24	0	4	0	0
T28	0	156	0	0
T31	0	14	0	0
T40	0	145	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	107549031	0	0
T1	41016	13709	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	11307	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	101754003	0	0
T1	41016	10919	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	10793	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	101754003	0	0
T1	41016	10919	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	10793	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	107549031	0	0
T1	41016	13709	0	0
T2	72226	2411	0	0
T3	1754	151	0	0
T4	199792	0	0	0
T5	37890	497	0	0
T6	2762	0	0	0
T7	65047	11307	0	0
T11	164137	0	0	0
T16	1206	0	0	0
T17	1767	169	0	0
T24	0	2	0	0
T28	0	229	0	0
T31	0	9	0	0
T45	0	14585	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439702502	438818875	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0