Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442382185	36354583	0	0
DepthKnown_A	442382185	441418588	0	0
RvalidKnown_A	442382185	441418588	0	0
WreadyKnown_A	442382185	441418588	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	36354583	0	0
T1	41016	24465	0	0
T2	72226	10530	0	0
T3	1754	534	0	0
T4	199792	32334	0	0
T5	37890	3582	0	0
T6	2762	833	0	0
T7	65047	39026	0	0
T11	164137	10168	0	0
T16	1206	344	0	0
T17	1767	244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442382185	38778406	0	0
DepthKnown_A	442382185	441418588	0	0
RvalidKnown_A	442382185	441418588	0	0
WreadyKnown_A	442382185	441418588	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	38778406	0	0
T1	41016	15481	0	0
T2	72226	10109	0	0
T3	1754	534	0	0
T4	199792	26444	0	0
T5	37890	11109	0	0
T6	2762	833	0	0
T7	65047	26866	0	0
T11	164137	45233	0	0
T16	1206	344	0	0
T17	1767	230	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442382185	6076260	0	0
DepthKnown_A	442382185	441418588	0	0
RvalidKnown_A	442382185	441418588	0	0
WreadyKnown_A	442382185	441418588	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	6076260	0	0
T2	72226	518	0	0
T3	1754	1	0	0
T4	199792	10498	0	0
T5	37890	0	0	0
T6	2762	14	0	0
T7	65047	0	0	0
T11	164137	2139	0	0
T16	1206	14	0	0
T17	1767	5	0	0
T22	337631	2408	0	0
T28	0	4	0	0
T29	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	442382185	3050646	0	0
DepthKnown_A	442382185	441418588	0	0
RvalidKnown_A	442382185	441418588	0	0
WreadyKnown_A	442382185	441418588	0	0
gen_passthru_fifo.paramCheckPass	1276	1276	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	3050646	0	0
T2	72226	103	0	0
T3	1754	1	0	0
T4	199792	4608	0	0
T5	37890	0	0	0
T6	2762	14	0	0
T7	65047	0	0	0
T11	164137	9607	0	0
T16	1206	14	0	0
T17	1767	5	0	0
T22	337631	2408	0	0
T28	0	4	0	0
T29	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442382185	441418588	0	0
T1	41016	40932	0	0
T2	72226	72166	0	0
T3	1754	1627	0	0
T4	199792	199715	0	0
T5	37890	37818	0	0
T6	2762	2627	0	0
T7	65047	64956	0	0
T11	164137	138330	0	0
T16	1206	1153	0	0
T17	1767	1671	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276	1276	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0