Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21897994	1		T1	66697		T2	103561		T3	113100
full_word	7463584	1		T1	673		T2	24448		T3	19365

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29361278	1		T1	67370		T2	128009		T3	132465
auto[TlIntgErrCmd]	110	1		T215	1		T216	3		T217	10
auto[TlIntgErrData]	98	1		T215	6		T216	2		T217	5
auto[TlIntgErrBoth]	92	1		T215	3		T216	5		T217	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	24994915	1		T1	66692		T2	112027		T3	120269
auto[1]	4366663	1		T1	678		T2	15982		T3	12196

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21214938	1		T1	66662		T2	102336		T3	111367
auto[TlIntgErrNone]	partial	auto[1]	682781	1		T1	35		T2	1225		T3	1733
auto[TlIntgErrNone]	full_word	auto[0]	3779851	1		T1	30		T2	9691		T3	8902
auto[TlIntgErrNone]	full_word	auto[1]	3683708	1		T1	643		T2	14757		T3	10463
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T216	1		T217	5		T295	4
auto[TlIntgErrCmd]	partial	auto[1]	59	1		T215	1		T216	2		T217	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T339	1		T336	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T217	1		T340	1		T336	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T215	3		T216	1		T217	1
auto[TlIntgErrData]	partial	auto[1]	47	1		T215	3		T216	1		T217	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T295	1		T334	1		T264	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T336	1		T341	1		T264	1
auto[TlIntgErrBoth]	partial	auto[0]	26	1		T216	1		T333	2		T295	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T215	3		T216	4		T217	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T217	1		T299	3		T263	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T339	1		T299	1		T337	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24427	1		T193	1030		T194	546		T195	1256
full_word	4342113	1		T1	166		T3	41612		T15	88

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4366252	1		T1	166		T3	41612		T15	88
auto[TlIntgErrCmd]	96	1		T215	3		T216	3		T217	7
auto[TlIntgErrData]	109	1		T215	3		T216	2		T217	7
auto[TlIntgErrBoth]	83	1		T215	3		T216	4		T217	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4334861	1		T1	166		T3	41612		T15	88
auto[1]	31679	1		T193	1533		T194	796		T195	1845

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1617	1		T193	65		T194	28		T195	65
auto[TlIntgErrNone]	partial	auto[1]	22547	1		T193	965		T194	518		T195	1191
auto[TlIntgErrNone]	full_word	auto[0]	4333128	1		T1	166		T3	41612		T15	88
auto[TlIntgErrNone]	full_word	auto[1]	8960	1		T193	568		T194	278		T195	654
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T215	1		T217	3		T295	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T216	3		T217	4		T333	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T215	1		T342	1		T335	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T215	1		T336	2		T264	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T215	2		T216	1		T217	2
auto[TlIntgErrData]	partial	auto[1]	59	1		T215	1		T216	1		T217	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T217	1		T339	1		T263	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T217	1		T334	1		T342	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T215	1		T216	2		T217	3
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T215	2		T216	2		T217	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T217	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T299	1		T337	1		-	-