Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1523946168	1520310408	0	0
CheckNGreaterZero_A	4240	4240	0	0
GntImpliesReady_A	1523946168	442231528	0	0
GntImpliesValid_A	1523946168	442231528	0	0
GrantKnown_A	1523946168	1520310408	0	0
IdxKnown_A	1523946168	1520310408	0	0
IndexIsCorrect_A	1523946168	442231528	0	0
NoReadyValidNoGrant_A	1523946168	178697184	0	0
Priority_A	1523946168	466702410	0	0
ReadyAndValidImplyGrant_A	1523946168	442231528	0	0
ReqAndReadyImplyGrant_A	1523946168	442231528	0	0
ReqImpliesValid_A	1523946168	466702410	0	0
ValidKnown_A	1523946168	1520310408	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	1520310408	0	0
T1	548576	548224	0	0
T2	3594732	3594400	0	0
T3	1098448	1098216	0	0
T4	136988	136612	0	0
T5	4484	4176	0	0
T6	459336	458664	0	0
T10	243036	242524	0	0
T15	20272	19892	0	0
T16	824368	824032	0	0
T17	210960	210652	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4240	4240	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	442231528	0	0
T1	548576	267022	0	0
T2	3594732	1240658	0	0
T3	1098448	300872	0	0
T4	136988	39152	0	0
T5	4484	70	0	0
T6	459336	64038	0	0
T10	243036	666	0	0
T15	20272	5364	0	0
T16	824368	376858	0	0
T17	210960	40876	0	0
T19	0	22418	0	0
T22	0	34626	0	0
T23	0	26726	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	442231528	0	0
T1	548576	267022	0	0
T2	3594732	1240658	0	0
T3	1098448	300872	0	0
T4	136988	39152	0	0
T5	4484	70	0	0
T6	459336	64038	0	0
T10	243036	666	0	0
T15	20272	5364	0	0
T16	824368	376858	0	0
T17	210960	40876	0	0
T19	0	22418	0	0
T22	0	34626	0	0
T23	0	26726	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	1520310408	0	0
T1	548576	548224	0	0
T2	3594732	3594400	0	0
T3	1098448	1098216	0	0
T4	136988	136612	0	0
T5	4484	4176	0	0
T6	459336	458664	0	0
T10	243036	242524	0	0
T15	20272	19892	0	0
T16	824368	824032	0	0
T17	210960	210652	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	1520310408	0	0
T1	548576	548224	0	0
T2	3594732	3594400	0	0
T3	1098448	1098216	0	0
T4	136988	136612	0	0
T5	4484	4176	0	0
T6	459336	458664	0	0
T10	243036	242524	0	0
T15	20272	19892	0	0
T16	824368	824032	0	0
T17	210960	210652	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	442231528	0	0
T1	548576	267022	0	0
T2	3594732	1240658	0	0
T3	1098448	300872	0	0
T4	136988	39152	0	0
T5	4484	70	0	0
T6	459336	64038	0	0
T10	243036	666	0	0
T15	20272	5364	0	0
T16	824368	376858	0	0
T17	210960	40876	0	0
T19	0	22418	0	0
T22	0	34626	0	0
T23	0	26726	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	178697184	0	0
T1	548576	1828	0	0
T2	3594732	7168	0	0
T3	1098448	215816	0	0
T4	136988	51312	0	0
T5	4484	274	0	0
T6	459336	163458	0	0
T10	243036	256	0	0
T15	20272	828	0	0
T16	824368	256	0	0
T17	210960	64436	0	0
T19	0	28670	0	0
T22	0	1107956	0	0
T23	0	856242	0	0
T52	0	552	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	466702410	0	0
T1	548576	267302	0	0
T2	3594732	1240658	0	0
T3	1098448	396184	0	0
T4	136988	49910	0	0
T5	4484	70	0	0
T6	459336	68442	0	0
T10	243036	666	0	0
T15	20272	5364	0	0
T16	824368	376858	0	0
T17	210960	50408	0	0
T19	0	28446	0	0
T22	0	274318	0	0
T23	0	342610	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	442231528	0	0
T1	548576	267022	0	0
T2	3594732	1240658	0	0
T3	1098448	300872	0	0
T4	136988	39152	0	0
T5	4484	70	0	0
T6	459336	64038	0	0
T10	243036	666	0	0
T15	20272	5364	0	0
T16	824368	376858	0	0
T17	210960	40876	0	0
T19	0	22418	0	0
T22	0	34626	0	0
T23	0	26726	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	442231528	0	0
T1	548576	267022	0	0
T2	3594732	1240658	0	0
T3	1098448	300872	0	0
T4	136988	39152	0	0
T5	4484	70	0	0
T6	459336	64038	0	0
T10	243036	666	0	0
T15	20272	5364	0	0
T16	824368	376858	0	0
T17	210960	40876	0	0
T19	0	22418	0	0
T22	0	34626	0	0
T23	0	26726	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	466702410	0	0
T1	548576	267302	0	0
T2	3594732	1240658	0	0
T3	1098448	396184	0	0
T4	136988	49910	0	0
T5	4484	70	0	0
T6	459336	68442	0	0
T10	243036	666	0	0
T15	20272	5364	0	0
T16	824368	376858	0	0
T17	210960	50408	0	0
T19	0	28446	0	0
T22	0	274318	0	0
T23	0	342610	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523946168	1520310408	0	0
T1	548576	548224	0	0
T2	3594732	3594400	0	0
T3	1098448	1098216	0	0
T4	136988	136612	0	0
T5	4484	4176	0	0
T6	459336	458664	0	0
T10	243036	242524	0	0
T15	20272	19892	0	0
T16	824368	824032	0	0
T17	210960	210652	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380986542	380077602	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	380986542	119592573	0	0
GntImpliesValid_A	380986542	119592573	0	0
GrantKnown_A	380986542	380077602	0	0
IdxKnown_A	380986542	380077602	0	0
IndexIsCorrect_A	380986542	119592573	0	0
NoReadyValidNoGrant_A	380986542	46245943	0	0
Priority_A	380986542	125751195	0	0
ReadyAndValidImplyGrant_A	380986542	119592573	0	0
ReqAndReadyImplyGrant_A	380986542	119592573	0	0
ReqImpliesValid_A	380986542	125751195	0	0
ValidKnown_A	380986542	380077602	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	119592573	0	0
T1	137144	65968	0	0
T2	898683	29331	0	0
T3	274612	89569	0	0
T4	34247	10102	0	0
T5	1121	35	0	0
T6	114834	18930	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	10153	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	119592573	0	0
T1	137144	65968	0	0
T2	898683	29331	0	0
T3	274612	89569	0	0
T4	34247	10102	0	0
T5	1121	35	0	0
T6	114834	18930	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	10153	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	119592573	0	0
T1	137144	65968	0	0
T2	898683	29331	0	0
T3	274612	89569	0	0
T4	34247	10102	0	0
T5	1121	35	0	0
T6	114834	18930	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	10153	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	46245943	0	0
T1	137144	603	0	0
T2	898683	1076	0	0
T3	274612	53777	0	0
T4	34247	13060	0	0
T5	1121	137	0	0
T6	114834	47098	0	0
T10	60759	128	0	0
T15	5068	414	0	0
T16	206092	128	0	0
T17	52740	14391	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	125751195	0	0
T1	137144	66063	0	0
T2	898683	29331	0	0
T3	274612	116268	0	0
T4	34247	13042	0	0
T5	1121	35	0	0
T6	114834	20226	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	12690	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	119592573	0	0
T1	137144	65968	0	0
T2	898683	29331	0	0
T3	274612	89569	0	0
T4	34247	10102	0	0
T5	1121	35	0	0
T6	114834	18930	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	10153	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	119592573	0	0
T1	137144	65968	0	0
T2	898683	29331	0	0
T3	274612	89569	0	0
T4	34247	10102	0	0
T5	1121	35	0	0
T6	114834	18930	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	10153	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	125751195	0	0
T1	137144	66063	0	0
T2	898683	29331	0	0
T3	274612	116268	0	0
T4	34247	13042	0	0
T5	1121	35	0	0
T6	114834	20226	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	12690	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380986542	380077602	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	380986542	119340069	0	0
GntImpliesValid_A	380986542	119340069	0	0
GrantKnown_A	380986542	380077602	0	0
IdxKnown_A	380986542	380077602	0	0
IndexIsCorrect_A	380986542	119340069	0	0
NoReadyValidNoGrant_A	380986542	46245945	0	0
Priority_A	380986542	125498689	0	0
ReadyAndValidImplyGrant_A	380986542	119340069	0	0
ReqAndReadyImplyGrant_A	380986542	119340069	0	0
ReqImpliesValid_A	380986542	125498689	0	0
ValidKnown_A	380986542	380077602	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	119340069	0	0
T1	137144	65968	0	0
T2	898683	29331	0	0
T3	274612	89569	0	0
T4	34247	10102	0	0
T5	1121	35	0	0
T6	114834	18930	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	10153	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	119340069	0	0
T1	137144	65968	0	0
T2	898683	29331	0	0
T3	274612	89569	0	0
T4	34247	10102	0	0
T5	1121	35	0	0
T6	114834	18930	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	10153	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	119340069	0	0
T1	137144	65968	0	0
T2	898683	29331	0	0
T3	274612	89569	0	0
T4	34247	10102	0	0
T5	1121	35	0	0
T6	114834	18930	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	10153	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	46245945	0	0
T1	137144	603	0	0
T2	898683	1076	0	0
T3	274612	53777	0	0
T4	34247	13060	0	0
T5	1121	137	0	0
T6	114834	47098	0	0
T10	60759	128	0	0
T15	5068	414	0	0
T16	206092	128	0	0
T17	52740	14391	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	125498689	0	0
T1	137144	66063	0	0
T2	898683	29331	0	0
T3	274612	116268	0	0
T4	34247	13042	0	0
T5	1121	35	0	0
T6	114834	20226	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	12690	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	119340069	0	0
T1	137144	65968	0	0
T2	898683	29331	0	0
T3	274612	89569	0	0
T4	34247	10102	0	0
T5	1121	35	0	0
T6	114834	18930	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	10153	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	119340069	0	0
T1	137144	65968	0	0
T2	898683	29331	0	0
T3	274612	89569	0	0
T4	34247	10102	0	0
T5	1121	35	0	0
T6	114834	18930	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	10153	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	125498689	0	0
T1	137144	66063	0	0
T2	898683	29331	0	0
T3	274612	116268	0	0
T4	34247	13042	0	0
T5	1121	35	0	0
T6	114834	20226	0	0
T10	60759	333	0	0
T15	5068	2682	0	0
T16	206092	114448	0	0
T17	52740	12690	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380986542	380077602	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	380986542	101649443	0	0
GntImpliesValid_A	380986542	101649443	0	0
GrantKnown_A	380986542	380077602	0	0
IdxKnown_A	380986542	380077602	0	0
IndexIsCorrect_A	380986542	101649443	0	0
NoReadyValidNoGrant_A	380986542	43102648	0	0
Priority_A	380986542	107726263	0	0
ReadyAndValidImplyGrant_A	380986542	101649443	0	0
ReqAndReadyImplyGrant_A	380986542	101649443	0	0
ReqImpliesValid_A	380986542	107726263	0	0
ValidKnown_A	380986542	380077602	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	101649443	0	0
T1	137144	67543	0	0
T2	898683	590998	0	0
T3	274612	60867	0	0
T4	34247	9474	0	0
T5	1121	0	0	0
T6	114834	13089	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	10285	0	0
T19	0	11209	0	0
T22	0	17313	0	0
T23	0	13363	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	101649443	0	0
T1	137144	67543	0	0
T2	898683	590998	0	0
T3	274612	60867	0	0
T4	34247	9474	0	0
T5	1121	0	0	0
T6	114834	13089	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	10285	0	0
T19	0	11209	0	0
T22	0	17313	0	0
T23	0	13363	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	101649443	0	0
T1	137144	67543	0	0
T2	898683	590998	0	0
T3	274612	60867	0	0
T4	34247	9474	0	0
T5	1121	0	0	0
T6	114834	13089	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	10285	0	0
T19	0	11209	0	0
T22	0	17313	0	0
T23	0	13363	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	43102648	0	0
T1	137144	311	0	0
T2	898683	2508	0	0
T3	274612	54131	0	0
T4	34247	12596	0	0
T5	1121	0	0	0
T6	114834	34631	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	0	0	0
T17	52740	17827	0	0
T19	0	14335	0	0
T22	0	553978	0	0
T23	0	428121	0	0
T52	0	276	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	107726263	0	0
T1	137144	67588	0	0
T2	898683	590998	0	0
T3	274612	81824	0	0
T4	34247	11913	0	0
T5	1121	0	0	0
T6	114834	13995	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	12514	0	0
T19	0	14223	0	0
T22	0	137159	0	0
T23	0	171305	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	101649443	0	0
T1	137144	67543	0	0
T2	898683	590998	0	0
T3	274612	60867	0	0
T4	34247	9474	0	0
T5	1121	0	0	0
T6	114834	13089	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	10285	0	0
T19	0	11209	0	0
T22	0	17313	0	0
T23	0	13363	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	101649443	0	0
T1	137144	67543	0	0
T2	898683	590998	0	0
T3	274612	60867	0	0
T4	34247	9474	0	0
T5	1121	0	0	0
T6	114834	13089	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	10285	0	0
T19	0	11209	0	0
T22	0	17313	0	0
T23	0	13363	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	107726263	0	0
T1	137144	67588	0	0
T2	898683	590998	0	0
T3	274612	81824	0	0
T4	34247	11913	0	0
T5	1121	0	0	0
T6	114834	13995	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	12514	0	0
T19	0	14223	0	0
T22	0	137159	0	0
T23	0	171305	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380986542	380077602	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	380986542	101649443	0	0
GntImpliesValid_A	380986542	101649443	0	0
GrantKnown_A	380986542	380077602	0	0
IdxKnown_A	380986542	380077602	0	0
IndexIsCorrect_A	380986542	101649443	0	0
NoReadyValidNoGrant_A	380986542	43102648	0	0
Priority_A	380986542	107726263	0	0
ReadyAndValidImplyGrant_A	380986542	101649443	0	0
ReqAndReadyImplyGrant_A	380986542	101649443	0	0
ReqImpliesValid_A	380986542	107726263	0	0
ValidKnown_A	380986542	380077602	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	101649443	0	0
T1	137144	67543	0	0
T2	898683	590998	0	0
T3	274612	60867	0	0
T4	34247	9474	0	0
T5	1121	0	0	0
T6	114834	13089	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	10285	0	0
T19	0	11209	0	0
T22	0	17313	0	0
T23	0	13363	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	101649443	0	0
T1	137144	67543	0	0
T2	898683	590998	0	0
T3	274612	60867	0	0
T4	34247	9474	0	0
T5	1121	0	0	0
T6	114834	13089	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	10285	0	0
T19	0	11209	0	0
T22	0	17313	0	0
T23	0	13363	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	101649443	0	0
T1	137144	67543	0	0
T2	898683	590998	0	0
T3	274612	60867	0	0
T4	34247	9474	0	0
T5	1121	0	0	0
T6	114834	13089	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	10285	0	0
T19	0	11209	0	0
T22	0	17313	0	0
T23	0	13363	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	43102648	0	0
T1	137144	311	0	0
T2	898683	2508	0	0
T3	274612	54131	0	0
T4	34247	12596	0	0
T5	1121	0	0	0
T6	114834	34631	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	0	0	0
T17	52740	17827	0	0
T19	0	14335	0	0
T22	0	553978	0	0
T23	0	428121	0	0
T52	0	276	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	107726263	0	0
T1	137144	67588	0	0
T2	898683	590998	0	0
T3	274612	81824	0	0
T4	34247	11913	0	0
T5	1121	0	0	0
T6	114834	13995	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	12514	0	0
T19	0	14223	0	0
T22	0	137159	0	0
T23	0	171305	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	101649443	0	0
T1	137144	67543	0	0
T2	898683	590998	0	0
T3	274612	60867	0	0
T4	34247	9474	0	0
T5	1121	0	0	0
T6	114834	13089	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	10285	0	0
T19	0	11209	0	0
T22	0	17313	0	0
T23	0	13363	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	101649443	0	0
T1	137144	67543	0	0
T2	898683	590998	0	0
T3	274612	60867	0	0
T4	34247	9474	0	0
T5	1121	0	0	0
T6	114834	13089	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	10285	0	0
T19	0	11209	0	0
T22	0	17313	0	0
T23	0	13363	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	107726263	0	0
T1	137144	67588	0	0
T2	898683	590998	0	0
T3	274612	81824	0	0
T4	34247	11913	0	0
T5	1121	0	0	0
T6	114834	13995	0	0
T10	60759	0	0	0
T15	5068	0	0	0
T16	206092	73981	0	0
T17	52740	12514	0	0
T19	0	14223	0	0
T22	0	137159	0	0
T23	0	171305	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380986542	380077602	0	0
T1	137144	137056	0	0
T2	898683	898600	0	0
T3	274612	274554	0	0
T4	34247	34153	0	0
T5	1121	1044	0	0
T6	114834	114666	0	0
T10	60759	60631	0	0
T15	5068	4973	0	0
T16	206092	206008	0	0
T17	52740	52663	0	0