Unified Coverage Report :: Module :: flash_ctrl_core_reg_top

Module : flash_ctrl_core_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.84	100.00	99.35			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core	99.84	100.00	99.35			100.00	100.00

---

Module Instance : tb.dut.u_reg_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.84	100.00	99.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	98.96	98.43	100.00		98.88	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.34	97.12	92.80	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_addr	100.00	100.00	100.00			100.00
u_alert_test_fatal_err	100.00	100.00
u_alert_test_fatal_prim_flash_alert	100.00	100.00
u_alert_test_fatal_std_err	100.00	100.00
u_alert_test_recov_err	100.00	100.00
u_alert_test_recov_prim_flash_alert	100.00	100.00
u_bank0_info0_page_cfg_0_ecc_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_erase_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_he_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_prog_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_rd_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_scramble_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_ecc_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_erase_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_he_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_prog_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_rd_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_scramble_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_ecc_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_erase_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_he_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_prog_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_rd_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_scramble_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_ecc_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_erase_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_he_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_prog_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_rd_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_scramble_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_ecc_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_erase_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_he_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_prog_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_rd_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_scramble_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_ecc_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_erase_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_he_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_prog_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_rd_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_scramble_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_ecc_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_erase_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_he_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_prog_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_rd_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_scramble_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_ecc_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_erase_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_he_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_prog_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_rd_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_scramble_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_ecc_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_erase_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_he_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_prog_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_rd_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_scramble_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_ecc_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_erase_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_he_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_prog_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_rd_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_scramble_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_0	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_1	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_2	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_3	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_4	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_5	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_6	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_7	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_8	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_9	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_ecc_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_erase_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_he_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_prog_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_rd_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_scramble_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_regwen	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_ecc_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_erase_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_he_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_prog_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_rd_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_scramble_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_ecc_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_erase_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_he_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_prog_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_rd_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_scramble_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_regwen_0	100.00	100.00	100.00			100.00
u_bank0_info2_regwen_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_ecc_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_erase_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_he_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_prog_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_rd_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_scramble_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_ecc_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_erase_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_he_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_prog_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_rd_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_scramble_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_ecc_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_erase_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_he_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_prog_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_rd_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_scramble_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_ecc_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_erase_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_he_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_prog_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_rd_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_scramble_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_ecc_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_erase_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_he_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_prog_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_rd_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_scramble_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_ecc_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_erase_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_he_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_prog_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_rd_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_scramble_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_ecc_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_erase_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_he_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_prog_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_rd_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_scramble_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_ecc_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_erase_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_he_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_prog_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_rd_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_scramble_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_ecc_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_erase_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_he_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_prog_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_rd_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_scramble_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_ecc_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_erase_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_he_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_prog_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_rd_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_scramble_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_0	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_1	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_2	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_3	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_4	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_5	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_6	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_7	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_8	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_9	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_ecc_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_erase_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_he_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_prog_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_rd_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_scramble_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_regwen	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_ecc_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_erase_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_he_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_prog_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_rd_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_scramble_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_ecc_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_erase_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_he_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_prog_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_rd_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_scramble_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_regwen_0	100.00	100.00	100.00			100.00
u_bank1_info2_regwen_1	100.00	100.00	100.00			100.00
u_bank_cfg_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_control_erase_sel	100.00	100.00	100.00			100.00
u_control_info_sel	100.00	100.00	100.00			100.00
u_control_num	100.00	100.00	100.00			100.00
u_control_op	100.00	100.00	100.00			100.00
u_control_partition_sel	100.00	100.00	100.00			100.00
u_control_prog_sel	100.00	100.00	100.00			100.00
u_control_start	100.00	100.00	100.00			100.00
u_ctrl_regwen	100.00	100.00
u_curr_fifo_lvl_prog	100.00	100.00
u_curr_fifo_lvl_rd	100.00	100.00
u_debug_state	100.00	100.00
u_default_region_ecc_en	100.00	100.00	100.00			100.00
u_default_region_erase_en	100.00	100.00	100.00			100.00
u_default_region_he_en	100.00	100.00	100.00			100.00
u_default_region_prog_en	100.00	100.00	100.00			100.00
u_default_region_rd_en	100.00	100.00	100.00			100.00
u_default_region_scramble_en	100.00	100.00	100.00			100.00
u_dis	100.00	100.00	100.00			100.00
u_ecc_single_err_addr_0	100.00	100.00	100.00			100.00
u_ecc_single_err_addr_1	100.00	100.00	100.00			100.00
u_ecc_single_err_cnt_ecc_single_err_cnt_0	100.00	100.00	100.00			100.00
u_ecc_single_err_cnt_ecc_single_err_cnt_1	100.00	100.00	100.00			100.00
u_erase_suspend	100.00	100.00	100.00			100.00
u_err_addr	100.00	100.00	100.00			100.00
u_err_code_macro_err	88.89	100.00	66.67			100.00
u_err_code_mp_err	100.00	100.00	100.00			100.00
u_err_code_op_err	100.00	100.00	100.00			100.00
u_err_code_prog_err	100.00	100.00	100.00			100.00
u_err_code_prog_type_err	100.00	100.00	100.00			100.00
u_err_code_prog_win_err	100.00	100.00	100.00			100.00
u_err_code_rd_err	100.00	100.00	100.00			100.00
u_err_code_update_err	88.89	100.00	66.67			100.00
u_exec	100.00	100.00	100.00			100.00
u_fault_status_arb_err	96.30	88.89	100.00			100.00
u_fault_status_host_gnt_err	96.30	88.89	100.00			100.00
u_fault_status_mp_err	96.30	88.89	100.00			100.00
u_fault_status_op_err	96.30	88.89	100.00			100.00
u_fault_status_phy_relbl_err	96.30	88.89	100.00			100.00
u_fault_status_phy_storage_err	96.30	88.89	100.00			100.00
u_fault_status_prog_err	96.30	88.89	100.00			100.00
u_fault_status_prog_type_err	96.30	88.89	100.00			100.00
u_fault_status_prog_win_err	96.30	88.89	100.00			100.00
u_fault_status_rd_err	96.30	88.89	100.00			100.00
u_fault_status_seed_err	96.30	88.89	100.00			100.00
u_fault_status_spurious_ack	96.30	88.89	100.00			100.00
u_fifo_lvl_prog	100.00	100.00	100.00			100.00
u_fifo_lvl_rd	100.00	100.00	100.00			100.00
u_fifo_rst	100.00	100.00	100.00			100.00
u_hw_info_cfg_override_ecc_dis	100.00	100.00	100.00			100.00
u_hw_info_cfg_override_scramble_dis	100.00	100.00	100.00			100.00
u_init	100.00	100.00	100.00			100.00
u_intr_enable_corr_err	100.00	100.00	100.00			100.00
u_intr_enable_op_done	100.00	100.00	100.00			100.00
u_intr_enable_prog_empty	100.00	100.00	100.00			100.00
u_intr_enable_prog_lvl	100.00	100.00	100.00			100.00
u_intr_enable_rd_full	100.00	100.00	100.00			100.00
u_intr_enable_rd_lvl	100.00	100.00	100.00			100.00
u_intr_state_corr_err	100.00	100.00	100.00			100.00
u_intr_state_op_done	100.00	100.00	100.00			100.00
u_intr_state_prog_empty	62.59	77.78	50.00			60.00
u_intr_state_prog_lvl	62.59	77.78	50.00			60.00
u_intr_state_rd_full	62.59	77.78	50.00			60.00
u_intr_state_rd_lvl	62.59	77.78	50.00			60.00
u_intr_test_corr_err	100.00	100.00
u_intr_test_op_done	100.00	100.00
u_intr_test_prog_empty	100.00	100.00
u_intr_test_prog_lvl	100.00	100.00
u_intr_test_rd_full	100.00	100.00
u_intr_test_rd_lvl	100.00	100.00
u_mp_bank_cfg_shadowed_erase_en_0	96.88	100.00	87.50			100.00	100.00
u_mp_bank_cfg_shadowed_erase_en_1	96.88	100.00	87.50			100.00	100.00
u_mp_region_0_base_0	100.00	100.00	100.00			100.00
u_mp_region_0_size_0	100.00	100.00	100.00			100.00
u_mp_region_1_base_1	100.00	100.00	100.00			100.00
u_mp_region_1_size_1	100.00	100.00	100.00			100.00
u_mp_region_2_base_2	100.00	100.00	100.00			100.00
u_mp_region_2_size_2	100.00	100.00	100.00			100.00
u_mp_region_3_base_3	100.00	100.00	100.00			100.00
u_mp_region_3_size_3	100.00	100.00	100.00			100.00
u_mp_region_4_base_4	100.00	100.00	100.00			100.00
u_mp_region_4_size_4	100.00	100.00	100.00			100.00
u_mp_region_5_base_5	100.00	100.00	100.00			100.00
u_mp_region_5_size_5	100.00	100.00	100.00			100.00
u_mp_region_6_base_6	100.00	100.00	100.00			100.00
u_mp_region_6_size_6	100.00	100.00	100.00			100.00
u_mp_region_7_base_7	100.00	100.00	100.00			100.00
u_mp_region_7_size_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_ecc_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_erase_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_he_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_prog_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_rd_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_scramble_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_ecc_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_erase_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_he_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_prog_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_rd_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_scramble_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_ecc_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_erase_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_he_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_prog_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_rd_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_scramble_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_ecc_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_erase_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_he_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_prog_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_rd_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_scramble_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_ecc_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_erase_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_he_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_prog_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_rd_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_scramble_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_ecc_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_erase_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_he_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_prog_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_rd_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_scramble_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_ecc_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_erase_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_he_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_prog_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_rd_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_scramble_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_ecc_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_erase_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_he_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_prog_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_rd_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_scramble_en_7	100.00	100.00	100.00			100.00
u_op_status_done	100.00	100.00	100.00			100.00
u_op_status_err	100.00	100.00	100.00			100.00
u_phy_alert_cfg_alert_ack	65.34	88.89	50.00			57.14
u_phy_alert_cfg_alert_trig	65.34	88.89	50.00			57.14
u_phy_status_init_wip	62.59	77.78	50.00			60.00
u_phy_status_prog_normal_avail	58.89	66.67	50.00			60.00
u_phy_status_prog_repair_avail	58.89	66.67	50.00			60.00
u_prim_reg_we_check	100.00	100.00		100.00
u_prog_type_en_normal	100.00	100.00	100.00			100.00
u_prog_type_en_repair	100.00	100.00	100.00			100.00
u_reg_if	98.49	98.72	95.24			100.00	100.00
u_region_cfg_regwen_0	100.00	100.00	100.00			100.00
u_region_cfg_regwen_1	100.00	100.00	100.00			100.00
u_region_cfg_regwen_2	100.00	100.00	100.00			100.00
u_region_cfg_regwen_3	100.00	100.00	100.00			100.00
u_region_cfg_regwen_4	100.00	100.00	100.00			100.00
u_region_cfg_regwen_5	100.00	100.00	100.00			100.00
u_region_cfg_regwen_6	100.00	100.00	100.00			100.00
u_region_cfg_regwen_7	100.00	100.00	100.00			100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_scratch	100.00	100.00	100.00			100.00
u_socket	92.21	96.18	82.65			90.00	100.00
u_status_init_wip	62.59	77.78	50.00			60.00
u_status_initialized	62.59	77.78	50.00			60.00
u_status_prog_empty	100.00	100.00	100.00			100.00
u_status_prog_full	100.00	100.00	100.00			100.00
u_status_rd_empty	100.00	100.00	100.00			100.00
u_status_rd_full	100.00	100.00	100.00			100.00
u_std_fault_status_arb_fsm_err	96.30	88.89	100.00			100.00
u_std_fault_status_ctrl_cnt_err	96.30	88.89	100.00			100.00
u_std_fault_status_fifo_err	96.30	88.89	100.00			100.00
u_std_fault_status_lcmgr_err	96.30	88.89	100.00			100.00
u_std_fault_status_lcmgr_intg_err	96.30	88.89	100.00			100.00
u_std_fault_status_phy_fsm_err	96.30	88.89	100.00			100.00
u_std_fault_status_prog_intg_err	96.30	88.89	100.00			100.00
u_std_fault_status_reg_intg_err	96.30	88.89	100.00			100.00
u_std_fault_status_storage_err	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
TOTAL		1152	1152	100.00
ALWAYS	77	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
ALWAYS	136	3	3	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1364	1	1	100.00
CONT_ASSIGN	1380	1	1	100.00
CONT_ASSIGN	1396	1	1	100.00
CONT_ASSIGN	1412	1	1	100.00
CONT_ASSIGN	1428	1	1	100.00
CONT_ASSIGN	1444	1	1	100.00
CONT_ASSIGN	1450	1	1	100.00
CONT_ASSIGN	1465	1	1	100.00
CONT_ASSIGN	1481	1	1	100.00
CONT_ASSIGN	1497	1	1	100.00
CONT_ASSIGN	1513	1	1	100.00
CONT_ASSIGN	1529	1	1	100.00
CONT_ASSIGN	1635	1	1	100.00
CONT_ASSIGN	1829	1	1	100.00
CONT_ASSIGN	1860	1	1	100.00
CONT_ASSIGN	2180	1	1	100.00
CONT_ASSIGN	2375	1	1	100.00
CONT_ASSIGN	2570	1	1	100.00
CONT_ASSIGN	2765	1	1	100.00
CONT_ASSIGN	2960	1	1	100.00
CONT_ASSIGN	3155	1	1	100.00
CONT_ASSIGN	3350	1	1	100.00
CONT_ASSIGN	3545	1	1	100.00
CONT_ASSIGN	3740	1	1	100.00
CONT_ASSIGN	3800	1	1	100.00
CONT_ASSIGN	3860	1	1	100.00
CONT_ASSIGN	3920	1	1	100.00
CONT_ASSIGN	3980	1	1	100.00
CONT_ASSIGN	4040	1	1	100.00
CONT_ASSIGN	4100	1	1	100.00
CONT_ASSIGN	4160	1	1	100.00
CONT_ASSIGN	4674	1	1	100.00
CONT_ASSIGN	4869	1	1	100.00
CONT_ASSIGN	5064	1	1	100.00
CONT_ASSIGN	5259	1	1	100.00
CONT_ASSIGN	5454	1	1	100.00
CONT_ASSIGN	5649	1	1	100.00
CONT_ASSIGN	5844	1	1	100.00
CONT_ASSIGN	6039	1	1	100.00
CONT_ASSIGN	6234	1	1	100.00
CONT_ASSIGN	6429	1	1	100.00
CONT_ASSIGN	6653	1	1	100.00
CONT_ASSIGN	6906	1	1	100.00
CONT_ASSIGN	7101	1	1	100.00
CONT_ASSIGN	7586	1	1	100.00
CONT_ASSIGN	7781	1	1	100.00
CONT_ASSIGN	7976	1	1	100.00
CONT_ASSIGN	8171	1	1	100.00
CONT_ASSIGN	8366	1	1	100.00
CONT_ASSIGN	8561	1	1	100.00
CONT_ASSIGN	8756	1	1	100.00
CONT_ASSIGN	8951	1	1	100.00
CONT_ASSIGN	9146	1	1	100.00
CONT_ASSIGN	9341	1	1	100.00
CONT_ASSIGN	9565	1	1	100.00
CONT_ASSIGN	9818	1	1	100.00
CONT_ASSIGN	10013	1	1	100.00
CONT_ASSIGN	10292	1	1	100.00
ALWAYS	11820	109	109	100.00
CONT_ASSIGN	11931	1	1	100.00
ALWAYS	11935	1	1	100.00
CONT_ASSIGN	12047	1	1	100.00
CONT_ASSIGN	12049	1	1	100.00
CONT_ASSIGN	12051	1	1	100.00
CONT_ASSIGN	12052	1	1	100.00
CONT_ASSIGN	12054	1	1	100.00
CONT_ASSIGN	12056	1	1	100.00
CONT_ASSIGN	12058	1	1	100.00
CONT_ASSIGN	12060	1	1	100.00
CONT_ASSIGN	12062	1	1	100.00
CONT_ASSIGN	12064	1	1	100.00
CONT_ASSIGN	12065	1	1	100.00
CONT_ASSIGN	12067	1	1	100.00
CONT_ASSIGN	12069	1	1	100.00
CONT_ASSIGN	12071	1	1	100.00
CONT_ASSIGN	12073	1	1	100.00
CONT_ASSIGN	12075	1	1	100.00
CONT_ASSIGN	12077	1	1	100.00
CONT_ASSIGN	12078	1	1	100.00
CONT_ASSIGN	12080	1	1	100.00
CONT_ASSIGN	12082	1	1	100.00
CONT_ASSIGN	12084	1	1	100.00
CONT_ASSIGN	12086	1	1	100.00
CONT_ASSIGN	12088	1	1	100.00
CONT_ASSIGN	12089	1	1	100.00
CONT_ASSIGN	12091	1	1	100.00
CONT_ASSIGN	12092	1	1	100.00
CONT_ASSIGN	12094	1	1	100.00
CONT_ASSIGN	12095	1	1	100.00
CONT_ASSIGN	12097	1	1	100.00
CONT_ASSIGN	12098	1	1	100.00
CONT_ASSIGN	12099	1	1	100.00
CONT_ASSIGN	12101	1	1	100.00
CONT_ASSIGN	12103	1	1	100.00
CONT_ASSIGN	12105	1	1	100.00
CONT_ASSIGN	12107	1	1	100.00
CONT_ASSIGN	12109	1	1	100.00
CONT_ASSIGN	12111	1	1	100.00
CONT_ASSIGN	12113	1	1	100.00
CONT_ASSIGN	12114	1	1	100.00
CONT_ASSIGN	12116	1	1	100.00
CONT_ASSIGN	12117	1	1	100.00
CONT_ASSIGN	12119	1	1	100.00
CONT_ASSIGN	12121	1	1	100.00
CONT_ASSIGN	12122	1	1	100.00
CONT_ASSIGN	12124	1	1	100.00
CONT_ASSIGN	12125	1	1	100.00
CONT_ASSIGN	12127	1	1	100.00
CONT_ASSIGN	12128	1	1	100.00
CONT_ASSIGN	12130	1	1	100.00
CONT_ASSIGN	12131	1	1	100.00
CONT_ASSIGN	12133	1	1	100.00
CONT_ASSIGN	12134	1	1	100.00
CONT_ASSIGN	12136	1	1	100.00
CONT_ASSIGN	12137	1	1	100.00
CONT_ASSIGN	12139	1	1	100.00
CONT_ASSIGN	12140	1	1	100.00
CONT_ASSIGN	12142	1	1	100.00
CONT_ASSIGN	12143	1	1	100.00
CONT_ASSIGN	12145	1	1	100.00
CONT_ASSIGN	12146	1	1	100.00
CONT_ASSIGN	12148	1	1	100.00
CONT_ASSIGN	12149	1	1	100.00
CONT_ASSIGN	12151	1	1	100.00
CONT_ASSIGN	12153	1	1	100.00
CONT_ASSIGN	12155	1	1	100.00
CONT_ASSIGN	12157	1	1	100.00
CONT_ASSIGN	12159	1	1	100.00
CONT_ASSIGN	12161	1	1	100.00
CONT_ASSIGN	12163	1	1	100.00
CONT_ASSIGN	12164	1	1	100.00
CONT_ASSIGN	12166	1	1	100.00
CONT_ASSIGN	12168	1	1	100.00
CONT_ASSIGN	12170	1	1	100.00
CONT_ASSIGN	12172	1	1	100.00
CONT_ASSIGN	12174	1	1	100.00
CONT_ASSIGN	12176	1	1	100.00
CONT_ASSIGN	12178	1	1	100.00
CONT_ASSIGN	12179	1	1	100.00
CONT_ASSIGN	12181	1	1	100.00
CONT_ASSIGN	12183	1	1	100.00
CONT_ASSIGN	12185	1	1	100.00
CONT_ASSIGN	12187	1	1	100.00
CONT_ASSIGN	12189	1	1	100.00
CONT_ASSIGN	12191	1	1	100.00
CONT_ASSIGN	12193	1	1	100.00
CONT_ASSIGN	12194	1	1	100.00
CONT_ASSIGN	12196	1	1	100.00
CONT_ASSIGN	12198	1	1	100.00
CONT_ASSIGN	12200	1	1	100.00
CONT_ASSIGN	12202	1	1	100.00
CONT_ASSIGN	12204	1	1	100.00
CONT_ASSIGN	12206	1	1	100.00
CONT_ASSIGN	12208	1	1	100.00
CONT_ASSIGN	12209	1	1	100.00
CONT_ASSIGN	12211	1	1	100.00
CONT_ASSIGN	12213	1	1	100.00
CONT_ASSIGN	12215	1	1	100.00
CONT_ASSIGN	12217	1	1	100.00
CONT_ASSIGN	12219	1	1	100.00
CONT_ASSIGN	12221	1	1	100.00
CONT_ASSIGN	12223	1	1	100.00
CONT_ASSIGN	12224	1	1	100.00
CONT_ASSIGN	12226	1	1	100.00
CONT_ASSIGN	12228	1	1	100.00
CONT_ASSIGN	12230	1	1	100.00
CONT_ASSIGN	12232	1	1	100.00
CONT_ASSIGN	12234	1	1	100.00
CONT_ASSIGN	12236	1	1	100.00
CONT_ASSIGN	12238	1	1	100.00
CONT_ASSIGN	12239	1	1	100.00
CONT_ASSIGN	12241	1	1	100.00
CONT_ASSIGN	12243	1	1	100.00
CONT_ASSIGN	12245	1	1	100.00
CONT_ASSIGN	12247	1	1	100.00
CONT_ASSIGN	12249	1	1	100.00
CONT_ASSIGN	12251	1	1	100.00
CONT_ASSIGN	12253	1	1	100.00
CONT_ASSIGN	12254	1	1	100.00
CONT_ASSIGN	12256	1	1	100.00
CONT_ASSIGN	12258	1	1	100.00
CONT_ASSIGN	12260	1	1	100.00
CONT_ASSIGN	12262	1	1	100.00
CONT_ASSIGN	12264	1	1	100.00
CONT_ASSIGN	12266	1	1	100.00
CONT_ASSIGN	12268	1	1	100.00
CONT_ASSIGN	12269	1	1	100.00
CONT_ASSIGN	12271	1	1	100.00
CONT_ASSIGN	12273	1	1	100.00
CONT_ASSIGN	12274	1	1	100.00
CONT_ASSIGN	12276	1	1	100.00
CONT_ASSIGN	12278	1	1	100.00
CONT_ASSIGN	12279	1	1	100.00
CONT_ASSIGN	12281	1	1	100.00
CONT_ASSIGN	12283	1	1	100.00
CONT_ASSIGN	12284	1	1	100.00
CONT_ASSIGN	12286	1	1	100.00
CONT_ASSIGN	12288	1	1	100.00
CONT_ASSIGN	12289	1	1	100.00
CONT_ASSIGN	12291	1	1	100.00
CONT_ASSIGN	12293	1	1	100.00
CONT_ASSIGN	12294	1	1	100.00
CONT_ASSIGN	12296	1	1	100.00
CONT_ASSIGN	12298	1	1	100.00
CONT_ASSIGN	12299	1	1	100.00
CONT_ASSIGN	12301	1	1	100.00
CONT_ASSIGN	12303	1	1	100.00
CONT_ASSIGN	12304	1	1	100.00
CONT_ASSIGN	12306	1	1	100.00
CONT_ASSIGN	12308	1	1	100.00
CONT_ASSIGN	12309	1	1	100.00
CONT_ASSIGN	12311	1	1	100.00
CONT_ASSIGN	12313	1	1	100.00
CONT_ASSIGN	12315	1	1	100.00
CONT_ASSIGN	12317	1	1	100.00
CONT_ASSIGN	12319	1	1	100.00
CONT_ASSIGN	12321	1	1	100.00
CONT_ASSIGN	12322	1	1	100.00
CONT_ASSIGN	12324	1	1	100.00
CONT_ASSIGN	12325	1	1	100.00
CONT_ASSIGN	12327	1	1	100.00
CONT_ASSIGN	12328	1	1	100.00
CONT_ASSIGN	12330	1	1	100.00
CONT_ASSIGN	12331	1	1	100.00
CONT_ASSIGN	12333	1	1	100.00
CONT_ASSIGN	12334	1	1	100.00
CONT_ASSIGN	12336	1	1	100.00
CONT_ASSIGN	12337	1	1	100.00
CONT_ASSIGN	12339	1	1	100.00
CONT_ASSIGN	12340	1	1	100.00
CONT_ASSIGN	12342	1	1	100.00
CONT_ASSIGN	12343	1	1	100.00
CONT_ASSIGN	12345	1	1	100.00
CONT_ASSIGN	12346	1	1	100.00
CONT_ASSIGN	12348	1	1	100.00
CONT_ASSIGN	12349	1	1	100.00
CONT_ASSIGN	12351	1	1	100.00
CONT_ASSIGN	12352	1	1	100.00
CONT_ASSIGN	12354	1	1	100.00
CONT_ASSIGN	12356	1	1	100.00
CONT_ASSIGN	12358	1	1	100.00
CONT_ASSIGN	12360	1	1	100.00
CONT_ASSIGN	12362	1	1	100.00
CONT_ASSIGN	12364	1	1	100.00
CONT_ASSIGN	12366	1	1	100.00
CONT_ASSIGN	12367	1	1	100.00
CONT_ASSIGN	12369	1	1	100.00
CONT_ASSIGN	12371	1	1	100.00
CONT_ASSIGN	12373	1	1	100.00
CONT_ASSIGN	12375	1	1	100.00
CONT_ASSIGN	12377	1	1	100.00
CONT_ASSIGN	12379	1	1	100.00
CONT_ASSIGN	12381	1	1	100.00
CONT_ASSIGN	12382	1	1	100.00
CONT_ASSIGN	12384	1	1	100.00
CONT_ASSIGN	12386	1	1	100.00
CONT_ASSIGN	12388	1	1	100.00
CONT_ASSIGN	12390	1	1	100.00
CONT_ASSIGN	12392	1	1	100.00
CONT_ASSIGN	12394	1	1	100.00
CONT_ASSIGN	12396	1	1	100.00
CONT_ASSIGN	12397	1	1	100.00
CONT_ASSIGN	12399	1	1	100.00
CONT_ASSIGN	12401	1	1	100.00
CONT_ASSIGN	12403	1	1	100.00
CONT_ASSIGN	12405	1	1	100.00
CONT_ASSIGN	12407	1	1	100.00
CONT_ASSIGN	12409	1	1	100.00
CONT_ASSIGN	12411	1	1	100.00
CONT_ASSIGN	12412	1	1	100.00
CONT_ASSIGN	12414	1	1	100.00
CONT_ASSIGN	12416	1	1	100.00
CONT_ASSIGN	12418	1	1	100.00
CONT_ASSIGN	12420	1	1	100.00
CONT_ASSIGN	12422	1	1	100.00
CONT_ASSIGN	12424	1	1	100.00
CONT_ASSIGN	12426	1	1	100.00
CONT_ASSIGN	12427	1	1	100.00
CONT_ASSIGN	12429	1	1	100.00
CONT_ASSIGN	12431	1	1	100.00
CONT_ASSIGN	12433	1	1	100.00
CONT_ASSIGN	12435	1	1	100.00
CONT_ASSIGN	12437	1	1	100.00
CONT_ASSIGN	12439	1	1	100.00
CONT_ASSIGN	12441	1	1	100.00
CONT_ASSIGN	12442	1	1	100.00
CONT_ASSIGN	12444	1	1	100.00
CONT_ASSIGN	12446	1	1	100.00
CONT_ASSIGN	12448	1	1	100.00
CONT_ASSIGN	12450	1	1	100.00
CONT_ASSIGN	12452	1	1	100.00
CONT_ASSIGN	12454	1	1	100.00
CONT_ASSIGN	12456	1	1	100.00
CONT_ASSIGN	12457	1	1	100.00
CONT_ASSIGN	12459	1	1	100.00
CONT_ASSIGN	12461	1	1	100.00
CONT_ASSIGN	12463	1	1	100.00
CONT_ASSIGN	12465	1	1	100.00
CONT_ASSIGN	12467	1	1	100.00
CONT_ASSIGN	12469	1	1	100.00
CONT_ASSIGN	12471	1	1	100.00
CONT_ASSIGN	12472	1	1	100.00
CONT_ASSIGN	12474	1	1	100.00
CONT_ASSIGN	12476	1	1	100.00
CONT_ASSIGN	12478	1	1	100.00
CONT_ASSIGN	12480	1	1	100.00
CONT_ASSIGN	12482	1	1	100.00
CONT_ASSIGN	12484	1	1	100.00
CONT_ASSIGN	12486	1	1	100.00
CONT_ASSIGN	12487	1	1	100.00
CONT_ASSIGN	12489	1	1	100.00
CONT_ASSIGN	12491	1	1	100.00
CONT_ASSIGN	12493	1	1	100.00
CONT_ASSIGN	12495	1	1	100.00
CONT_ASSIGN	12497	1	1	100.00
CONT_ASSIGN	12499	1	1	100.00
CONT_ASSIGN	12501	1	1	100.00
CONT_ASSIGN	12502	1	1	100.00
CONT_ASSIGN	12504	1	1	100.00
CONT_ASSIGN	12505	1	1	100.00
CONT_ASSIGN	12507	1	1	100.00
CONT_ASSIGN	12509	1	1	100.00
CONT_ASSIGN	12511	1	1	100.00
CONT_ASSIGN	12513	1	1	100.00
CONT_ASSIGN	12515	1	1	100.00
CONT_ASSIGN	12517	1	1	100.00
CONT_ASSIGN	12519	1	1	100.00
CONT_ASSIGN	12520	1	1	100.00
CONT_ASSIGN	12522	1	1	100.00
CONT_ASSIGN	12523	1	1	100.00
CONT_ASSIGN	12525	1	1	100.00
CONT_ASSIGN	12526	1	1	100.00
CONT_ASSIGN	12528	1	1	100.00
CONT_ASSIGN	12530	1	1	100.00
CONT_ASSIGN	12532	1	1	100.00
CONT_ASSIGN	12534	1	1	100.00
CONT_ASSIGN	12536	1	1	100.00
CONT_ASSIGN	12538	1	1	100.00
CONT_ASSIGN	12540	1	1	100.00
CONT_ASSIGN	12541	1	1	100.00
CONT_ASSIGN	12543	1	1	100.00
CONT_ASSIGN	12545	1	1	100.00
CONT_ASSIGN	12547	1	1	100.00
CONT_ASSIGN	12549	1	1	100.00
CONT_ASSIGN	12551	1	1	100.00
CONT_ASSIGN	12553	1	1	100.00
CONT_ASSIGN	12555	1	1	100.00
CONT_ASSIGN	12556	1	1	100.00
CONT_ASSIGN	12558	1	1	100.00
CONT_ASSIGN	12559	1	1	100.00
CONT_ASSIGN	12561	1	1	100.00
CONT_ASSIGN	12562	1	1	100.00
CONT_ASSIGN	12564	1	1	100.00
CONT_ASSIGN	12565	1	1	100.00
CONT_ASSIGN	12567	1	1	100.00
CONT_ASSIGN	12568	1	1	100.00
CONT_ASSIGN	12570	1	1	100.00
CONT_ASSIGN	12571	1	1	100.00
CONT_ASSIGN	12573	1	1	100.00
CONT_ASSIGN	12574	1	1	100.00
CONT_ASSIGN	12576	1	1	100.00
CONT_ASSIGN	12577	1	1	100.00
CONT_ASSIGN	12579	1	1	100.00
CONT_ASSIGN	12580	1	1	100.00
CONT_ASSIGN	12582	1	1	100.00
CONT_ASSIGN	12583	1	1	100.00
CONT_ASSIGN	12585	1	1	100.00
CONT_ASSIGN	12586	1	1	100.00
CONT_ASSIGN	12588	1	1	100.00
CONT_ASSIGN	12590	1	1	100.00
CONT_ASSIGN	12592	1	1	100.00
CONT_ASSIGN	12594	1	1	100.00
CONT_ASSIGN	12596	1	1	100.00
CONT_ASSIGN	12598	1	1	100.00
CONT_ASSIGN	12600	1	1	100.00
CONT_ASSIGN	12601	1	1	100.00
CONT_ASSIGN	12603	1	1	100.00
CONT_ASSIGN	12605	1	1	100.00
CONT_ASSIGN	12607	1	1	100.00
CONT_ASSIGN	12609	1	1	100.00
CONT_ASSIGN	12611	1	1	100.00
CONT_ASSIGN	12613	1	1	100.00
CONT_ASSIGN	12615	1	1	100.00
CONT_ASSIGN	12616	1	1	100.00
CONT_ASSIGN	12618	1	1	100.00
CONT_ASSIGN	12620	1	1	100.00
CONT_ASSIGN	12622	1	1	100.00
CONT_ASSIGN	12624	1	1	100.00
CONT_ASSIGN	12626	1	1	100.00
CONT_ASSIGN	12628	1	1	100.00
CONT_ASSIGN	12630	1	1	100.00
CONT_ASSIGN	12631	1	1	100.00
CONT_ASSIGN	12633	1	1	100.00
CONT_ASSIGN	12635	1	1	100.00
CONT_ASSIGN	12637	1	1	100.00
CONT_ASSIGN	12639	1	1	100.00
CONT_ASSIGN	12641	1	1	100.00
CONT_ASSIGN	12643	1	1	100.00
CONT_ASSIGN	12645	1	1	100.00
CONT_ASSIGN	12646	1	1	100.00
CONT_ASSIGN	12648	1	1	100.00
CONT_ASSIGN	12650	1	1	100.00
CONT_ASSIGN	12652	1	1	100.00
CONT_ASSIGN	12654	1	1	100.00
CONT_ASSIGN	12656	1	1	100.00
CONT_ASSIGN	12658	1	1	100.00
CONT_ASSIGN	12660	1	1	100.00
CONT_ASSIGN	12661	1	1	100.00
CONT_ASSIGN	12663	1	1	100.00
CONT_ASSIGN	12665	1	1	100.00
CONT_ASSIGN	12667	1	1	100.00
CONT_ASSIGN	12669	1	1	100.00
CONT_ASSIGN	12671	1	1	100.00
CONT_ASSIGN	12673	1	1	100.00
CONT_ASSIGN	12675	1	1	100.00
CONT_ASSIGN	12676	1	1	100.00
CONT_ASSIGN	12678	1	1	100.00
CONT_ASSIGN	12680	1	1	100.00
CONT_ASSIGN	12682	1	1	100.00
CONT_ASSIGN	12684	1	1	100.00
CONT_ASSIGN	12686	1	1	100.00
CONT_ASSIGN	12688	1	1	100.00
CONT_ASSIGN	12690	1	1	100.00
CONT_ASSIGN	12691	1	1	100.00
CONT_ASSIGN	12693	1	1	100.00
CONT_ASSIGN	12695	1	1	100.00
CONT_ASSIGN	12697	1	1	100.00
CONT_ASSIGN	12699	1	1	100.00
CONT_ASSIGN	12701	1	1	100.00
CONT_ASSIGN	12703	1	1	100.00
CONT_ASSIGN	12705	1	1	100.00
CONT_ASSIGN	12706	1	1	100.00
CONT_ASSIGN	12708	1	1	100.00
CONT_ASSIGN	12710	1	1	100.00
CONT_ASSIGN	12712	1	1	100.00
CONT_ASSIGN	12714	1	1	100.00
CONT_ASSIGN	12716	1	1	100.00
CONT_ASSIGN	12718	1	1	100.00
CONT_ASSIGN	12720	1	1	100.00
CONT_ASSIGN	12721	1	1	100.00
CONT_ASSIGN	12723	1	1	100.00
CONT_ASSIGN	12725	1	1	100.00
CONT_ASSIGN	12727	1	1	100.00
CONT_ASSIGN	12729	1	1	100.00
CONT_ASSIGN	12731	1	1	100.00
CONT_ASSIGN	12733	1	1	100.00
CONT_ASSIGN	12735	1	1	100.00
CONT_ASSIGN	12736	1	1	100.00
CONT_ASSIGN	12738	1	1	100.00
CONT_ASSIGN	12739	1	1	100.00
CONT_ASSIGN	12741	1	1	100.00
CONT_ASSIGN	12743	1	1	100.00
CONT_ASSIGN	12745	1	1	100.00
CONT_ASSIGN	12747	1	1	100.00
CONT_ASSIGN	12749	1	1	100.00
CONT_ASSIGN	12751	1	1	100.00
CONT_ASSIGN	12753	1	1	100.00
CONT_ASSIGN	12754	1	1	100.00
CONT_ASSIGN	12756	1	1	100.00
CONT_ASSIGN	12757	1	1	100.00
CONT_ASSIGN	12759	1	1	100.00
CONT_ASSIGN	12760	1	1	100.00
CONT_ASSIGN	12762	1	1	100.00
CONT_ASSIGN	12764	1	1	100.00
CONT_ASSIGN	12766	1	1	100.00
CONT_ASSIGN	12768	1	1	100.00
CONT_ASSIGN	12770	1	1	100.00
CONT_ASSIGN	12772	1	1	100.00
CONT_ASSIGN	12774	1	1	100.00
CONT_ASSIGN	12775	1	1	100.00
CONT_ASSIGN	12777	1	1	100.00
CONT_ASSIGN	12779	1	1	100.00
CONT_ASSIGN	12781	1	1	100.00
CONT_ASSIGN	12783	1	1	100.00
CONT_ASSIGN	12785	1	1	100.00
CONT_ASSIGN	12787	1	1	100.00
CONT_ASSIGN	12789	1	1	100.00
CONT_ASSIGN	12790	1	1	100.00
CONT_ASSIGN	12792	1	1	100.00
CONT_ASSIGN	12794	1	1	100.00
CONT_ASSIGN	12795	1	1	100.00
CONT_ASSIGN	12797	1	1	100.00
CONT_ASSIGN	12798	1	1	100.00
CONT_ASSIGN	12799	1	1	100.00
CONT_ASSIGN	12801	1	1	100.00
CONT_ASSIGN	12803	1	1	100.00
CONT_ASSIGN	12804	1	1	100.00
CONT_ASSIGN	12806	1	1	100.00
CONT_ASSIGN	12808	1	1	100.00
CONT_ASSIGN	12809	1	1	100.00
CONT_ASSIGN	12810	1	1	100.00
CONT_ASSIGN	12812	1	1	100.00
CONT_ASSIGN	12814	1	1	100.00
CONT_ASSIGN	12816	1	1	100.00
CONT_ASSIGN	12818	1	1	100.00
CONT_ASSIGN	12820	1	1	100.00
CONT_ASSIGN	12822	1	1	100.00
CONT_ASSIGN	12824	1	1	100.00
CONT_ASSIGN	12826	1	1	100.00
CONT_ASSIGN	12827	1	1	100.00
CONT_ASSIGN	12829	1	1	100.00
CONT_ASSIGN	12831	1	1	100.00
CONT_ASSIGN	12832	1	1	100.00
CONT_ASSIGN	12834	1	1	100.00
CONT_ASSIGN	12836	1	1	100.00
CONT_ASSIGN	12837	1	1	100.00
CONT_ASSIGN	12839	1	1	100.00
CONT_ASSIGN	12840	1	1	100.00
CONT_ASSIGN	12842	1	1	100.00
CONT_ASSIGN	12844	1	1	100.00
CONT_ASSIGN	12845	1	1	100.00
CONT_ASSIGN	12847	1	1	100.00
CONT_ASSIGN	12848	1	1	100.00
ALWAYS	12852	109	109	100.00
ALWAYS	12965	393	393	100.00
ALWAYS	13693	3	3	100.00
ALWAYS	13701	3	3	100.00
CONT_ASSIGN	13709	1	1	100.00
CONT_ASSIGN	13712	1	1	100.00
CONT_ASSIGN	13716	1	1	100.00
CONT_ASSIGN	13722	1	1	100.00
CONT_ASSIGN	13730	1	1	100.00
CONT_ASSIGN	13731	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
77	1	1
78	1	1
79	1	1
80	1	1
			MISSING_ELSE
86	1	1
104	1	1
105	1	1
107	1	1
108	1	1
109	1	1
110	1	1
136	1	1
143	1	1
144	1	1
			MISSING_ELSE
174	1	1
175	1	1
1349	1	1
1364	1	1
1380	1	1
1396	1	1
1412	1	1
1428	1	1
1444	1	1
1450	1	1
1465	1	1
1481	1	1
1497	1	1
1513	1	1
1529	1	1
1635	1	1
1829	1	1
1860	1	1
2180	1	1
2375	1	1
2570	1	1
2765	1	1
2960	1	1
3155	1	1
3350	1	1
3545	1	1
3740	1	1
3800	1	1
3860	1	1
3920	1	1
3980	1	1
4040	1	1
4100	1	1
4160	1	1
4674	1	1
4869	1	1
5064	1	1
5259	1	1
5454	1	1
5649	1	1
5844	1	1
6039	1	1
6234	1	1
6429	1	1
6653	1	1
6906	1	1
7101	1	1
7586	1	1
7781	1	1
7976	1	1
8171	1	1
8366	1	1
8561	1	1
8756	1	1
8951	1	1
9146	1	1
9341	1	1
9565	1	1
9818	1	1
10013	1	1
10292	1	1
11820	1	1
11821	1	1
11822	1	1
11823	1	1
11824	1	1
11825	1	1
11826	1	1
11827	1	1
11828	1	1
11829	1	1
11830	1	1
11831	1	1
11832	1	1
11833	1	1
11834	1	1
11835	1	1
11836	1	1
11837	1	1
11838	1	1
11839	1	1
11840	1	1
11841	1	1
11842	1	1
11843	1	1
11844	1	1
11845	1	1
11846	1	1
11847	1	1
11848	1	1
11849	1	1
11850	1	1
11851	1	1
11852	1	1
11853	1	1
11854	1	1
11855	1	1
11856	1	1
11857	1	1
11858	1	1
11859	1	1
11860	1	1
11861	1	1
11862	1	1
11863	1	1
11864	1	1
11865	1	1
11866	1	1
11867	1	1
11868	1	1
11869	1	1
11870	1	1
11871	1	1
11872	1	1
11873	1	1
11874	1	1
11875	1	1
11876	1	1
11877	1	1
11878	1	1
11879	1	1
11880	1	1
11881	1	1
11882	1	1
11883	1	1
11884	1	1
11885	1	1
11886	1	1
11887	1	1
11888	1	1
11889	1	1
11890	1	1
11891	1	1
11892	1	1
11893	1	1
11894	1	1
11895	1	1
11896	1	1
11897	1	1
11898	1	1
11899	1	1
11900	1	1
11901	1	1
11902	1	1
11903	1	1
11904	1	1
11905	1	1
11906	1	1
11907	1	1
11908	1	1
11909	1	1
11910	1	1
11911	1	1
11912	1	1
11913	1	1
11914	1	1
11915	1	1
11916	1	1
11917	1	1
11918	1	1
11919	1	1
11920	1	1
11921	1	1
11922	1	1
11923	1	1
11924	1	1
11925	1	1
11926	1	1
11927	1	1
11928	1	1
11931	1	1
11935	1	1
12047	1	1
12049	1	1
12051	1	1
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12060	1	1
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12194	1	1
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12206	1	1
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12211	1	1
12213	1	1
12215	1	1
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12219	1	1
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12224	1	1
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12230	1	1
12232	1	1
12234	1	1
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12243	1	1
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12247	1	1
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12254	1	1
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12260	1	1
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12311	1	1
12313	1	1
12315	1	1
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12325	1	1
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12340	1	1
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12345	1	1
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12360	1	1
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12480	1	1
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12484	1	1
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12495	1	1
12497	1	1
12499	1	1
12501	1	1
12502	1	1
12504	1	1
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12509	1	1
12511	1	1
12513	1	1
12515	1	1
12517	1	1
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12520	1	1
12522	1	1
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12525	1	1
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12528	1	1
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12538	1	1
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12545	1	1
12547	1	1
12549	1	1
12551	1	1
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12562	1	1
12564	1	1
12565	1	1
12567	1	1
12568	1	1
12570	1	1
12571	1	1
12573	1	1
12574	1	1
12576	1	1
12577	1	1
12579	1	1
12580	1	1
12582	1	1
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12585	1	1
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12598	1	1
12600	1	1
12601	1	1
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12607	1	1
12609	1	1
12611	1	1
12613	1	1
12615	1	1
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12618	1	1
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12622	1	1
12624	1	1
12626	1	1
12628	1	1
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12635	1	1
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12639	1	1
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12665	1	1
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12680	1	1
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12699	1	1
12701	1	1
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12705	1	1
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12710	1	1
12712	1	1
12714	1	1
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12718	1	1
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12721	1	1
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12725	1	1
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12731	1	1
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12735	1	1
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12760	1	1
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12768	1	1
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12775	1	1
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12785	1	1
12787	1	1
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12799	1	1
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12810	1	1
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12960	1	1
12965	1	1
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13256	1	1
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13258	1	1
13259	1	1
13263	1	1
13264	1	1
13265	1	1
13266	1	1
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13268	1	1
13269	1	1
13273	1	1
13274	1	1
13275	1	1
13276	1	1
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13284	1	1
13285	1	1
13286	1	1
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13288	1	1
13289	1	1
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13294	1	1
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13299	1	1
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13305	1	1
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13313	1	1
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13323	1	1
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13325	1	1
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13357	1	1
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13370	1	1
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13378	1	1
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13380	1	1
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13385	1	1
13389	1	1
13393	1	1
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13401	1	1
13405	1	1
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13413	1	1
13417	1	1
13421	1	1
13425	1	1
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13428	1	1
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13435	1	1
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13459	1	1
13460	1	1
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13465	1	1
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13467	1	1
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13488	1	1
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13490	1	1
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13495	1	1
13496	1	1
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13499	1	1
13500	1	1
13501	1	1
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13506	1	1
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13508	1	1
13509	1	1
13510	1	1
13511	1	1
13515	1	1
13516	1	1
13517	1	1
13518	1	1
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13520	1	1
13521	1	1
13525	1	1
13529	1	1
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13539	1	1
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13550	1	1
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13558	1	1
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13560	1	1
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13562	1	1
13563	1	1
13567	1	1
13568	1	1
13572	1	1
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13577	1	1
13581	1	1
13582	1	1
13586	1	1
13587	1	1
13588	1	1
13589	1	1
13590	1	1
13591	1	1
13595	1	1
13599	1	1
13600	1	1
13601	1	1
13602	1	1
13603	1	1
13604	1	1
13605	1	1
13606	1	1
13610	1	1
13611	1	1
13612	1	1
13613	1	1
13614	1	1
13615	1	1
13616	1	1
13617	1	1
13618	1	1
13622	1	1
13623	1	1
13624	1	1
13625	1	1
13626	1	1
13627	1	1
13628	1	1
13629	1	1
13630	1	1
13631	1	1
13632	1	1
13633	1	1
13637	1	1
13641	1	1
13642	1	1
13646	1	1
13650	1	1
13654	1	1
13655	1	1
13659	1	1
13660	1	1
13661	1	1
13665	1	1
13669	1	1
13670	1	1
13674	1	1
13678	1	1
13679	1	1
13693	1	1
13694	1	1
13696	1	1
13701	1	1
13702	1	1
13704	1	1
13709	1	1
13712	1	1
13716	1	1
13722	1	1
13730	1	1
13731	1	1

---

Cond Coverage for Module : flash_ctrl_core_reg_top

	Total	Covered	Percent
Conditions	1224	1216	99.35
Logical	1224	1216	99.35
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
67-11935	99.59
11935-12269	100.00
12274-13709	97.97

---

Branch Coverage for Module : flash_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
Branches		123	123	100.00
TERNARY	11931	2	2	100.00
IF	77	3	3	100.00
TERNARY	136	3	3	100.00
IF	143	2	2	100.00
CASE	12966	109	109	100.00
IF	13693	2	2	100.00
IF	13701	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	11931	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if ((!rst_ni))
-2-:	79	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	((tl_i.a_address[(AW - 1):0] inside {[432:435]})) ? 
-2-:	136	((tl_i.a_address[(AW - 1):0] inside {[436:439]})) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T215,T216,T217
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	12966	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T1,T2,T3
addr_hit[57]	Covered	T1,T2,T3
addr_hit[58]	Covered	T1,T2,T3
addr_hit[59]	Covered	T1,T2,T3
addr_hit[60]	Covered	T1,T2,T3
addr_hit[61]	Covered	T1,T2,T3
addr_hit[62]	Covered	T1,T2,T3
addr_hit[63]	Covered	T1,T2,T3
addr_hit[64]	Covered	T1,T2,T3
addr_hit[65]	Covered	T1,T2,T3
addr_hit[66]	Covered	T1,T2,T3
addr_hit[67]	Covered	T1,T2,T3
addr_hit[68]	Covered	T1,T2,T3
addr_hit[69]	Covered	T1,T2,T3
addr_hit[70]	Covered	T1,T2,T3
addr_hit[71]	Covered	T1,T2,T3
addr_hit[72]	Covered	T1,T2,T3
addr_hit[73]	Covered	T1,T2,T3
addr_hit[74]	Covered	T1,T2,T3
addr_hit[75]	Covered	T1,T2,T3
addr_hit[76]	Covered	T1,T2,T3
addr_hit[77]	Covered	T1,T2,T3
addr_hit[78]	Covered	T1,T2,T3
addr_hit[79]	Covered	T1,T2,T3
addr_hit[80]	Covered	T1,T2,T3
addr_hit[81]	Covered	T1,T2,T3
addr_hit[82]	Covered	T1,T2,T3
addr_hit[83]	Covered	T1,T2,T3
addr_hit[84]	Covered	T1,T2,T3
addr_hit[85]	Covered	T1,T2,T3
addr_hit[86]	Covered	T1,T2,T3
addr_hit[87]	Covered	T1,T2,T3
addr_hit[88]	Covered	T1,T2,T3
addr_hit[89]	Covered	T1,T2,T3
addr_hit[90]	Covered	T1,T2,T3
addr_hit[91]	Covered	T1,T2,T3
addr_hit[92]	Covered	T1,T2,T3
addr_hit[93]	Covered	T1,T2,T3
addr_hit[94]	Covered	T1,T2,T3
addr_hit[95]	Covered	T1,T2,T3
addr_hit[96]	Covered	T1,T2,T3
addr_hit[97]	Covered	T1,T2,T3
addr_hit[98]	Covered	T1,T2,T3
addr_hit[99]	Covered	T1,T2,T3
addr_hit[100]	Covered	T1,T2,T3
addr_hit[101]	Covered	T1,T2,T3
addr_hit[102]	Covered	T1,T2,T3
addr_hit[103]	Covered	T1,T2,T3
addr_hit[104]	Covered	T1,T2,T3
addr_hit[105]	Covered	T1,T2,T3
addr_hit[106]	Covered	T1,T2,T3
addr_hit[107]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	13693	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	13701	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_ctrl_core_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	383421541	24205444	0	0
reAfterRv	383421541	24205421	0	0
rePulse	383421541	21841267	0	0
wePulse	383421541	2364154	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	24205444	0	0
T1	137144	67274	0	0
T2	898683	110885	0	0
T3	274612	119176	0	0
T4	34247	9591	0	0
T5	1121	119	0	0
T6	114834	8228	0	0
T10	60759	161	0	0
T15	5068	1464	0	0
T16	206092	95799	0	0
T17	52740	17683	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	24205421	0	0
T1	137144	67274	0	0
T2	898683	110885	0	0
T3	274612	119176	0	0
T4	34247	9591	0	0
T5	1121	119	0	0
T6	114834	8228	0	0
T10	60759	161	0	0
T15	5068	1464	0	0
T16	206092	95799	0	0
T17	52740	17683	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	21841267	0	0
T1	137144	66672	0	0
T2	898683	102912	0	0
T3	274612	112476	0	0
T4	34247	7454	0	0
T5	1121	67	0	0
T6	114834	4169	0	0
T10	60759	115	0	0
T15	5068	1395	0	0
T16	206092	92531	0	0
T17	52740	13971	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2364154	0	0
T1	137144	602	0	0
T2	898683	7973	0	0
T3	274612	6700	0	0
T4	34247	2137	0	0
T5	1121	52	0	0
T6	114834	4059	0	0
T10	60759	46	0	0
T15	5068	69	0	0
T16	206092	3268	0	0
T17	52740	3712	0	0