Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.34	97.12	92.80	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	383421541	4328	0	0
addr_rd_A	383421541	2027	0	0
bank0_info0_page_cfg_0_rd_A	383421541	3472	0	0
bank0_info0_page_cfg_1_rd_A	383421541	3077	0	0
bank0_info0_page_cfg_2_rd_A	383421541	3366	0	0
bank0_info0_page_cfg_3_rd_A	383421541	3236	0	0
bank0_info0_page_cfg_4_rd_A	383421541	3154	0	0
bank0_info0_page_cfg_5_rd_A	383421541	3358	0	0
bank0_info0_page_cfg_6_rd_A	383421541	2973	0	0
bank0_info0_page_cfg_7_rd_A	383421541	3346	0	0
bank0_info0_page_cfg_8_rd_A	383421541	3439	0	0
bank0_info0_page_cfg_9_rd_A	383421541	2710	0	0
bank0_info0_regwen_0_rd_A	383421541	1826	0	0
bank0_info0_regwen_1_rd_A	383421541	1301	0	0
bank0_info0_regwen_2_rd_A	383421541	1844	0	0
bank0_info0_regwen_3_rd_A	383421541	1932	0	0
bank0_info0_regwen_4_rd_A	383421541	1959	0	0
bank0_info0_regwen_5_rd_A	383421541	1994	0	0
bank0_info0_regwen_6_rd_A	383421541	1955	0	0
bank0_info0_regwen_7_rd_A	383421541	1819	0	0
bank0_info0_regwen_8_rd_A	383421541	2053	0	0
bank0_info0_regwen_9_rd_A	383421541	1861	0	0
bank0_info1_page_cfg_rd_A	383421541	3245	0	0
bank0_info1_regwen_rd_A	383421541	1641	0	0
bank0_info2_page_cfg_0_rd_A	383421541	3464	0	0
bank0_info2_page_cfg_1_rd_A	383421541	2696	0	0
bank0_info2_regwen_0_rd_A	383421541	1963	0	0
bank0_info2_regwen_1_rd_A	383421541	2069	0	0
bank1_info0_page_cfg_0_rd_A	383421541	3488	0	0
bank1_info0_page_cfg_1_rd_A	383421541	3437	0	0
bank1_info0_page_cfg_2_rd_A	383421541	2816	0	0
bank1_info0_page_cfg_3_rd_A	383421541	3105	0	0
bank1_info0_page_cfg_4_rd_A	383421541	3575	0	0
bank1_info0_page_cfg_5_rd_A	383421541	3087	0	0
bank1_info0_page_cfg_6_rd_A	383421541	3111	0	0
bank1_info0_page_cfg_7_rd_A	383421541	2941	0	0
bank1_info0_page_cfg_8_rd_A	383421541	2740	0	0
bank1_info0_page_cfg_9_rd_A	383421541	3450	0	0
bank1_info0_regwen_0_rd_A	383421541	2044	0	0
bank1_info0_regwen_1_rd_A	383421541	1338	0	0
bank1_info0_regwen_2_rd_A	383421541	2004	0	0
bank1_info0_regwen_3_rd_A	383421541	1784	0	0
bank1_info0_regwen_4_rd_A	383421541	1937	0	0
bank1_info0_regwen_5_rd_A	383421541	1413	0	0
bank1_info0_regwen_6_rd_A	383421541	2007	0	0
bank1_info0_regwen_7_rd_A	383421541	1385	0	0
bank1_info0_regwen_8_rd_A	383421541	1925	0	0
bank1_info0_regwen_9_rd_A	383421541	1995	0	0
bank1_info1_page_cfg_rd_A	383421541	3040	0	0
bank1_info1_regwen_rd_A	383421541	1842	0	0
bank1_info2_page_cfg_0_rd_A	383421541	3249	0	0
bank1_info2_page_cfg_1_rd_A	383421541	3372	0	0
bank1_info2_regwen_0_rd_A	383421541	1803	0	0
bank1_info2_regwen_1_rd_A	383421541	1432	0	0
bank_cfg_regwen_rd_A	383421541	2162	0	0
default_region_rd_A	383421541	3009	0	0
exec_rd_A	383421541	1785	0	0
fifo_lvl_rd_A	383421541	2153	0	0
fifo_rst_rd_A	383421541	2039	0	0
hw_info_cfg_override_rd_A	383421541	1592	0	0
intr_enable_rd_A	383421541	2812	0	0
mp_region_0_rd_A	383421541	2050	0	0
mp_region_1_rd_A	383421541	2195	0	0
mp_region_2_rd_A	383421541	2142	0	0
mp_region_3_rd_A	383421541	2124	0	0
mp_region_4_rd_A	383421541	2061	0	0
mp_region_5_rd_A	383421541	1666	0	0
mp_region_6_rd_A	383421541	2124	0	0
mp_region_7_rd_A	383421541	2184	0	0
mp_region_cfg_0_rd_A	383421541	3213	0	0
mp_region_cfg_1_rd_A	383421541	3428	0	0
mp_region_cfg_2_rd_A	383421541	3705	0	0
mp_region_cfg_3_rd_A	383421541	3292	0	0
mp_region_cfg_4_rd_A	383421541	3342	0	0
mp_region_cfg_5_rd_A	383421541	3377	0	0
mp_region_cfg_6_rd_A	383421541	2953	0	0
mp_region_cfg_7_rd_A	383421541	3371	0	0
phy_alert_cfg_rd_A	383421541	744	0	0
region_cfg_regwen_0_rd_A	383421541	1928	0	0
region_cfg_regwen_1_rd_A	383421541	1460	0	0
region_cfg_regwen_2_rd_A	383421541	1853	0	0
region_cfg_regwen_3_rd_A	383421541	1855	0	0
region_cfg_regwen_4_rd_A	383421541	2003	0	0
region_cfg_regwen_5_rd_A	383421541	1533	0	0
region_cfg_regwen_6_rd_A	383421541	1866	0	0
region_cfg_regwen_7_rd_A	383421541	2022	0	0
scratch_rd_A	383421541	1489	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	4328	0	0
T56	3744	40	0	0
T193	4967	377	0	0
T194	2735	43	0	0
T195	5593	155	0	0
T196	7705	4	0	0
T197	4997	4	0	0
T215	23635	1	0	0
T228	2030	1	0	0
T229	4104	187	0	0
T230	8361	3	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2027	0	0
T54	20505	11	0	0
T287	6001	8	0	0
T288	3997	2	0	0
T289	4133	3	0	0
T290	87277	562	0	0
T291	6687	6	0	0
T292	21586	26	0	0
T293	9511	5	0	0
T294	9316	15	0	0
T295	88003	76	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3472	0	0
T54	20505	58	0	0
T287	6001	73	0	0
T288	3997	3	0	0
T289	4133	22	0	0
T290	87277	469	0	0
T291	6687	37	0	0
T292	21586	60	0	0
T293	9511	20	0	0
T294	9316	5	0	0
T296	5977	22	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3077	0	0
T54	20505	13	0	0
T287	6001	21	0	0
T288	3997	1	0	0
T289	4133	8	0	0
T290	87277	462	0	0
T291	6687	39	0	0
T292	21586	48	0	0
T293	9511	24	0	0
T294	9316	13	0	0
T296	5977	6	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3366	0	0
T54	20505	70	0	0
T287	6001	65	0	0
T288	3997	1	0	0
T289	4133	41	0	0
T290	87277	519	0	0
T291	6687	57	0	0
T292	21586	3	0	0
T293	9511	21	0	0
T294	9316	10	0	0
T296	5977	8	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3236	0	0
T54	20505	63	0	0
T287	6001	41	0	0
T288	3997	27	0	0
T289	4133	34	0	0
T290	87277	437	0	0
T291	6687	49	0	0
T292	21586	27	0	0
T293	9511	11	0	0
T295	88003	300	0	0
T296	5977	32	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3154	0	0
T54	20505	50	0	0
T287	6001	27	0	0
T288	3997	17	0	0
T290	87277	476	0	0
T291	6687	25	0	0
T292	21586	35	0	0
T293	9511	51	0	0
T294	9316	3	0	0
T295	88003	292	0	0
T296	5977	29	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3358	0	0
T54	20505	23	0	0
T287	6001	71	0	0
T288	3997	49	0	0
T289	4133	8	0	0
T290	87277	434	0	0
T291	6687	31	0	0
T292	21586	53	0	0
T293	9511	3	0	0
T294	9316	19	0	0
T296	5977	19	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2973	0	0
T54	20505	30	0	0
T287	6001	7	0	0
T288	3997	36	0	0
T289	4133	32	0	0
T290	87277	515	0	0
T292	21586	37	0	0
T293	9511	60	0	0
T294	9316	16	0	0
T295	88003	226	0	0
T296	5977	3	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3346	0	0
T54	20505	45	0	0
T287	6001	28	0	0
T288	3997	42	0	0
T290	87277	457	0	0
T291	6687	31	0	0
T292	21586	74	0	0
T293	9511	6	0	0
T294	9316	5	0	0
T295	88003	351	0	0
T296	5977	30	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3439	0	0
T54	20505	67	0	0
T287	6001	6	0	0
T288	3997	3	0	0
T289	4133	2	0	0
T290	87277	474	0	0
T291	6687	25	0	0
T292	21586	43	0	0
T293	9511	37	0	0
T294	9316	10	0	0
T296	5977	4	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2710	0	0
T54	20505	10	0	0
T287	6001	10	0	0
T288	3997	4	0	0
T289	4133	9	0	0
T291	6687	34	0	0
T292	21586	46	0	0
T293	9511	17	0	0
T294	9316	13	0	0
T295	88003	291	0	0
T296	5977	16	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1826	0	0
T54	20505	27	0	0
T287	6001	11	0	0
T288	3997	4	0	0
T289	4133	4	0	0
T290	87277	465	0	0
T291	6687	9	0	0
T292	21586	45	0	0
T293	9511	6	0	0
T294	9316	20	0	0
T295	88003	67	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1301	0	0
T54	20505	50	0	0
T287	6001	2	0	0
T288	3997	2	0	0
T289	4133	9	0	0
T291	6687	14	0	0
T292	21586	29	0	0
T293	9511	7	0	0
T295	88003	53	0	0
T296	5977	6	0	0
T297	21152	37	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1844	0	0
T54	20505	41	0	0
T287	6001	10	0	0
T288	3997	1	0	0
T289	4133	4	0	0
T290	87277	482	0	0
T291	6687	11	0	0
T292	21586	23	0	0
T293	9511	8	0	0
T294	9316	3	0	0
T296	5977	10	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1932	0	0
T54	20505	60	0	0
T287	6001	10	0	0
T289	4133	1	0	0
T290	87277	468	0	0
T291	6687	6	0	0
T292	21586	36	0	0
T293	9511	11	0	0
T294	9316	13	0	0
T295	88003	65	0	0
T296	5977	6	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1959	0	0
T54	20505	13	0	0
T287	6001	7	0	0
T288	3997	8	0	0
T289	4133	7	0	0
T290	87277	439	0	0
T291	6687	7	0	0
T292	21586	73	0	0
T294	9316	21	0	0
T295	88003	70	0	0
T297	21152	36	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1994	0	0
T54	20505	38	0	0
T287	6001	16	0	0
T288	3997	3	0	0
T289	4133	1	0	0
T290	87277	496	0	0
T291	6687	4	0	0
T292	21586	18	0	0
T293	9511	16	0	0
T294	9316	15	0	0
T296	5977	6	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1955	0	0
T54	20505	29	0	0
T287	6001	3	0	0
T289	4133	2	0	0
T290	87277	503	0	0
T291	6687	7	0	0
T292	21586	50	0	0
T294	9316	27	0	0
T295	88003	69	0	0
T296	5977	3	0	0
T297	21152	33	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1819	0	0
T54	20505	34	0	0
T287	6001	7	0	0
T288	3997	3	0	0
T289	4133	4	0	0
T290	87277	416	0	0
T291	6687	7	0	0
T292	21586	33	0	0
T293	9511	9	0	0
T294	9316	10	0	0
T295	88003	88	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2053	0	0
T54	20505	57	0	0
T287	6001	11	0	0
T288	3997	8	0	0
T289	4133	8	0	0
T290	87277	540	0	0
T291	6687	3	0	0
T292	21586	21	0	0
T293	9511	7	0	0
T294	9316	13	0	0
T295	88003	54	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1861	0	0
T54	20505	54	0	0
T287	6001	10	0	0
T288	3997	2	0	0
T290	87277	466	0	0
T291	6687	5	0	0
T292	21586	32	0	0
T293	9511	7	0	0
T294	9316	14	0	0
T295	88003	79	0	0
T297	21152	31	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3245	0	0
T54	20505	12	0	0
T287	6001	64	0	0
T289	4133	6	0	0
T290	87277	447	0	0
T291	6687	53	0	0
T292	21586	60	0	0
T293	9511	17	0	0
T294	9316	32	0	0
T295	88003	284	0	0
T296	5977	35	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1641	0	0
T54	20505	36	0	0
T287	6001	11	0	0
T288	3997	9	0	0
T289	4133	5	0	0
T291	6687	3	0	0
T292	21586	90	0	0
T293	9511	14	0	0
T295	88003	91	0	0
T297	21152	38	0	0
T298	9846	24	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3464	0	0
T54	20505	14	0	0
T287	6001	33	0	0
T288	3997	9	0	0
T289	4133	6	0	0
T290	87277	481	0	0
T291	6687	38	0	0
T292	21586	59	0	0
T293	9511	24	0	0
T294	9316	15	0	0
T296	5977	12	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2696	0	0
T54	20505	62	0	0
T287	6001	5	0	0
T288	3997	24	0	0
T289	4133	37	0	0
T291	6687	4	0	0
T292	21586	35	0	0
T293	9511	21	0	0
T294	9316	8	0	0
T295	88003	276	0	0
T296	5977	12	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1963	0	0
T54	20505	74	0	0
T287	6001	8	0	0
T288	3997	2	0	0
T289	4133	6	0	0
T290	87277	504	0	0
T291	6687	5	0	0
T292	21586	38	0	0
T293	9511	8	0	0
T294	9316	23	0	0
T296	5977	4	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2069	0	0
T54	20505	67	0	0
T287	6001	9	0	0
T288	3997	3	0	0
T289	4133	4	0	0
T290	87277	439	0	0
T291	6687	17	0	0
T292	21586	48	0	0
T293	9511	8	0	0
T294	9316	19	0	0
T296	5977	1	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3488	0	0
T54	20505	21	0	0
T287	6001	24	0	0
T289	4133	30	0	0
T290	87277	516	0	0
T291	6687	29	0	0
T292	21586	12	0	0
T294	9316	1	0	0
T295	88003	414	0	0
T296	5977	27	0	0
T297	21152	28	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3437	0	0
T54	20505	54	0	0
T287	6001	48	0	0
T288	3997	9	0	0
T289	4133	25	0	0
T290	87277	458	0	0
T292	21586	23	0	0
T293	9511	23	0	0
T294	9316	12	0	0
T295	88003	317	0	0
T296	5977	5	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2816	0	0
T54	20505	77	0	0
T287	6001	24	0	0
T288	3997	21	0	0
T289	4133	18	0	0
T291	6687	28	0	0
T292	21586	53	0	0
T293	9511	8	0	0
T294	9316	6	0	0
T295	88003	244	0	0
T296	5977	34	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3105	0	0
T54	20505	9	0	0
T287	6001	33	0	0
T288	3997	6	0	0
T289	4133	20	0	0
T290	87277	427	0	0
T291	6687	48	0	0
T292	21586	37	0	0
T293	9511	49	0	0
T294	9316	17	0	0
T296	5977	11	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3575	0	0
T54	20505	35	0	0
T287	6001	35	0	0
T288	3997	20	0	0
T289	4133	2	0	0
T290	87277	450	0	0
T291	6687	4	0	0
T292	21586	12	0	0
T293	9511	16	0	0
T294	9316	11	0	0
T296	5977	18	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3087	0	0
T54	20505	46	0	0
T287	6001	7	0	0
T288	3997	1	0	0
T289	4133	25	0	0
T290	87277	451	0	0
T291	6687	2	0	0
T292	21586	30	0	0
T293	9511	25	0	0
T294	9316	15	0	0
T296	5977	25	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3111	0	0
T54	20505	66	0	0
T287	6001	12	0	0
T288	3997	32	0	0
T289	4133	6	0	0
T290	87277	462	0	0
T291	6687	7	0	0
T292	21586	35	0	0
T293	9511	28	0	0
T294	9316	4	0	0
T296	5977	22	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2941	0	0
T54	20505	39	0	0
T287	6001	25	0	0
T288	3997	26	0	0
T289	4133	23	0	0
T290	87277	441	0	0
T291	6687	19	0	0
T292	21586	10	0	0
T293	9511	25	0	0
T294	9316	4	0	0
T296	5977	25	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2740	0	0
T54	20505	72	0	0
T287	6001	47	0	0
T288	3997	8	0	0
T289	4133	9	0	0
T291	6687	2	0	0
T292	21586	42	0	0
T293	9511	13	0	0
T294	9316	50	0	0
T295	88003	343	0	0
T296	5977	9	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3450	0	0
T54	20505	64	0	0
T287	6001	24	0	0
T288	3997	31	0	0
T289	4133	2	0	0
T290	87277	498	0	0
T291	6687	35	0	0
T292	21586	63	0	0
T293	9511	11	0	0
T294	9316	15	0	0
T295	88003	404	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2044	0	0
T54	20505	36	0	0
T287	6001	15	0	0
T288	3997	5	0	0
T289	4133	6	0	0
T290	87277	461	0	0
T291	6687	12	0	0
T292	21586	20	0	0
T293	9511	15	0	0
T294	9316	28	0	0
T296	5977	10	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1338	0	0
T54	20505	59	0	0
T287	6001	6	0	0
T288	3997	5	0	0
T291	6687	8	0	0
T292	21586	28	0	0
T293	9511	11	0	0
T294	9316	13	0	0
T295	88003	52	0	0
T296	5977	3	0	0
T297	21152	25	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2004	0	0
T54	20505	75	0	0
T287	6001	4	0	0
T288	3997	8	0	0
T289	4133	4	0	0
T290	87277	520	0	0
T291	6687	11	0	0
T292	21586	15	0	0
T293	9511	12	0	0
T294	9316	1	0	0
T296	5977	2	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1784	0	0
T54	20505	23	0	0
T287	6001	1	0	0
T288	3997	7	0	0
T289	4133	4	0	0
T290	87277	450	0	0
T291	6687	6	0	0
T292	21586	62	0	0
T293	9511	16	0	0
T294	9316	6	0	0
T296	5977	10	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1937	0	0
T54	20505	68	0	0
T287	6001	10	0	0
T289	4133	6	0	0
T290	87277	507	0	0
T291	6687	9	0	0
T292	21586	21	0	0
T293	9511	4	0	0
T294	9316	27	0	0
T295	88003	63	0	0
T296	5977	5	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1413	0	0
T54	20505	40	0	0
T287	6001	4	0	0
T289	4133	5	0	0
T291	6687	11	0	0
T292	21586	20	0	0
T293	9511	4	0	0
T294	9316	10	0	0
T295	88003	79	0	0
T296	5977	10	0	0
T297	21152	41	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2007	0	0
T54	20505	39	0	0
T287	6001	8	0	0
T288	3997	5	0	0
T289	4133	4	0	0
T290	87277	467	0	0
T291	6687	3	0	0
T292	21586	43	0	0
T293	9511	17	0	0
T294	9316	7	0	0
T295	88003	85	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1385	0	0
T54	20505	47	0	0
T287	6001	4	0	0
T288	3997	3	0	0
T289	4133	9	0	0
T291	6687	10	0	0
T292	21586	15	0	0
T293	9511	8	0	0
T294	9316	18	0	0
T295	88003	81	0	0
T296	5977	10	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1925	0	0
T54	20505	68	0	0
T287	6001	12	0	0
T288	3997	1	0	0
T290	87277	495	0	0
T292	21586	24	0	0
T294	9316	15	0	0
T295	88003	82	0	0
T297	21152	33	0	0
T298	9846	6	0	0
T299	80856	67	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1995	0	0
T54	20505	25	0	0
T287	6001	16	0	0
T288	3997	4	0	0
T289	4133	5	0	0
T290	87277	458	0	0
T291	6687	12	0	0
T292	21586	75	0	0
T293	9511	5	0	0
T294	9316	16	0	0
T295	88003	96	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3040	0	0
T54	20505	26	0	0
T287	6001	61	0	0
T288	3997	4	0	0
T289	4133	34	0	0
T291	6687	37	0	0
T292	21586	111	0	0
T293	9511	8	0	0
T294	9316	11	0	0
T295	88003	364	0	0
T296	5977	29	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1842	0	0
T54	20505	47	0	0
T287	6001	6	0	0
T288	3997	7	0	0
T289	4133	1	0	0
T290	87277	490	0	0
T291	6687	7	0	0
T292	21586	68	0	0
T293	9511	1	0	0
T294	9316	14	0	0
T296	5977	8	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3249	0	0
T54	20505	28	0	0
T287	6001	39	0	0
T288	3997	5	0	0
T289	4133	34	0	0
T290	87277	508	0	0
T291	6687	29	0	0
T292	21586	36	0	0
T293	9511	22	0	0
T295	88003	310	0	0
T296	5977	29	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3372	0	0
T54	20505	57	0	0
T287	6001	59	0	0
T288	3997	16	0	0
T289	4133	28	0	0
T290	87277	508	0	0
T291	6687	9	0	0
T292	21586	45	0	0
T293	9511	9	0	0
T294	9316	45	0	0
T296	5977	15	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1803	0	0
T54	20505	20	0	0
T287	6001	5	0	0
T288	3997	5	0	0
T289	4133	1	0	0
T290	87277	488	0	0
T291	6687	5	0	0
T292	21586	39	0	0
T293	9511	8	0	0
T294	9316	14	0	0
T296	5977	7	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1432	0	0
T54	20505	52	0	0
T288	3997	4	0	0
T289	4133	4	0	0
T291	6687	8	0	0
T292	21586	26	0	0
T293	9511	5	0	0
T295	88003	62	0	0
T297	21152	59	0	0
T298	9846	10	0	0
T300	4814	6	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2162	0	0
T54	20505	77	0	0
T287	6001	10	0	0
T288	3997	5	0	0
T289	4133	7	0	0
T290	87277	543	0	0
T291	6687	6	0	0
T292	21586	52	0	0
T293	9511	10	0	0
T294	9316	32	0	0
T295	88003	86	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3009	0	0
T54	20505	31	0	0
T287	6001	9	0	0
T288	3997	2	0	0
T289	4133	17	0	0
T290	87277	466	0	0
T291	6687	17	0	0
T292	21586	66	0	0
T293	9511	12	0	0
T294	9316	6	0	0
T296	5977	3	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1785	0	0
T54	20505	28	0	0
T287	6001	13	0	0
T288	3997	6	0	0
T289	4133	4	0	0
T290	87277	407	0	0
T291	6687	13	0	0
T292	21586	45	0	0
T293	9511	4	0	0
T294	9316	28	0	0
T295	88003	83	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2153	0	0
T54	20505	34	0	0
T287	6001	15	0	0
T288	3997	2	0	0
T290	87277	494	0	0
T291	6687	9	0	0
T292	21586	62	0	0
T293	9511	6	0	0
T294	9316	11	0	0
T295	88003	115	0	0
T297	21152	60	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2039	0	0
T54	20505	39	0	0
T287	6001	10	0	0
T288	3997	6	0	0
T289	4133	3	0	0
T290	87277	540	0	0
T291	6687	14	0	0
T292	21586	61	0	0
T293	9511	3	0	0
T294	9316	5	0	0
T296	5977	6	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1592	0	0
T54	20505	13	0	0
T287	6001	10	0	0
T288	3997	17	0	0
T289	4133	5	0	0
T291	6687	11	0	0
T292	21586	28	0	0
T293	9511	8	0	0
T294	9316	6	0	0
T295	88003	113	0	0
T297	21152	36	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2812	0	0
T54	20505	79	0	0
T287	6001	22	0	0
T289	4133	8	0	0
T290	87277	474	0	0
T291	6687	18	0	0
T292	21586	14	0	0
T293	9511	4	0	0
T294	9316	13	0	0
T295	88003	163	0	0
T296	5977	14	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2050	0	0
T54	20505	21	0	0
T287	6001	12	0	0
T288	3997	8	0	0
T289	4133	2	0	0
T290	87277	500	0	0
T291	6687	3	0	0
T292	21586	28	0	0
T294	9316	8	0	0
T295	88003	93	0	0
T296	5977	13	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2195	0	0
T54	20505	14	0	0
T287	6001	15	0	0
T288	3997	6	0	0
T289	4133	14	0	0
T290	87277	498	0	0
T291	6687	1	0	0
T292	21586	50	0	0
T293	9511	15	0	0
T294	9316	20	0	0
T295	88003	113	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2142	0	0
T54	20505	31	0	0
T287	6001	8	0	0
T288	3997	12	0	0
T289	4133	7	0	0
T290	87277	460	0	0
T291	6687	7	0	0
T292	21586	22	0	0
T293	9511	16	0	0
T294	9316	38	0	0
T296	5977	9	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2124	0	0
T54	20505	32	0	0
T287	6001	17	0	0
T288	3997	11	0	0
T289	4133	7	0	0
T290	87277	529	0	0
T291	6687	9	0	0
T292	21586	59	0	0
T293	9511	6	0	0
T295	88003	119	0	0
T296	5977	15	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2061	0	0
T54	20505	22	0	0
T287	6001	14	0	0
T288	3997	8	0	0
T289	4133	16	0	0
T290	87277	458	0	0
T291	6687	9	0	0
T292	21586	68	0	0
T293	9511	9	0	0
T294	9316	4	0	0
T296	5977	6	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1666	0	0
T54	20505	39	0	0
T287	6001	5	0	0
T289	4133	10	0	0
T291	6687	10	0	0
T292	21586	21	0	0
T294	9316	14	0	0
T295	88003	144	0	0
T296	5977	11	0	0
T297	21152	25	0	0
T301	4504	4	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2124	0	0
T54	20505	37	0	0
T287	6001	13	0	0
T288	3997	3	0	0
T289	4133	9	0	0
T290	87277	500	0	0
T291	6687	19	0	0
T292	21586	33	0	0
T293	9511	15	0	0
T294	9316	5	0	0
T296	5977	9	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2184	0	0
T54	20505	9	0	0
T287	6001	4	0	0
T288	3997	8	0	0
T289	4133	2	0	0
T290	87277	528	0	0
T291	6687	5	0	0
T292	21586	58	0	0
T293	9511	11	0	0
T294	9316	14	0	0
T296	5977	2	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3213	0	0
T54	20505	21	0	0
T287	6001	34	0	0
T288	3997	9	0	0
T289	4133	40	0	0
T290	87277	468	0	0
T291	6687	12	0	0
T292	21586	54	0	0
T293	9511	56	0	0
T294	9316	10	0	0
T296	5977	63	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3428	0	0
T54	20505	52	0	0
T287	6001	29	0	0
T288	3997	6	0	0
T289	4133	29	0	0
T290	87277	503	0	0
T291	6687	50	0	0
T292	21586	20	0	0
T293	9511	22	0	0
T294	9316	16	0	0
T296	5977	32	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3705	0	0
T54	20505	63	0	0
T287	6001	54	0	0
T288	3997	6	0	0
T289	4133	19	0	0
T290	87277	537	0	0
T291	6687	20	0	0
T292	21586	73	0	0
T293	9511	44	0	0
T294	9316	24	0	0
T296	5977	20	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3292	0	0
T54	20505	11	0	0
T287	6001	14	0	0
T288	3997	44	0	0
T289	4133	3	0	0
T290	87277	509	0	0
T291	6687	36	0	0
T292	21586	57	0	0
T293	9511	7	0	0
T294	9316	18	0	0
T296	5977	11	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3342	0	0
T54	20505	43	0	0
T287	6001	54	0	0
T288	3997	6	0	0
T289	4133	20	0	0
T290	87277	592	0	0
T291	6687	47	0	0
T292	21586	56	0	0
T293	9511	29	0	0
T294	9316	18	0	0
T296	5977	15	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3377	0	0
T54	20505	83	0	0
T287	6001	39	0	0
T288	3997	29	0	0
T289	4133	31	0	0
T290	87277	485	0	0
T291	6687	34	0	0
T292	21586	43	0	0
T293	9511	30	0	0
T295	88003	251	0	0
T296	5977	6	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2953	0	0
T54	20505	18	0	0
T287	6001	29	0	0
T288	3997	27	0	0
T289	4133	36	0	0
T291	6687	41	0	0
T292	21586	31	0	0
T293	9511	11	0	0
T294	9316	5	0	0
T295	88003	286	0	0
T296	5977	20	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	3371	0	0
T54	20505	36	0	0
T287	6001	3	0	0
T288	3997	37	0	0
T289	4133	28	0	0
T290	87277	446	0	0
T291	6687	10	0	0
T292	21586	48	0	0
T293	9511	39	0	0
T294	9316	11	0	0
T295	88003	406	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	744	0	0
T54	20505	10	0	0
T264	78700	7	0	0
T290	87277	463	0	0
T292	21586	33	0	0
T293	9511	4	0	0
T294	9316	14	0	0
T297	21152	18	0	0
T298	9846	27	0	0
T301	4504	8	0	0
T302	19157	6	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1928	0	0
T54	20505	45	0	0
T287	6001	12	0	0
T288	3997	4	0	0
T289	4133	1	0	0
T290	87277	467	0	0
T291	6687	12	0	0
T292	21586	18	0	0
T293	9511	21	0	0
T294	9316	3	0	0
T296	5977	2	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1460	0	0
T54	20505	60	0	0
T287	6001	6	0	0
T288	3997	4	0	0
T289	4133	3	0	0
T291	6687	8	0	0
T292	21586	75	0	0
T293	9511	6	0	0
T295	88003	68	0	0
T296	5977	7	0	0
T297	21152	38	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1853	0	0
T54	20505	21	0	0
T287	6001	10	0	0
T288	3997	3	0	0
T289	4133	7	0	0
T290	87277	510	0	0
T291	6687	3	0	0
T292	21586	43	0	0
T293	9511	9	0	0
T294	9316	21	0	0
T296	5977	8	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1855	0	0
T54	20505	10	0	0
T287	6001	8	0	0
T288	3997	1	0	0
T289	4133	7	0	0
T290	87277	470	0	0
T291	6687	10	0	0
T292	21586	50	0	0
T293	9511	16	0	0
T294	9316	16	0	0
T295	88003	67	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2003	0	0
T54	20505	84	0	0
T287	6001	3	0	0
T288	3997	4	0	0
T289	4133	7	0	0
T290	87277	430	0	0
T291	6687	3	0	0
T292	21586	31	0	0
T293	9511	16	0	0
T294	9316	10	0	0
T296	5977	5	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1533	0	0
T54	20505	48	0	0
T287	6001	14	0	0
T288	3997	5	0	0
T289	4133	5	0	0
T291	6687	5	0	0
T292	21586	46	0	0
T293	9511	7	0	0
T294	9316	16	0	0
T295	88003	73	0	0
T296	5977	1	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1866	0	0
T54	20505	44	0	0
T287	6001	9	0	0
T288	3997	3	0	0
T289	4133	4	0	0
T290	87277	488	0	0
T291	6687	13	0	0
T292	21586	18	0	0
T293	9511	1	0	0
T294	9316	11	0	0
T295	88003	74	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	2022	0	0
T54	20505	51	0	0
T287	6001	6	0	0
T288	3997	8	0	0
T289	4133	9	0	0
T290	87277	541	0	0
T291	6687	13	0	0
T292	21586	64	0	0
T293	9511	15	0	0
T294	9316	16	0	0
T296	5977	10	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383421541	1489	0	0
T54	20505	14	0	0
T287	6001	14	0	0
T288	3997	2	0	0
T289	4133	1	0	0
T291	6687	9	0	0
T292	21586	38	0	0
T293	9511	16	0	0
T294	9316	17	0	0
T295	88003	78	0	0
T296	5977	6	0	0