Line Coverage for Module :
prim_fifo_sync ( parameter Width=109,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Line Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
ALWAYS | 157 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
154 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Line Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
ALWAYS | 157 | 2 | 2 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
CONT_ASSIGN | 173 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
154 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
|
|
|
MISSING_ELSE |
172 |
1 |
1 |
173 |
1 |
1 |
180 |
1 |
1 |
Line Coverage for Module :
prim_fifo_sync ( parameter Width=39,Pass=1,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
CONT_ASSIGN | 173 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
172 |
1 |
1 |
173 |
1 |
1 |
180 |
1 |
1 |
Line Coverage for Module :
prim_fifo_sync ( parameter Width=39,Pass=1,Depth=16,OutputZeroIfEmpty=1,Secure=0,DepthW=5,gen_normal_fifo.PTRV_W=4,gen_normal_fifo.PTR_WIDTH=5 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
CONT_ASSIGN | 173 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
172 |
1 |
1 |
173 |
1 |
1 |
180 |
1 |
1 |
Line Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=75,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Line Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
CONT_ASSIGN | 173 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
172 |
1 |
1 |
173 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=39,Pass=1,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 34 | 30 | 88.24 |
Logical | 34 | 30 | 88.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T16 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T1,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T4,T16 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T11,T32 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T6 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T16 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 172
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 172
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T6 |
LINE 173
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=75,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 26 | 21 | 80.77 |
Logical | 26 | 21 | 80.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T33,T122 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T33,T122 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T33,T122 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 26 | 21 | 80.77 |
Logical | 26 | 21 | 80.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 23 | 18 | 78.26 |
Logical | 23 | 18 | 78.26 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | T1,T2,T3 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 26 | 22 | 84.62 |
Logical | 26 | 22 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T16 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T4,T16 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T16 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 34 | 30 | 88.24 |
Logical | 34 | 30 | 88.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T27,T28 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T33,T122 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T33,T122 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T67,T68,T33 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T5,T6,T16 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T27,T28 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T4,T5 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T27,T28 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 172
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 172
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T67,T68,T33 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 173
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T27,T28 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 26 | 21 | 80.77 |
Logical | 26 | 21 | 80.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 26 | 18 | 69.23 |
Logical | 26 | 18 | 69.23 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T4,T5 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 34 | 29 | 85.29 |
Logical | 34 | 29 | 85.29 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T46,T49 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T44,T123,T124 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T44,T123,T124 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T4,T17,T18 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T44,T46,T49 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T46,T49 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 172
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
LINE 172
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T44,T46,T49 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T6 |
LINE 173
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T44,T123,T124 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=39,Pass=1,Depth=16,OutputZeroIfEmpty=1,Secure=0,DepthW=5,gen_normal_fifo.PTRV_W=4,gen_normal_fifo.PTR_WIDTH=5 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 34 | 29 | 85.29 |
Logical | 34 | 29 | 85.29 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (5'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((5'(gen_normal_fifo.wptr_value) - 5'(gen_normal_fifo.rptr_value))) : (((5'(Depth) - 5'(gen_normal_fifo.rptr_value)) + 5'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T11,T19,T24 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((5'(gen_normal_fifo.wptr_value) - 5'(gen_normal_fifo.rptr_value))) : (((5'(Depth) - 5'(gen_normal_fifo.rptr_value)) + 5'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T3,T4,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T11,T19,T24 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T4,T5 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T11,T19,T24 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 172
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 172
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T5 |
LINE 173
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 26 | 21 | 80.77 |
Logical | 26 | 21 | 80.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T5,T6 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 26 | 19 | 73.08 |
Logical | 26 | 19 | 73.08 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T6,T16 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 26 | 21 | 80.77 |
Logical | 26 | 21 | 80.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T17 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T17 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T17 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=75,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
157 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T3,T4 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=39,Pass=1,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=39,Pass=1,Depth=16,OutputZeroIfEmpty=1,Secure=0,DepthW=5,gen_normal_fifo.PTRV_W=4,gen_normal_fifo.PTR_WIDTH=5 + Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
172 |
2 |
2 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
157 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T4,T16 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
890135157 |
0 |
0 |
T1 |
433641 |
42975 |
0 |
0 |
T2 |
41509 |
898 |
0 |
0 |
T3 |
25897 |
288 |
0 |
0 |
T4 |
5455647 |
202217 |
0 |
0 |
T5 |
24167673 |
1930789 |
0 |
0 |
T6 |
79632 |
1200 |
0 |
0 |
T7 |
1089564 |
116949 |
0 |
0 |
T11 |
3518928 |
3110878 |
0 |
0 |
T16 |
59472 |
2096 |
0 |
0 |
T17 |
2775024 |
268416 |
0 |
0 |
T18 |
0 |
153078 |
0 |
0 |
T19 |
6706449 |
1187460 |
0 |
0 |
T27 |
5341290 |
831471 |
0 |
0 |
T28 |
4689615 |
655355 |
0 |
0 |
T38 |
187989 |
18909 |
0 |
0 |
T47 |
0 |
17498 |
0 |
0 |
T48 |
0 |
197 |
0 |
0 |
T54 |
0 |
262144 |
0 |
0 |
T65 |
1260 |
0 |
0 |
0 |
T67 |
0 |
8 |
0 |
0 |
T69 |
0 |
16619 |
0 |
0 |
T118 |
0 |
18 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1000710 |
998280 |
0 |
0 |
T2 |
95790 |
76170 |
0 |
0 |
T3 |
40890 |
38250 |
0 |
0 |
T4 |
6061830 |
6059820 |
0 |
0 |
T5 |
26852970 |
26849130 |
0 |
0 |
T6 |
85320 |
80550 |
0 |
0 |
T7 |
1167390 |
1165440 |
0 |
0 |
T11 |
3770280 |
3770190 |
0 |
0 |
T16 |
63720 |
59940 |
0 |
0 |
T17 |
2973240 |
2969250 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1000710 |
998280 |
0 |
0 |
T2 |
95790 |
76170 |
0 |
0 |
T3 |
40890 |
38250 |
0 |
0 |
T4 |
6061830 |
6059820 |
0 |
0 |
T5 |
26852970 |
26849130 |
0 |
0 |
T6 |
85320 |
80550 |
0 |
0 |
T7 |
1167390 |
1165440 |
0 |
0 |
T11 |
3770280 |
3770190 |
0 |
0 |
T16 |
63720 |
59940 |
0 |
0 |
T17 |
2973240 |
2969250 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1000710 |
998280 |
0 |
0 |
T2 |
95790 |
76170 |
0 |
0 |
T3 |
40890 |
38250 |
0 |
0 |
T4 |
6061830 |
6059820 |
0 |
0 |
T5 |
26852970 |
26849130 |
0 |
0 |
T6 |
85320 |
80550 |
0 |
0 |
T7 |
1167390 |
1165440 |
0 |
0 |
T11 |
3770280 |
3770190 |
0 |
0 |
T16 |
63720 |
59940 |
0 |
0 |
T17 |
2973240 |
2969250 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
731306187 |
0 |
0 |
T1 |
233499 |
42975 |
0 |
0 |
T2 |
22351 |
898 |
0 |
0 |
T3 |
14993 |
288 |
0 |
0 |
T4 |
3839159 |
202217 |
0 |
0 |
T5 |
17006881 |
1930789 |
0 |
0 |
T6 |
56880 |
1200 |
0 |
0 |
T7 |
778260 |
116949 |
0 |
0 |
T11 |
2513520 |
3110878 |
0 |
0 |
T16 |
42480 |
2096 |
0 |
0 |
T17 |
1982160 |
268416 |
0 |
0 |
T18 |
0 |
153078 |
0 |
0 |
T19 |
6706449 |
1187460 |
0 |
0 |
T27 |
4629118 |
831471 |
0 |
0 |
T28 |
4064333 |
655355 |
0 |
0 |
T38 |
187989 |
18909 |
0 |
0 |
T47 |
0 |
17498 |
0 |
0 |
T48 |
0 |
197 |
0 |
0 |
T54 |
0 |
262144 |
0 |
0 |
T65 |
1260 |
0 |
0 |
0 |
T67 |
0 |
8 |
0 |
0 |
T69 |
0 |
16619 |
0 |
0 |
T118 |
0 |
18 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10224 |
10224 |
0 |
0 |
T1 |
8 |
8 |
0 |
0 |
T2 |
8 |
8 |
0 |
0 |
T3 |
8 |
8 |
0 |
0 |
T4 |
8 |
8 |
0 |
0 |
T5 |
8 |
8 |
0 |
0 |
T6 |
8 |
8 |
0 |
0 |
T7 |
8 |
8 |
0 |
0 |
T11 |
8 |
8 |
0 |
0 |
T16 |
8 |
8 |
0 |
0 |
T17 |
8 |
8 |
0 |
0 |