Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
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Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 0 2 100.00 100 1 1 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0



Group Instance : tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 1 13 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0



Group Instance : tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 1 13 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29017364 1 T1 8455 T2 242 T3 67098
auto[1] 5429185 1 T1 11264 T3 123 T4 71



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 34446359 1 T1 19719 T2 242 T3 67221
values[1] 24 1 T56 2 T177 1 T216 1
values[2] 5 1 T56 2 T216 1 T334 1
values[3] 92 1 T56 3 T177 8 T216 7



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 34446355 1 T1 19719 T2 242 T3 67221
values[1] 21 1 T56 1 T177 1 T216 5
values[2] 6 1 T334 2 T335 1 T336 1
values[3] 95 1 T56 8 T177 8 T216 7



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 34446259 1 T1 19719 T2 242 T3 67221
auto[TlIntgErrCmd] 96 1 T56 6 T177 6 T216 3
auto[TlIntgErrData] 100 1 T56 10 T177 9 T216 4
auto[TlIntgErrBoth] 94 1 T56 4 T177 5 T216 13


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[0]] 0 0 - - - - - -
auto[1] 4500334 0 T3 170 T5 10 T6 15999



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4500163 1 T3 170 T5 10 T6 15999
values[1] 22 1 T56 2 T177 3 T216 1
values[2] 5 1 T56 1 T270 2 T336 1
values[3] 90 1 T56 7 T177 4 T216 6



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4500157 1 T3 170 T5 10 T6 15999
values[1] 25 1 T56 1 T216 3 T334 3
values[2] 2 1 T293 1 T336 1 - -
values[3] 84 1 T56 7 T177 5 T216 7



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 4500067 1 T3 170 T5 10 T6 15999
auto[TlIntgErrCmd] 90 1 T56 6 T177 7 T216 7
auto[TlIntgErrData] 96 1 T56 6 T177 8 T216 9
auto[TlIntgErrBoth] 81 1 T56 6 T177 2 T216 4


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 78252 0 T56 1290 T176 138 T177 1247



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 78058 1 T56 1273 T176 138 T177 1235
values[1] 19 1 T56 1 T216 4 T217 1
values[2] 3 1 T270 1 T336 1 T337 1
values[3] 98 1 T56 9 T177 6 T216 5



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 78056 1 T56 1279 T176 138 T177 1233
values[1] 19 1 T56 1 T177 2 T216 2
values[2] 6 1 T217 1 T270 1 T263 1
values[3] 108 1 T56 4 T177 9 T216 8



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 77962 1 T56 1270 T176 138 T177 1227
auto[TlIntgErrCmd] 94 1 T56 9 T177 6 T216 5
auto[TlIntgErrData] 96 1 T56 3 T177 8 T216 5
auto[TlIntgErrBoth] 100 1 T56 8 T177 6 T216 10

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