Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26353985	1		T1	7334		T2	192		T3	66529
full_word	8092564	1		T1	12385		T2	50		T3	692

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34446259	1		T1	19719		T2	242		T3	67221
auto[TlIntgErrCmd]	96	1		T56	6		T177	6		T216	3
auto[TlIntgErrData]	100	1		T56	10		T177	9		T216	4
auto[TlIntgErrBoth]	94	1		T56	4		T177	5		T216	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29863140	1		T1	12362		T2	191		T3	66538
auto[1]	4583409	1		T1	7357		T2	51		T3	683

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25631571	1		T1	7029		T2	189		T3	66488
auto[TlIntgErrNone]	partial	auto[1]	722147	1		T1	305		T2	3		T3	41
auto[TlIntgErrNone]	full_word	auto[0]	4231420	1		T1	5333		T2	2		T3	50
auto[TlIntgErrNone]	full_word	auto[1]	3861121	1		T1	7052		T2	48		T3	642
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T56	2		T177	4		T216	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T56	3		T177	2		T216	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T334	1		T338	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T56	1		T335	1		T339	1
auto[TlIntgErrData]	partial	auto[0]	53	1		T56	4		T177	3		T216	3
auto[TlIntgErrData]	partial	auto[1]	39	1		T56	4		T177	6		T216	1
auto[TlIntgErrData]	full_word	auto[0]	6	1		T56	1		T334	1		T270	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T56	1		T340	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T56	4		T177	2		T216	5
auto[TlIntgErrBoth]	partial	auto[1]	43	1		T177	3		T216	5		T217	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T216	1		T263	1		T337	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T216	2		T339	1		T341	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21655	1		T56	15		T177	16		T178	87
full_word	4478679	1		T3	170		T5	10		T6	15999

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4500067	1		T3	170		T5	10		T6	15999
auto[TlIntgErrCmd]	90	1		T56	6		T177	7		T216	7
auto[TlIntgErrData]	96	1		T56	6		T177	8		T216	9
auto[TlIntgErrBoth]	81	1		T56	6		T177	2		T216	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4472896	1		T3	170		T5	10		T6	15999
auto[1]	27438	1		T56	8		T177	11		T178	119

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1415	1		T178	6		T214	4		T215	11
auto[TlIntgErrNone]	partial	auto[1]	20007	1		T178	81		T214	83		T215	407
auto[TlIntgErrNone]	full_word	auto[0]	4471366	1		T3	170		T5	10		T6	15999
auto[TlIntgErrNone]	full_word	auto[1]	7279	1		T178	38		T214	50		T215	164
auto[TlIntgErrCmd]	partial	auto[0]	22	1		T56	3		T177	1		T217	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T56	2		T177	6		T216	5
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T216	2		T334	1		T293	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T56	1		T334	1		T293	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T56	3		T177	2		T216	5
auto[TlIntgErrData]	partial	auto[1]	39	1		T56	3		T177	5		T216	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T177	1		T216	1		T334	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T334	1		T270	1		T336	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T56	3		T177	2		T216	3
auto[TlIntgErrBoth]	partial	auto[1]	39	1		T56	1		T216	1		T217	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T56	1		T342	1		T337	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T56	1		T270	1		T336	1