Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1773796928	1770544208	0	0
CheckNGreaterZero_A	4248	4248	0	0
GntImpliesReady_A	1773796928	460905352	0	0
GntImpliesValid_A	1773796928	460905352	0	0
GrantKnown_A	1773796928	1770544208	0	0
IdxKnown_A	1773796928	1770544208	0	0
IndexIsCorrect_A	1773796928	460905352	0	0
NoReadyValidNoGrant_A	1773796928	179325051	0	0
Priority_A	1773796928	485670989	0	0
ReadyAndValidImplyGrant_A	1773796928	460905352	0	0
ReqAndReadyImplyGrant_A	1773796928	460905352	0	0
ReqImpliesValid_A	1773796928	485670989	0	0
ValidKnown_A	1773796928	1770544208	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	1770544208	0	0
T1	850176	849892	0	0
T2	3232	2920	0	0
T3	547208	546888	0	0
T4	8712	8080	0	0
T5	7024	6672	0	0
T6	419612	419160	0	0
T16	8840	8524	0	0
T17	3244632	3244252	0	0
T18	616600	616564	0	0
T19	14696	14152	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4248	4248	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	460905352	0	0
T1	425088	53530	0	0
T2	1616	584	0	0
T3	547208	267372	0	0
T4	8712	136	0	0
T5	7024	84	0	0
T6	419612	61930	0	0
T7	0	31026	0	0
T11	2736	466	0	0
T16	8840	64	0	0
T17	3244632	1485388	0	0
T18	616600	2944926	0	0
T19	14696	2552	0	0
T20	0	874	0	0
T22	0	660	0	0
T39	0	22026	0	0
T48	2912	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	460905352	0	0
T1	425088	53530	0	0
T2	1616	584	0	0
T3	547208	267372	0	0
T4	8712	136	0	0
T5	7024	84	0	0
T6	419612	61930	0	0
T7	0	31026	0	0
T11	2736	466	0	0
T16	8840	64	0	0
T17	3244632	1485388	0	0
T18	616600	2944926	0	0
T19	14696	2552	0	0
T20	0	874	0	0
T22	0	660	0	0
T39	0	22026	0	0
T48	2912	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	1770544208	0	0
T1	850176	849892	0	0
T2	3232	2920	0	0
T3	547208	546888	0	0
T4	8712	8080	0	0
T5	7024	6672	0	0
T6	419612	419160	0	0
T16	8840	8524	0	0
T17	3244632	3244252	0	0
T18	616600	616564	0	0
T19	14696	14152	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	1770544208	0	0
T1	850176	849892	0	0
T2	3232	2920	0	0
T3	547208	546888	0	0
T4	8712	8080	0	0
T5	7024	6672	0	0
T6	419612	419160	0	0
T16	8840	8524	0	0
T17	3244632	3244252	0	0
T18	616600	616564	0	0
T19	14696	14152	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	460905352	0	0
T1	425088	53530	0	0
T2	1616	584	0	0
T3	547208	267372	0	0
T4	8712	136	0	0
T5	7024	84	0	0
T6	419612	61930	0	0
T7	0	31026	0	0
T11	2736	466	0	0
T16	8840	64	0	0
T17	3244632	1485388	0	0
T18	616600	2944926	0	0
T19	14696	2552	0	0
T20	0	874	0	0
T22	0	660	0	0
T39	0	22026	0	0
T48	2912	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	179325051	0	0
T1	425088	2688	0	0
T2	1616	256	0	0
T3	547208	856	0	0
T4	8712	512	0	0
T5	7024	286	0	0
T6	419612	161584	0	0
T7	0	78898	0	0
T11	2736	0	0	0
T16	8840	256	0	0
T17	3244632	11610	0	0
T18	616600	13084	0	0
T19	14696	686	0	0
T21	0	3482	0	0
T22	0	992	0	0
T34	0	1021498	0	0
T39	0	26898	0	0
T48	2912	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	485670989	0	0
T1	425088	53530	0	0
T2	1616	584	0	0
T3	547208	267590	0	0
T4	8712	136	0	0
T5	7024	84	0	0
T6	419612	65544	0	0
T7	0	33296	0	0
T11	2736	466	0	0
T16	8840	64	0	0
T17	3244632	1485388	0	0
T18	616600	2944926	0	0
T19	14696	2552	0	0
T20	0	874	0	0
T22	0	660	0	0
T39	0	28950	0	0
T48	2912	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	460905352	0	0
T1	425088	53530	0	0
T2	1616	584	0	0
T3	547208	267372	0	0
T4	8712	136	0	0
T5	7024	84	0	0
T6	419612	61930	0	0
T7	0	31026	0	0
T11	2736	466	0	0
T16	8840	64	0	0
T17	3244632	1485388	0	0
T18	616600	2944926	0	0
T19	14696	2552	0	0
T20	0	874	0	0
T22	0	660	0	0
T39	0	22026	0	0
T48	2912	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	460905352	0	0
T1	425088	53530	0	0
T2	1616	584	0	0
T3	547208	267372	0	0
T4	8712	136	0	0
T5	7024	84	0	0
T6	419612	61930	0	0
T7	0	31026	0	0
T11	2736	466	0	0
T16	8840	64	0	0
T17	3244632	1485388	0	0
T18	616600	2944926	0	0
T19	14696	2552	0	0
T20	0	874	0	0
T22	0	660	0	0
T39	0	22026	0	0
T48	2912	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	485670989	0	0
T1	425088	53530	0	0
T2	1616	584	0	0
T3	547208	267590	0	0
T4	8712	136	0	0
T5	7024	84	0	0
T6	419612	65544	0	0
T7	0	33296	0	0
T11	2736	466	0	0
T16	8840	64	0	0
T17	3244632	1485388	0	0
T18	616600	2944926	0	0
T19	14696	2552	0	0
T20	0	874	0	0
T22	0	660	0	0
T39	0	28950	0	0
T48	2912	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1773796928	1770544208	0	0
T1	850176	849892	0	0
T2	3232	2920	0	0
T3	547208	546888	0	0
T4	8712	8080	0	0
T5	7024	6672	0	0
T6	419612	419160	0	0
T16	8840	8524	0	0
T17	3244632	3244252	0	0
T18	616600	616564	0	0
T19	14696	14152	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443449232	442636052	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	443449232	129798979	0	0
GntImpliesValid_A	443449232	129798979	0	0
GrantKnown_A	443449232	442636052	0	0
IdxKnown_A	443449232	442636052	0	0
IndexIsCorrect_A	443449232	129798979	0	0
NoReadyValidNoGrant_A	443449232	47456733	0	0
Priority_A	443449232	136019081	0	0
ReadyAndValidImplyGrant_A	443449232	129798979	0	0
ReqAndReadyImplyGrant_A	443449232	129798979	0	0
ReqImpliesValid_A	443449232	136019081	0	0
ValidKnown_A	443449232	442636052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	129798979	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1799	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	16506	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	129798979	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1799	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	16506	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	129798979	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1799	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	16506	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	47456733	0	0
T1	212544	1344	0	0
T2	808	128	0	0
T3	136802	285	0	0
T4	2178	256	0	0
T5	1756	143	0	0
T6	104903	43495	0	0
T16	2210	128	0	0
T17	811158	3315	0	0
T18	154150	3332	0	0
T19	3674	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	136019081	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1908	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	17367	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	129798979	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1799	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	16506	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	129798979	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1799	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	16506	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	136019081	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1908	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	17367	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443449232	442636052	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	443449232	129670145	0	0
GntImpliesValid_A	443449232	129670145	0	0
GrantKnown_A	443449232	442636052	0	0
IdxKnown_A	443449232	442636052	0	0
IndexIsCorrect_A	443449232	129670145	0	0
NoReadyValidNoGrant_A	443449232	47456736	0	0
Priority_A	443449232	135890244	0	0
ReadyAndValidImplyGrant_A	443449232	129670145	0	0
ReqAndReadyImplyGrant_A	443449232	129670145	0	0
ReqImpliesValid_A	443449232	135890244	0	0
ValidKnown_A	443449232	442636052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	129670145	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1799	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	16506	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	129670145	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1799	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	16506	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	129670145	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1799	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	16506	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	47456736	0	0
T1	212544	1344	0	0
T2	808	128	0	0
T3	136802	285	0	0
T4	2178	256	0	0
T5	1756	143	0	0
T6	104903	43495	0	0
T16	2210	128	0	0
T17	811158	3315	0	0
T18	154150	3332	0	0
T19	3674	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	135890244	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1908	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	17367	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	129670145	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1799	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	16506	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	129670145	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1799	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	16506	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	135890244	0	0
T1	212544	26765	0	0
T2	808	292	0	0
T3	136802	1908	0	0
T4	2178	68	0	0
T5	1756	42	0	0
T6	104903	17367	0	0
T16	2210	32	0	0
T17	811158	62681	0	0
T18	154150	806013	0	0
T19	3674	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T17,T6
1	0	Covered	T3,T6,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T39
1	0	Covered	T3,T17,T6
1	1	Covered	T3,T6,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T19
1	1	Covered	T3,T17,T6

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T39
1	1	Covered	T3,T17,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443449232	442636052	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	443449232	100718114	0	0
GntImpliesValid_A	443449232	100718114	0	0
GrantKnown_A	443449232	442636052	0	0
IdxKnown_A	443449232	442636052	0	0
IndexIsCorrect_A	443449232	100718114	0	0
NoReadyValidNoGrant_A	443449232	42205791	0	0
Priority_A	443449232	106880832	0	0
ReadyAndValidImplyGrant_A	443449232	100718114	0	0
ReqAndReadyImplyGrant_A	443449232	100718114	0	0
ReqImpliesValid_A	443449232	106880832	0	0
ValidKnown_A	443449232	442636052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	100718114	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	14459	0	0
T7	0	15513	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	11013	0	0
T48	1456	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	100718114	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	14459	0	0
T7	0	15513	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	11013	0	0
T48	1456	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	100718114	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	14459	0	0
T7	0	15513	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	11013	0	0
T48	1456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	42205791	0	0
T3	136802	143	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	37297	0	0
T7	0	39449	0	0
T11	1368	0	0	0
T16	2210	0	0	0
T17	811158	2490	0	0
T18	154150	3210	0	0
T19	3674	87	0	0
T21	0	1741	0	0
T22	0	496	0	0
T34	0	510749	0	0
T39	0	13449	0	0
T48	1456	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	106880832	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	15405	0	0
T7	0	16648	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	14475	0	0
T48	1456	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	100718114	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	14459	0	0
T7	0	15513	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	11013	0	0
T48	1456	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	100718114	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	14459	0	0
T7	0	15513	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	11013	0	0
T48	1456	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	106880832	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	15405	0	0
T7	0	16648	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	14475	0	0
T48	1456	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T17,T6
1	0	Covered	T3,T6,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T39
1	0	Covered	T3,T17,T6
1	1	Covered	T3,T6,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T19
1	1	Covered	T3,T17,T6

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T39
1	1	Covered	T3,T17,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443449232	442636052	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	443449232	100718114	0	0
GntImpliesValid_A	443449232	100718114	0	0
GrantKnown_A	443449232	442636052	0	0
IdxKnown_A	443449232	442636052	0	0
IndexIsCorrect_A	443449232	100718114	0	0
NoReadyValidNoGrant_A	443449232	42205791	0	0
Priority_A	443449232	106880832	0	0
ReadyAndValidImplyGrant_A	443449232	100718114	0	0
ReqAndReadyImplyGrant_A	443449232	100718114	0	0
ReqImpliesValid_A	443449232	106880832	0	0
ValidKnown_A	443449232	442636052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	100718114	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	14459	0	0
T7	0	15513	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	11013	0	0
T48	1456	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	100718114	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	14459	0	0
T7	0	15513	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	11013	0	0
T48	1456	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	100718114	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	14459	0	0
T7	0	15513	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	11013	0	0
T48	1456	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	42205791	0	0
T3	136802	143	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	37297	0	0
T7	0	39449	0	0
T11	1368	0	0	0
T16	2210	0	0	0
T17	811158	2490	0	0
T18	154150	3210	0	0
T19	3674	87	0	0
T21	0	1741	0	0
T22	0	496	0	0
T34	0	510749	0	0
T39	0	13449	0	0
T48	1456	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	106880832	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	15405	0	0
T7	0	16648	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	14475	0	0
T48	1456	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	100718114	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	14459	0	0
T7	0	15513	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	11013	0	0
T48	1456	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	100718114	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	14459	0	0
T7	0	15513	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	11013	0	0
T48	1456	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	106880832	0	0
T3	136802	131887	0	0
T4	2178	0	0	0
T5	1756	0	0	0
T6	104903	15405	0	0
T7	0	16648	0	0
T11	1368	233	0	0
T16	2210	0	0	0
T17	811158	680013	0	0
T18	154150	666450	0	0
T19	3674	1212	0	0
T20	0	437	0	0
T22	0	330	0	0
T39	0	14475	0	0
T48	1456	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443449232	442636052	0	0
T1	212544	212473	0	0
T2	808	730	0	0
T3	136802	136722	0	0
T4	2178	2020	0	0
T5	1756	1668	0	0
T6	104903	104790	0	0
T16	2210	2131	0	0
T17	811158	811063	0	0
T18	154150	154141	0	0
T19	3674	3538	0	0