SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 8496 | 8496 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 2147483647 | 196650962 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 8496 | 8496 | 0 | 0 |
T1 | 8 | 8 | 0 | 0 |
T2 | 8 | 8 | 0 | 0 |
T3 | 8 | 8 | 0 | 0 |
T4 | 8 | 8 | 0 | 0 |
T5 | 8 | 8 | 0 | 0 |
T6 | 8 | 8 | 0 | 0 |
T16 | 8 | 8 | 0 | 0 |
T17 | 8 | 8 | 0 | 0 |
T18 | 8 | 8 | 0 | 0 |
T19 | 8 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 196650962 | 0 | 0 |
T1 | 212544 | 25856 | 0 | 0 |
T2 | 808 | 256 | 0 | 0 |
T3 | 410406 | 0 | 0 | 0 |
T4 | 6534 | 0 | 0 | 0 |
T5 | 5268 | 0 | 0 | 0 |
T6 | 629418 | 0 | 0 | 0 |
T7 | 602340 | 0 | 0 | 0 |
T11 | 9576 | 0 | 0 | 0 |
T12 | 4895 | 0 | 0 | 0 |
T16 | 6630 | 0 | 0 | 0 |
T17 | 4866948 | 51756 | 0 | 0 |
T18 | 1233200 | 2372396 | 0 | 0 |
T19 | 29392 | 0 | 0 | 0 |
T20 | 3032 | 0 | 0 | 0 |
T21 | 0 | 76800 | 0 | 0 |
T22 | 121000 | 0 | 0 | 0 |
T24 | 0 | 5120 | 0 | 0 |
T30 | 0 | 12800 | 0 | 0 |
T39 | 188410 | 0 | 0 | 0 |
T41 | 2118 | 0 | 0 | 0 |
T46 | 0 | 87552 | 0 | 0 |
T48 | 10192 | 0 | 0 | 0 |
T49 | 0 | 74784 | 0 | 0 |
T52 | 0 | 200 | 0 | 0 |
T81 | 0 | 84360 | 0 | 0 |
T82 | 0 | 1200 | 0 | 0 |
T83 | 0 | 1703936 | 0 | 0 |
T84 | 0 | 38400 | 0 | 0 |
T85 | 0 | 131072 | 0 | 0 |
T86 | 0 | 786432 | 0 | 0 |
T87 | 0 | 12800 | 0 | 0 |
T88 | 0 | 524288 | 0 | 0 |
T89 | 0 | 458752 | 0 | 0 |
T90 | 0 | 12800 | 0 | 0 |
T91 | 0 | 393216 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T3,T17,T18 |
1 | 0 | Covered | T3,T5,T17 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1062 | 1062 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 443449232 | 78032146 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1062 | 1062 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 443449232 | 78032146 | 0 | 0 |
T3 | 136802 | 1600 | 0 | 0 |
T4 | 2178 | 0 | 0 | 0 |
T5 | 1756 | 0 | 0 | 0 |
T6 | 104903 | 0 | 0 | 0 |
T11 | 1368 | 0 | 0 | 0 |
T12 | 0 | 256 | 0 | 0 |
T16 | 2210 | 0 | 0 | 0 |
T17 | 811158 | 3798 | 0 | 0 |
T18 | 154150 | 789386 | 0 | 0 |
T19 | 3674 | 0 | 0 | 0 |
T21 | 0 | 3580 | 0 | 0 |
T23 | 0 | 89600 | 0 | 0 |
T40 | 0 | 450 | 0 | 0 |
T48 | 1456 | 0 | 0 | 0 |
T92 | 0 | 393221 | 0 | 0 |
T93 | 0 | 100 | 0 | 0 |
T94 | 0 | 6400 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T17 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1062 | 1062 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 443449232 | 21353650 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1062 | 1062 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 443449232 | 21353650 | 0 | 0 |
T1 | 212544 | 25856 | 0 | 0 |
T2 | 808 | 256 | 0 | 0 |
T3 | 136802 | 0 | 0 | 0 |
T4 | 2178 | 0 | 0 | 0 |
T5 | 1756 | 0 | 0 | 0 |
T6 | 104903 | 0 | 0 | 0 |
T16 | 2210 | 0 | 0 | 0 |
T17 | 811158 | 51756 | 0 | 0 |
T18 | 154150 | 799532 | 0 | 0 |
T19 | 3674 | 0 | 0 | 0 |
T21 | 0 | 76800 | 0 | 0 |
T24 | 0 | 5120 | 0 | 0 |
T30 | 0 | 12800 | 0 | 0 |
T46 | 0 | 87552 | 0 | 0 |
T49 | 0 | 74784 | 0 | 0 |
T81 | 0 | 84360 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T18,T83,T84 |
1 | 0 | Covered | T6,T39,T34 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1062 | 1062 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 443449232 | 5307436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1062 | 1062 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 443449232 | 5307436 | 0 | 0 |
T7 | 120468 | 0 | 0 | 0 |
T11 | 1368 | 0 | 0 | 0 |
T12 | 979 | 0 | 0 | 0 |
T18 | 154150 | 786432 | 0 | 0 |
T19 | 3674 | 0 | 0 | 0 |
T20 | 1516 | 0 | 0 | 0 |
T22 | 24200 | 0 | 0 | 0 |
T39 | 37682 | 0 | 0 | 0 |
T41 | 1059 | 0 | 0 | 0 |
T48 | 1456 | 0 | 0 | 0 |
T83 | 0 | 851968 | 0 | 0 |
T84 | 0 | 12800 | 0 | 0 |
T85 | 0 | 65536 | 0 | 0 |
T86 | 0 | 393216 | 0 | 0 |
T87 | 0 | 12800 | 0 | 0 |
T88 | 0 | 524288 | 0 | 0 |
T89 | 0 | 458752 | 0 | 0 |
T90 | 0 | 12800 | 0 | 0 |
T91 | 0 | 393216 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T18,T52,T82 |
1 | 0 | Covered | T6,T39,T34 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1062 | 1062 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 443449232 | 5904454 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1062 | 1062 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 443449232 | 5904454 | 0 | 0 |
T7 | 120468 | 0 | 0 | 0 |
T11 | 1368 | 0 | 0 | 0 |
T12 | 979 | 0 | 0 | 0 |
T18 | 154150 | 786432 | 0 | 0 |
T19 | 3674 | 0 | 0 | 0 |
T20 | 1516 | 0 | 0 | 0 |
T22 | 24200 | 0 | 0 | 0 |
T39 | 37682 | 0 | 0 | 0 |
T41 | 1059 | 0 | 0 | 0 |
T48 | 1456 | 0 | 0 | 0 |
T52 | 0 | 200 | 0 | 0 |
T82 | 0 | 1200 | 0 | 0 |
T83 | 0 | 851968 | 0 | 0 |
T84 | 0 | 25600 | 0 | 0 |
T85 | 0 | 65536 | 0 | 0 |
T86 | 0 | 393216 | 0 | 0 |
T95 | 0 | 4864 | 0 | 0 |
T96 | 0 | 900 | 0 | 0 |
T97 | 0 | 256 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T3,T17,T18 |
1 | 0 | Covered | T3,T17,T6 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1062 | 1062 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 443449232 | 65833574 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1062 | 1062 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 443449232 | 65833574 | 0 | 0 |
T3 | 136802 | 131722 | 0 | 0 |
T4 | 2178 | 0 | 0 | 0 |
T5 | 1756 | 0 | 0 | 0 |
T6 | 104903 | 0 | 0 | 0 |
T11 | 1368 | 350 | 0 | 0 |
T16 | 2210 | 0 | 0 | 0 |
T17 | 811158 | 593804 | 0 | 0 |
T18 | 154150 | 593872 | 0 | 0 |
T19 | 3674 | 500 | 0 | 0 |
T20 | 0 | 400 | 0 | 0 |
T21 | 0 | 3792 | 0 | 0 |
T23 | 0 | 91600 | 0 | 0 |
T40 | 0 | 400 | 0 | 0 |
T48 | 1456 | 0 | 0 | 0 |
T92 | 0 | 393216 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T17,T18,T19 |
1 | 0 | Covered | T17,T18,T19 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1062 | 1062 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 443449232 | 7233176 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1062 | 1062 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 443449232 | 7233176 | 0 | 0 |
T6 | 104903 | 0 | 0 | 0 |
T7 | 120468 | 0 | 0 | 0 |
T11 | 1368 | 0 | 0 | 0 |
T12 | 979 | 0 | 0 | 0 |
T17 | 811158 | 666924 | 0 | 0 |
T18 | 154150 | 654080 | 0 | 0 |
T19 | 3674 | 550 | 0 | 0 |
T21 | 0 | 12800 | 0 | 0 |
T22 | 24200 | 0 | 0 | 0 |
T39 | 37682 | 0 | 0 | 0 |
T43 | 0 | 606 | 0 | 0 |
T48 | 1456 | 0 | 0 | 0 |
T75 | 0 | 470016 | 0 | 0 |
T83 | 0 | 641024 | 0 | 0 |
T98 | 0 | 256 | 0 | 0 |
T99 | 0 | 50 | 0 | 0 |
T100 | 0 | 915968 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T17,T18,T75 |
1 | 0 | Covered | T98,T101,T102 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1062 | 1062 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 443449232 | 6488064 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1062 | 1062 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 443449232 | 6488064 | 0 | 0 |
T6 | 104903 | 0 | 0 | 0 |
T7 | 120468 | 0 | 0 | 0 |
T11 | 1368 | 0 | 0 | 0 |
T12 | 979 | 0 | 0 | 0 |
T17 | 811158 | 589824 | 0 | 0 |
T18 | 154150 | 589824 | 0 | 0 |
T19 | 3674 | 0 | 0 | 0 |
T22 | 24200 | 0 | 0 | 0 |
T39 | 37682 | 0 | 0 | 0 |
T48 | 1456 | 0 | 0 | 0 |
T75 | 0 | 393216 | 0 | 0 |
T83 | 0 | 589824 | 0 | 0 |
T89 | 0 | 589824 | 0 | 0 |
T91 | 0 | 327680 | 0 | 0 |
T100 | 0 | 851968 | 0 | 0 |
T103 | 0 | 327680 | 0 | 0 |
T104 | 0 | 655360 | 0 | 0 |
T105 | 0 | 524288 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T17,T18,T21 |
1 | 0 | Covered | T21,T24,T101 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1062 | 1062 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 443449232 | 6498462 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1062 | 1062 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 443449232 | 6498462 | 0 | 0 |
T6 | 104903 | 0 | 0 | 0 |
T7 | 120468 | 0 | 0 | 0 |
T11 | 1368 | 0 | 0 | 0 |
T12 | 979 | 0 | 0 | 0 |
T17 | 811158 | 589824 | 0 | 0 |
T18 | 154150 | 589824 | 0 | 0 |
T19 | 3674 | 0 | 0 | 0 |
T21 | 0 | 300 | 0 | 0 |
T22 | 24200 | 0 | 0 | 0 |
T39 | 37682 | 0 | 0 | 0 |
T48 | 1456 | 0 | 0 | 0 |
T75 | 0 | 393216 | 0 | 0 |
T83 | 0 | 589824 | 0 | 0 |
T100 | 0 | 851968 | 0 | 0 |
T101 | 0 | 250 | 0 | 0 |
T106 | 0 | 506 | 0 | 0 |
T107 | 0 | 450 | 0 | 0 |
T108 | 0 | 400 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |