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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.62 95.75 94.21 98.95 92.52 98.24 98.41 98.24


Total test records in report: 1277
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1071 /workspace/coverage/default/67.flash_ctrl_connect.1766673833 Mar 10 12:39:34 PM PDT 24 Mar 10 12:39:50 PM PDT 24 43219100 ps
T1072 /workspace/coverage/default/4.flash_ctrl_alert_test.1645183039 Mar 10 12:35:44 PM PDT 24 Mar 10 12:35:58 PM PDT 24 96629700 ps
T1073 /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3077622234 Mar 10 12:36:10 PM PDT 24 Mar 10 12:38:32 PM PDT 24 10011706900 ps
T1074 /workspace/coverage/default/47.flash_ctrl_alert_test.601657939 Mar 10 12:39:29 PM PDT 24 Mar 10 12:39:46 PM PDT 24 42178700 ps
T1075 /workspace/coverage/default/29.flash_ctrl_connect.4108795110 Mar 10 12:38:37 PM PDT 24 Mar 10 12:38:50 PM PDT 24 21649800 ps
T1076 /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.4219416433 Mar 10 12:39:13 PM PDT 24 Mar 10 12:40:36 PM PDT 24 1005146400 ps
T1077 /workspace/coverage/default/3.flash_ctrl_ro_derr.3004677856 Mar 10 12:35:28 PM PDT 24 Mar 10 12:37:09 PM PDT 24 821673000 ps
T1078 /workspace/coverage/default/20.flash_ctrl_disable.625263657 Mar 10 12:37:54 PM PDT 24 Mar 10 12:38:17 PM PDT 24 21039300 ps
T1079 /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.3957144396 Mar 10 12:35:18 PM PDT 24 Mar 10 12:35:32 PM PDT 24 119220400 ps
T1080 /workspace/coverage/default/18.flash_ctrl_sec_info_access.3869453468 Mar 10 12:37:54 PM PDT 24 Mar 10 12:38:56 PM PDT 24 3073417900 ps
T1081 /workspace/coverage/default/4.flash_ctrl_rw.910220726 Mar 10 12:35:35 PM PDT 24 Mar 10 12:43:55 PM PDT 24 9040923900 ps
T1082 /workspace/coverage/default/31.flash_ctrl_connect.433485585 Mar 10 12:38:35 PM PDT 24 Mar 10 12:38:51 PM PDT 24 14370900 ps
T1083 /workspace/coverage/default/34.flash_ctrl_otp_reset.3208889828 Mar 10 12:38:53 PM PDT 24 Mar 10 12:41:06 PM PDT 24 221277500 ps
T1084 /workspace/coverage/default/16.flash_ctrl_rw.601955471 Mar 10 12:37:38 PM PDT 24 Mar 10 12:46:14 PM PDT 24 8171731100 ps
T347 /workspace/coverage/default/25.flash_ctrl_disable.2541446043 Mar 10 12:38:17 PM PDT 24 Mar 10 12:38:39 PM PDT 24 10921700 ps
T1085 /workspace/coverage/default/71.flash_ctrl_connect.3870491987 Mar 10 12:39:42 PM PDT 24 Mar 10 12:39:56 PM PDT 24 29641400 ps
T1086 /workspace/coverage/default/27.flash_ctrl_smoke.3238864268 Mar 10 12:38:15 PM PDT 24 Mar 10 12:39:53 PM PDT 24 139416600 ps
T1087 /workspace/coverage/default/70.flash_ctrl_otp_reset.2709060255 Mar 10 12:39:33 PM PDT 24 Mar 10 12:41:49 PM PDT 24 76358100 ps
T1088 /workspace/coverage/default/27.flash_ctrl_intr_rd.1895293202 Mar 10 12:38:22 PM PDT 24 Mar 10 12:41:36 PM PDT 24 15299989900 ps
T1089 /workspace/coverage/default/4.flash_ctrl_fetch_code.2219934389 Mar 10 12:35:38 PM PDT 24 Mar 10 12:36:05 PM PDT 24 137631400 ps
T1090 /workspace/coverage/default/9.flash_ctrl_fetch_code.1527151200 Mar 10 12:36:34 PM PDT 24 Mar 10 12:37:02 PM PDT 24 700055200 ps
T1091 /workspace/coverage/default/46.flash_ctrl_smoke.3782636316 Mar 10 12:39:21 PM PDT 24 Mar 10 12:43:02 PM PDT 24 166650400 ps
T1092 /workspace/coverage/default/33.flash_ctrl_smoke.3025380187 Mar 10 12:38:43 PM PDT 24 Mar 10 12:39:32 PM PDT 24 109982100 ps
T1093 /workspace/coverage/default/48.flash_ctrl_otp_reset.3902505246 Mar 10 12:39:15 PM PDT 24 Mar 10 12:41:33 PM PDT 24 74410100 ps
T223 /workspace/coverage/default/16.flash_ctrl_disable.3997465329 Mar 10 12:37:34 PM PDT 24 Mar 10 12:37:54 PM PDT 24 10286500 ps
T1094 /workspace/coverage/default/4.flash_ctrl_rw_evict.739189964 Mar 10 12:35:41 PM PDT 24 Mar 10 12:36:12 PM PDT 24 186442100 ps
T387 /workspace/coverage/default/18.flash_ctrl_rw_evict.193957293 Mar 10 12:37:49 PM PDT 24 Mar 10 12:38:24 PM PDT 24 103193000 ps
T1095 /workspace/coverage/default/9.flash_ctrl_connect.1594927024 Mar 10 12:36:38 PM PDT 24 Mar 10 12:36:52 PM PDT 24 63847200 ps
T1096 /workspace/coverage/default/20.flash_ctrl_intr_rd.1979972307 Mar 10 12:37:59 PM PDT 24 Mar 10 12:40:33 PM PDT 24 2254093400 ps
T1097 /workspace/coverage/default/1.flash_ctrl_serr_address.403806890 Mar 10 12:35:33 PM PDT 24 Mar 10 12:36:36 PM PDT 24 2268170800 ps
T1098 /workspace/coverage/default/34.flash_ctrl_alert_test.2308063095 Mar 10 12:38:46 PM PDT 24 Mar 10 12:38:59 PM PDT 24 50179700 ps
T1099 /workspace/coverage/default/43.flash_ctrl_connect.3224539381 Mar 10 12:39:14 PM PDT 24 Mar 10 12:39:28 PM PDT 24 53125300 ps
T1100 /workspace/coverage/default/19.flash_ctrl_alert_test.326275423 Mar 10 12:37:53 PM PDT 24 Mar 10 12:38:07 PM PDT 24 68649000 ps
T1101 /workspace/coverage/default/21.flash_ctrl_disable.3569521438 Mar 10 12:37:58 PM PDT 24 Mar 10 12:38:20 PM PDT 24 11018100 ps
T1102 /workspace/coverage/default/19.flash_ctrl_disable.1255020240 Mar 10 12:37:58 PM PDT 24 Mar 10 12:38:18 PM PDT 24 82586100 ps
T1103 /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2769767711 Mar 10 12:37:15 PM PDT 24 Mar 10 12:37:51 PM PDT 24 830627600 ps
T1104 /workspace/coverage/default/3.flash_ctrl_mp_regions.4000337346 Mar 10 12:35:29 PM PDT 24 Mar 10 12:42:13 PM PDT 24 29051668700 ps
T1105 /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.835793933 Mar 10 12:37:45 PM PDT 24 Mar 10 12:40:29 PM PDT 24 10019388900 ps
T1106 /workspace/coverage/default/46.flash_ctrl_otp_reset.229109641 Mar 10 12:39:17 PM PDT 24 Mar 10 12:41:32 PM PDT 24 392677100 ps
T1107 /workspace/coverage/default/42.flash_ctrl_connect.737249394 Mar 10 12:39:06 PM PDT 24 Mar 10 12:39:19 PM PDT 24 29791700 ps
T1108 /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.185858888 Mar 10 12:37:34 PM PDT 24 Mar 10 12:37:48 PM PDT 24 31871500 ps
T1109 /workspace/coverage/default/10.flash_ctrl_ro.2409362165 Mar 10 12:36:37 PM PDT 24 Mar 10 12:38:17 PM PDT 24 515131900 ps
T1110 /workspace/coverage/default/14.flash_ctrl_rw_evict.3583090265 Mar 10 12:37:20 PM PDT 24 Mar 10 12:37:52 PM PDT 24 99697500 ps
T1111 /workspace/coverage/default/17.flash_ctrl_ro.1986533235 Mar 10 12:37:36 PM PDT 24 Mar 10 12:39:07 PM PDT 24 838891000 ps
T1112 /workspace/coverage/default/10.flash_ctrl_prog_reset.3661707981 Mar 10 12:36:44 PM PDT 24 Mar 10 12:36:57 PM PDT 24 30624700 ps
T360 /workspace/coverage/default/46.flash_ctrl_disable.3887004306 Mar 10 12:39:28 PM PDT 24 Mar 10 12:39:48 PM PDT 24 35867500 ps
T1113 /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.2103233455 Mar 10 12:35:39 PM PDT 24 Mar 10 12:36:03 PM PDT 24 24414900 ps
T1114 /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.2486223523 Mar 10 12:38:31 PM PDT 24 Mar 10 12:41:43 PM PDT 24 19456064500 ps
T1115 /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.2330265655 Mar 10 12:37:20 PM PDT 24 Mar 10 12:37:51 PM PDT 24 55429900 ps
T1116 /workspace/coverage/default/10.flash_ctrl_rw_evict.3717579383 Mar 10 12:36:44 PM PDT 24 Mar 10 12:37:15 PM PDT 24 40593000 ps
T1117 /workspace/coverage/default/1.flash_ctrl_full_mem_access.1269758969 Mar 10 12:35:23 PM PDT 24 Mar 10 01:46:30 PM PDT 24 49891766700 ps
T1118 /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1227558849 Mar 10 12:38:21 PM PDT 24 Mar 10 12:38:54 PM PDT 24 79948800 ps
T126 /workspace/coverage/default/0.flash_ctrl_mid_op_rst.1273437004 Mar 10 12:35:21 PM PDT 24 Mar 10 12:36:35 PM PDT 24 9191511500 ps
T331 /workspace/coverage/default/3.flash_ctrl_derr_detect.3972077690 Mar 10 12:35:31 PM PDT 24 Mar 10 12:37:14 PM PDT 24 308509200 ps
T1119 /workspace/coverage/default/6.flash_ctrl_ro.2421226704 Mar 10 12:36:10 PM PDT 24 Mar 10 12:37:23 PM PDT 24 317600000 ps
T1120 /workspace/coverage/default/4.flash_ctrl_derr_detect.74100198 Mar 10 12:35:42 PM PDT 24 Mar 10 12:37:28 PM PDT 24 285727900 ps
T1121 /workspace/coverage/default/19.flash_ctrl_wo.1945240854 Mar 10 12:37:43 PM PDT 24 Mar 10 12:40:49 PM PDT 24 5661228800 ps
T1122 /workspace/coverage/default/2.flash_ctrl_prog_reset.3337732142 Mar 10 12:35:32 PM PDT 24 Mar 10 12:35:46 PM PDT 24 31886300 ps
T1123 /workspace/coverage/default/33.flash_ctrl_rw_evict.2711974298 Mar 10 12:38:53 PM PDT 24 Mar 10 12:39:30 PM PDT 24 192002400 ps
T1124 /workspace/coverage/default/5.flash_ctrl_intr_wr.517987091 Mar 10 12:36:57 PM PDT 24 Mar 10 12:38:26 PM PDT 24 7780560300 ps
T1125 /workspace/coverage/default/6.flash_ctrl_invalid_op.1352486807 Mar 10 12:36:00 PM PDT 24 Mar 10 12:37:28 PM PDT 24 1929431700 ps
T1126 /workspace/coverage/default/60.flash_ctrl_otp_reset.1563284908 Mar 10 12:39:30 PM PDT 24 Mar 10 12:41:47 PM PDT 24 38963800 ps
T1127 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2286292075 Mar 10 12:26:40 PM PDT 24 Mar 10 12:26:56 PM PDT 24 15098600 ps
T258 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2514789657 Mar 10 12:26:30 PM PDT 24 Mar 10 12:26:44 PM PDT 24 46354200 ps
T56 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1781672845 Mar 10 12:26:25 PM PDT 24 Mar 10 12:41:19 PM PDT 24 2836399500 ps
T259 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2163794636 Mar 10 12:28:25 PM PDT 24 Mar 10 12:28:38 PM PDT 24 23537900 ps
T57 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1728403911 Mar 10 12:26:26 PM PDT 24 Mar 10 12:27:02 PM PDT 24 69878700 ps
T58 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1673554519 Mar 10 12:26:31 PM PDT 24 Mar 10 12:27:08 PM PDT 24 348317500 ps
T176 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1270068912 Mar 10 12:26:39 PM PDT 24 Mar 10 12:26:54 PM PDT 24 102085700 ps
T177 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2153850688 Mar 10 12:26:01 PM PDT 24 Mar 10 12:40:45 PM PDT 24 7244705500 ps
T260 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2830409715 Mar 10 12:28:08 PM PDT 24 Mar 10 12:28:21 PM PDT 24 14222900 ps
T178 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2242967317 Mar 10 12:26:00 PM PDT 24 Mar 10 12:26:20 PM PDT 24 92754600 ps
T320 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.367308853 Mar 10 12:25:55 PM PDT 24 Mar 10 12:26:10 PM PDT 24 84616300 ps
T216 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3868705197 Mar 10 12:26:34 PM PDT 24 Mar 10 12:39:11 PM PDT 24 3001036600 ps
T1128 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2427441984 Mar 10 12:26:19 PM PDT 24 Mar 10 12:26:33 PM PDT 24 33511200 ps
T321 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3972419229 Mar 10 12:26:33 PM PDT 24 Mar 10 12:26:47 PM PDT 24 198594100 ps
T323 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1008918696 Mar 10 12:25:59 PM PDT 24 Mar 10 12:26:13 PM PDT 24 52045600 ps
T217 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.419221668 Mar 10 12:26:24 PM PDT 24 Mar 10 12:33:55 PM PDT 24 549847500 ps
T214 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1578917159 Mar 10 12:26:09 PM PDT 24 Mar 10 12:26:28 PM PDT 24 96380500 ps
T1129 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.416477425 Mar 10 12:26:09 PM PDT 24 Mar 10 12:26:25 PM PDT 24 40676000 ps
T322 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2044011495 Mar 10 12:26:41 PM PDT 24 Mar 10 12:26:54 PM PDT 24 48366100 ps
T1130 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.773733534 Mar 10 12:28:25 PM PDT 24 Mar 10 12:28:38 PM PDT 24 26556100 ps
T215 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3058301286 Mar 10 12:26:21 PM PDT 24 Mar 10 12:26:37 PM PDT 24 38323700 ps
T1131 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.258632430 Mar 10 12:26:04 PM PDT 24 Mar 10 12:26:18 PM PDT 24 23474900 ps
T319 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3572043758 Mar 10 12:25:56 PM PDT 24 Mar 10 12:27:07 PM PDT 24 2480343900 ps
T228 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2652919321 Mar 10 12:25:57 PM PDT 24 Mar 10 12:26:16 PM PDT 24 142564200 ps
T1132 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1636541253 Mar 10 12:26:17 PM PDT 24 Mar 10 12:26:36 PM PDT 24 305785200 ps
T1133 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2598785493 Mar 10 12:26:05 PM PDT 24 Mar 10 12:26:19 PM PDT 24 16116300 ps
T229 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3237381338 Mar 10 12:26:02 PM PDT 24 Mar 10 12:26:18 PM PDT 24 49082400 ps
T324 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4142489327 Mar 10 12:26:45 PM PDT 24 Mar 10 12:26:58 PM PDT 24 16612800 ps
T1134 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2601614991 Mar 10 12:26:16 PM PDT 24 Mar 10 12:26:30 PM PDT 24 12208400 ps
T1135 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2281944237 Mar 10 12:26:08 PM PDT 24 Mar 10 12:26:25 PM PDT 24 639293000 ps
T1136 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3245316118 Mar 10 12:26:02 PM PDT 24 Mar 10 12:26:16 PM PDT 24 49467600 ps
T230 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.183177165 Mar 10 12:26:03 PM PDT 24 Mar 10 12:26:24 PM PDT 24 149410900 ps
T239 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.241924748 Mar 10 12:26:07 PM PDT 24 Mar 10 12:26:21 PM PDT 24 34475100 ps
T1137 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.103060219 Mar 10 12:26:39 PM PDT 24 Mar 10 12:26:53 PM PDT 24 191391800 ps
T1138 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3104845122 Mar 10 12:26:26 PM PDT 24 Mar 10 12:26:41 PM PDT 24 33457400 ps
T1139 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.997199516 Mar 10 12:26:01 PM PDT 24 Mar 10 12:26:15 PM PDT 24 18178900 ps
T290 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2906379071 Mar 10 12:26:09 PM PDT 24 Mar 10 12:26:27 PM PDT 24 301746100 ps
T1140 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3654646409 Mar 10 12:26:27 PM PDT 24 Mar 10 12:26:42 PM PDT 24 42858200 ps
T231 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2258914093 Mar 10 12:25:59 PM PDT 24 Mar 10 12:26:19 PM PDT 24 98676700 ps
T291 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3335800649 Mar 10 12:26:35 PM PDT 24 Mar 10 12:26:55 PM PDT 24 849432000 ps
T1141 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3928818903 Mar 10 12:26:01 PM PDT 24 Mar 10 12:26:15 PM PDT 24 84467100 ps
T232 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.138788087 Mar 10 12:26:17 PM PDT 24 Mar 10 12:26:34 PM PDT 24 245035300 ps
T1142 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.4125676165 Mar 10 12:26:29 PM PDT 24 Mar 10 12:26:43 PM PDT 24 42314900 ps
T233 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1999406707 Mar 10 12:26:52 PM PDT 24 Mar 10 12:27:07 PM PDT 24 50959100 ps
T1143 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2376014328 Mar 10 12:26:06 PM PDT 24 Mar 10 12:26:24 PM PDT 24 53230300 ps
T1144 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1793166633 Mar 10 12:25:56 PM PDT 24 Mar 10 12:26:12 PM PDT 24 14388400 ps
T292 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2290608275 Mar 10 12:25:57 PM PDT 24 Mar 10 12:26:36 PM PDT 24 813233800 ps
T325 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.617855551 Mar 10 12:26:31 PM PDT 24 Mar 10 12:26:46 PM PDT 24 28260700 ps
T1145 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4177536046 Mar 10 12:25:53 PM PDT 24 Mar 10 12:26:07 PM PDT 24 15363100 ps
T234 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1933902499 Mar 10 12:26:11 PM PDT 24 Mar 10 12:26:31 PM PDT 24 1436982400 ps
T256 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3416735993 Mar 10 12:26:26 PM PDT 24 Mar 10 12:26:45 PM PDT 24 93293100 ps
T1146 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.744968790 Mar 10 12:26:31 PM PDT 24 Mar 10 12:26:45 PM PDT 24 49908900 ps
T265 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3495233237 Mar 10 12:26:30 PM PDT 24 Mar 10 12:26:46 PM PDT 24 214732300 ps
T1147 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3955712941 Mar 10 12:25:46 PM PDT 24 Mar 10 12:26:02 PM PDT 24 45172400 ps
T326 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.53407455 Mar 10 12:26:36 PM PDT 24 Mar 10 12:26:50 PM PDT 24 16207400 ps
T257 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1273463333 Mar 10 12:26:00 PM PDT 24 Mar 10 12:26:20 PM PDT 24 83379600 ps
T1148 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.122555549 Mar 10 12:25:59 PM PDT 24 Mar 10 12:26:42 PM PDT 24 4608420000 ps
T342 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3153651153 Mar 10 12:26:09 PM PDT 24 Mar 10 12:32:36 PM PDT 24 2997690000 ps
T262 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.691404970 Mar 10 12:26:36 PM PDT 24 Mar 10 12:26:55 PM PDT 24 183554100 ps
T1149 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2118913503 Mar 10 12:26:41 PM PDT 24 Mar 10 12:26:55 PM PDT 24 11746400 ps
T334 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1394182595 Mar 10 12:26:07 PM PDT 24 Mar 10 12:40:52 PM PDT 24 654052500 ps
T261 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2270890919 Mar 10 12:26:23 PM PDT 24 Mar 10 12:26:43 PM PDT 24 298565200 ps
T293 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.170446956 Mar 10 12:26:02 PM PDT 24 Mar 10 12:33:38 PM PDT 24 879778000 ps
T1150 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1372931893 Mar 10 12:25:58 PM PDT 24 Mar 10 12:26:13 PM PDT 24 35029000 ps
T255 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.812391144 Mar 10 12:25:51 PM PDT 24 Mar 10 12:26:10 PM PDT 24 63536700 ps
T266 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.208189780 Mar 10 12:26:27 PM PDT 24 Mar 10 12:26:43 PM PDT 24 37907700 ps
T1151 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2986794391 Mar 10 12:26:37 PM PDT 24 Mar 10 12:26:50 PM PDT 24 24953900 ps
T1152 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2516158289 Mar 10 12:26:32 PM PDT 24 Mar 10 12:26:46 PM PDT 24 36783300 ps
T1153 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.351543849 Mar 10 12:26:42 PM PDT 24 Mar 10 12:26:57 PM PDT 24 12379800 ps
T294 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1116437800 Mar 10 12:26:01 PM PDT 24 Mar 10 12:26:39 PM PDT 24 874606900 ps
T1154 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1204699108 Mar 10 12:26:13 PM PDT 24 Mar 10 12:26:30 PM PDT 24 27749800 ps
T1155 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2033978025 Mar 10 12:26:41 PM PDT 24 Mar 10 12:26:59 PM PDT 24 130158200 ps
T238 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3256640701 Mar 10 12:26:00 PM PDT 24 Mar 10 12:26:14 PM PDT 24 61404500 ps
T295 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2350286473 Mar 10 12:26:06 PM PDT 24 Mar 10 12:26:42 PM PDT 24 826853800 ps
T1156 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2713007926 Mar 10 12:26:38 PM PDT 24 Mar 10 12:26:52 PM PDT 24 36150800 ps
T1157 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.135773033 Mar 10 12:26:11 PM PDT 24 Mar 10 12:26:25 PM PDT 24 39918600 ps
T1158 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4285957921 Mar 10 12:26:34 PM PDT 24 Mar 10 12:26:48 PM PDT 24 16325700 ps
T1159 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1686944077 Mar 10 12:26:23 PM PDT 24 Mar 10 12:26:58 PM PDT 24 379035600 ps
T1160 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3768473236 Mar 10 12:26:13 PM PDT 24 Mar 10 12:26:44 PM PDT 24 40447800 ps
T1161 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3976417045 Mar 10 12:26:22 PM PDT 24 Mar 10 12:26:36 PM PDT 24 153190000 ps
T1162 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2345892407 Mar 10 12:25:58 PM PDT 24 Mar 10 12:26:16 PM PDT 24 69420700 ps
T270 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2389063492 Mar 10 12:26:07 PM PDT 24 Mar 10 12:38:39 PM PDT 24 1291101500 ps
T264 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2541667650 Mar 10 12:26:09 PM PDT 24 Mar 10 12:26:29 PM PDT 24 99868700 ps
T1163 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1743764258 Mar 10 12:26:35 PM PDT 24 Mar 10 12:26:48 PM PDT 24 46209000 ps
T269 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4034914912 Mar 10 12:26:43 PM PDT 24 Mar 10 12:26:58 PM PDT 24 32226600 ps
T1164 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1332243885 Mar 10 12:26:36 PM PDT 24 Mar 10 12:26:52 PM PDT 24 13149600 ps
T1165 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1969626346 Mar 10 12:26:11 PM PDT 24 Mar 10 12:26:26 PM PDT 24 36690700 ps
T1166 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2766903137 Mar 10 12:26:23 PM PDT 24 Mar 10 12:26:43 PM PDT 24 643986700 ps
T1167 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1955566402 Mar 10 12:26:25 PM PDT 24 Mar 10 12:26:40 PM PDT 24 14328000 ps
T1168 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.530785563 Mar 10 12:26:00 PM PDT 24 Mar 10 12:26:13 PM PDT 24 21199700 ps
T1169 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1487633159 Mar 10 12:26:01 PM PDT 24 Mar 10 12:26:48 PM PDT 24 48513200 ps
T296 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2888633917 Mar 10 12:26:33 PM PDT 24 Mar 10 12:26:53 PM PDT 24 833413500 ps
T1170 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2205947091 Mar 10 12:26:45 PM PDT 24 Mar 10 12:27:04 PM PDT 24 169256500 ps
T297 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2488288041 Mar 10 12:26:09 PM PDT 24 Mar 10 12:26:27 PM PDT 24 807215800 ps
T1171 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2097474856 Mar 10 12:26:03 PM PDT 24 Mar 10 12:26:16 PM PDT 24 24115900 ps
T1172 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2647020200 Mar 10 12:26:16 PM PDT 24 Mar 10 12:26:30 PM PDT 24 39384000 ps
T298 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.901352872 Mar 10 12:25:56 PM PDT 24 Mar 10 12:26:15 PM PDT 24 396613000 ps
T1173 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3433329734 Mar 10 12:26:56 PM PDT 24 Mar 10 12:27:11 PM PDT 24 360384400 ps
T240 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2502485421 Mar 10 12:26:02 PM PDT 24 Mar 10 12:26:16 PM PDT 24 30984000 ps
T1174 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2276923880 Mar 10 12:26:40 PM PDT 24 Mar 10 12:26:54 PM PDT 24 15728900 ps
T1175 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3127096674 Mar 10 12:25:58 PM PDT 24 Mar 10 12:26:14 PM PDT 24 20044400 ps
T1176 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1976343513 Mar 10 12:26:06 PM PDT 24 Mar 10 12:26:22 PM PDT 24 17538200 ps
T1177 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.4251358691 Mar 10 12:26:07 PM PDT 24 Mar 10 12:26:42 PM PDT 24 7266527400 ps
T1178 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2460480640 Mar 10 12:26:30 PM PDT 24 Mar 10 12:26:44 PM PDT 24 124143000 ps
T1179 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3927663395 Mar 10 12:26:20 PM PDT 24 Mar 10 12:26:40 PM PDT 24 108232400 ps
T1180 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3180456999 Mar 10 12:26:41 PM PDT 24 Mar 10 12:27:18 PM PDT 24 1711425900 ps
T1181 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2819917081 Mar 10 12:26:40 PM PDT 24 Mar 10 12:27:47 PM PDT 24 2381102800 ps
T1182 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2425188316 Mar 10 12:26:35 PM PDT 24 Mar 10 12:26:49 PM PDT 24 32565100 ps
T1183 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3004987118 Mar 10 12:25:57 PM PDT 24 Mar 10 12:26:14 PM PDT 24 318435700 ps
T1184 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.94226363 Mar 10 12:25:59 PM PDT 24 Mar 10 12:26:12 PM PDT 24 23973400 ps
T1185 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.790449228 Mar 10 12:26:36 PM PDT 24 Mar 10 12:26:50 PM PDT 24 18295000 ps
T1186 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.672416205 Mar 10 12:25:53 PM PDT 24 Mar 10 12:26:10 PM PDT 24 66520600 ps
T1187 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.990344812 Mar 10 12:26:15 PM PDT 24 Mar 10 12:26:28 PM PDT 24 17600900 ps
T1188 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.54906678 Mar 10 12:26:02 PM PDT 24 Mar 10 12:26:17 PM PDT 24 52304900 ps
T1189 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1600901149 Mar 10 12:26:35 PM PDT 24 Mar 10 12:26:49 PM PDT 24 16060900 ps
T1190 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1453354347 Mar 10 12:26:18 PM PDT 24 Mar 10 12:26:35 PM PDT 24 326355200 ps
T1191 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3884639154 Mar 10 12:26:01 PM PDT 24 Mar 10 12:26:18 PM PDT 24 147637600 ps
T267 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2188189175 Mar 10 12:25:57 PM PDT 24 Mar 10 12:26:13 PM PDT 24 107209900 ps
T1192 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3929808981 Mar 10 12:26:13 PM PDT 24 Mar 10 12:26:29 PM PDT 24 47871100 ps
T1193 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2654685008 Mar 10 12:26:02 PM PDT 24 Mar 10 12:26:18 PM PDT 24 15507700 ps
T1194 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3538404995 Mar 10 12:26:42 PM PDT 24 Mar 10 12:26:56 PM PDT 24 149722400 ps
T1195 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2580401585 Mar 10 12:26:26 PM PDT 24 Mar 10 12:26:43 PM PDT 24 33843000 ps
T1196 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4280254086 Mar 10 12:25:55 PM PDT 24 Mar 10 12:26:22 PM PDT 24 66427100 ps
T1197 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2190780788 Mar 10 12:26:06 PM PDT 24 Mar 10 12:26:21 PM PDT 24 134494100 ps
T1198 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3691195184 Mar 10 12:26:01 PM PDT 24 Mar 10 12:26:21 PM PDT 24 115892000 ps
T1199 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.435814933 Mar 10 12:26:17 PM PDT 24 Mar 10 12:26:30 PM PDT 24 20207900 ps
T1200 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3299231283 Mar 10 12:26:01 PM PDT 24 Mar 10 12:26:36 PM PDT 24 248931800 ps
T335 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1096491498 Mar 10 12:26:00 PM PDT 24 Mar 10 12:33:41 PM PDT 24 742537900 ps
T1201 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2924816017 Mar 10 12:26:32 PM PDT 24 Mar 10 12:26:47 PM PDT 24 54194800 ps
T1202 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3897621995 Mar 10 12:25:57 PM PDT 24 Mar 10 12:26:10 PM PDT 24 108198300 ps
T1203 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1497575543 Mar 10 12:26:26 PM PDT 24 Mar 10 12:26:43 PM PDT 24 23015500 ps
T1204 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4017189957 Mar 10 12:26:33 PM PDT 24 Mar 10 12:26:47 PM PDT 24 31332800 ps
T1205 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3065977554 Mar 10 12:26:26 PM PDT 24 Mar 10 12:26:42 PM PDT 24 145395400 ps
T1206 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2268243033 Mar 10 12:25:57 PM PDT 24 Mar 10 12:26:13 PM PDT 24 21941800 ps
T1207 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3529217389 Mar 10 12:26:22 PM PDT 24 Mar 10 12:26:36 PM PDT 24 58954000 ps
T1208 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2357849752 Mar 10 12:26:33 PM PDT 24 Mar 10 12:26:50 PM PDT 24 284857400 ps
T1209 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.889323557 Mar 10 12:25:54 PM PDT 24 Mar 10 12:26:12 PM PDT 24 57873200 ps
T336 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1700363485 Mar 10 12:26:03 PM PDT 24 Mar 10 12:41:04 PM PDT 24 10808240200 ps
T1210 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2547600805 Mar 10 12:26:05 PM PDT 24 Mar 10 12:26:19 PM PDT 24 57104000 ps
T1211 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3338508149 Mar 10 12:26:34 PM PDT 24 Mar 10 12:26:48 PM PDT 24 30412200 ps
T1212 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3481555788 Mar 10 12:26:19 PM PDT 24 Mar 10 12:26:35 PM PDT 24 13194900 ps
T1213 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2036542989 Mar 10 12:26:02 PM PDT 24 Mar 10 12:26:21 PM PDT 24 248890500 ps
T1214 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3095264948 Mar 10 12:26:19 PM PDT 24 Mar 10 12:26:58 PM PDT 24 4437817700 ps
T1215 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.876689798 Mar 10 12:26:18 PM PDT 24 Mar 10 12:26:35 PM PDT 24 192253700 ps
T268 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3421302047 Mar 10 12:26:08 PM PDT 24 Mar 10 12:26:27 PM PDT 24 47119800 ps
T1216 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1566353323 Mar 10 12:26:16 PM PDT 24 Mar 10 12:26:31 PM PDT 24 37036900 ps
T1217 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.4113816325 Mar 10 12:26:06 PM PDT 24 Mar 10 12:26:19 PM PDT 24 61558700 ps
T1218 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.888792186 Mar 10 12:27:39 PM PDT 24 Mar 10 12:27:54 PM PDT 24 26511600 ps
T1219 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1828639542 Mar 10 12:26:04 PM PDT 24 Mar 10 12:26:20 PM PDT 24 33000500 ps
T1220 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1903628542 Mar 10 12:26:04 PM PDT 24 Mar 10 12:27:05 PM PDT 24 5286524600 ps
T1221 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3546293207 Mar 10 12:25:59 PM PDT 24 Mar 10 12:26:30 PM PDT 24 50783900 ps
T1222 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3003542639 Mar 10 12:26:46 PM PDT 24 Mar 10 12:26:59 PM PDT 24 19822500 ps
T1223 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.467440679 Mar 10 12:25:59 PM PDT 24 Mar 10 12:26:19 PM PDT 24 61516400 ps
T1224 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.222185672 Mar 10 12:25:58 PM PDT 24 Mar 10 12:26:14 PM PDT 24 40333800 ps
T1225 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2074439523 Mar 10 12:26:31 PM PDT 24 Mar 10 12:26:47 PM PDT 24 32397200 ps
T1226 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2662164432 Mar 10 12:26:46 PM PDT 24 Mar 10 12:27:20 PM PDT 24 998083000 ps
T241 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3534522026 Mar 10 12:25:56 PM PDT 24 Mar 10 12:26:10 PM PDT 24 17699500 ps
T1227 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3776762059 Mar 10 12:26:04 PM PDT 24 Mar 10 12:26:18 PM PDT 24 127601200 ps
T1228 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.388558220 Mar 10 12:26:06 PM PDT 24 Mar 10 12:26:20 PM PDT 24 16389200 ps
T1229 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1402437316 Mar 10 12:26:00 PM PDT 24 Mar 10 12:26:18 PM PDT 24 92618000 ps
T1230 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3276809396 Mar 10 12:26:19 PM PDT 24 Mar 10 12:26:35 PM PDT 24 13795000 ps
T1231 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.70200904 Mar 10 12:26:04 PM PDT 24 Mar 10 12:26:20 PM PDT 24 14785600 ps
T1232 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1429099787 Mar 10 12:26:01 PM PDT 24 Mar 10 12:26:23 PM PDT 24 166714800 ps
T1233 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3091999892 Mar 10 12:26:36 PM PDT 24 Mar 10 12:26:49 PM PDT 24 30617200 ps
T1234 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3876964879 Mar 10 12:26:36 PM PDT 24 Mar 10 12:26:50 PM PDT 24 44369500 ps
T1235 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2881022268 Mar 10 12:26:19 PM PDT 24 Mar 10 12:26:35 PM PDT 24 18057800 ps
T1236 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3920278603 Mar 10 12:26:35 PM PDT 24 Mar 10 12:26:49 PM PDT 24 14652800 ps
T263 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2518373950 Mar 10 12:26:04 PM PDT 24 Mar 10 12:41:07 PM PDT 24 3066560600 ps
T242 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1766052478 Mar 10 12:25:56 PM PDT 24 Mar 10 12:26:10 PM PDT 24 58824000 ps
T1237 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2017262930 Mar 10 12:26:38 PM PDT 24 Mar 10 12:26:51 PM PDT 24 17335700 ps
T1238 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.4238773284 Mar 10 12:26:37 PM PDT 24 Mar 10 12:26:51 PM PDT 24 52557000 ps
T1239 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3844922884 Mar 10 12:26:19 PM PDT 24 Mar 10 12:26:33 PM PDT 24 50574000 ps
T1240 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4222649367 Mar 10 12:26:07 PM PDT 24 Mar 10 12:26:20 PM PDT 24 35785300 ps
T1241 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3470174134 Mar 10 12:26:07 PM PDT 24 Mar 10 12:26:23 PM PDT 24 193084200 ps
T1242 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1606384379 Mar 10 12:26:37 PM PDT 24 Mar 10 12:26:50 PM PDT 24 47772700 ps
T1243 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4123095995 Mar 10 12:26:43 PM PDT 24 Mar 10 12:26:57 PM PDT 24 78445400 ps
T339 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2785789173 Mar 10 12:26:15 PM PDT 24 Mar 10 12:32:39 PM PDT 24 3261076900 ps
T1244 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3980122012 Mar 10 12:25:56 PM PDT 24 Mar 10 12:26:10 PM PDT 24 67302100 ps
T337 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1751907864 Mar 10 12:26:19 PM PDT 24 Mar 10 12:41:40 PM PDT 24 13218352400 ps
T1245 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1401899275 Mar 10 12:26:01 PM PDT 24 Mar 10 12:26:16 PM PDT 24 74881500 ps
T1246 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1866169091 Mar 10 12:26:08 PM PDT 24 Mar 10 12:26:25 PM PDT 24 35170100 ps
T1247 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.4182953385 Mar 10 12:26:02 PM PDT 24 Mar 10 12:26:18 PM PDT 24 28452500 ps
T1248 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2815339355 Mar 10 12:26:12 PM PDT 24 Mar 10 12:26:28 PM PDT 24 12407400 ps
T1249 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1519415628 Mar 10 12:26:26 PM PDT 24 Mar 10 12:26:44 PM PDT 24 126753900 ps
T1250 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3065594081 Mar 10 12:26:13 PM PDT 24 Mar 10 12:32:31 PM PDT 24 732997300 ps
T1251 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3672014040 Mar 10 12:25:52 PM PDT 24 Mar 10 12:38:32 PM PDT 24 1366149000 ps
T1252 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.612742734 Mar 10 12:26:37 PM PDT 24 Mar 10 12:26:56 PM PDT 24 284993200 ps
T1253 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2441634910 Mar 10 12:25:47 PM PDT 24 Mar 10 12:26:03 PM PDT 24 98681100 ps
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