Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.62 95.75 94.21 98.95 92.52 98.24 98.41 98.24


Total test records in report: 1277
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T1254 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4268122382 Mar 10 12:26:37 PM PDT 24 Mar 10 12:27:14 PM PDT 24 1283074400 ps
T1255 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3091851524 Mar 10 12:26:04 PM PDT 24 Mar 10 12:26:34 PM PDT 24 196517300 ps
T1256 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3715518483 Mar 10 12:28:08 PM PDT 24 Mar 10 12:28:21 PM PDT 24 30875100 ps
T1257 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.181248512 Mar 10 12:26:38 PM PDT 24 Mar 10 12:26:52 PM PDT 24 28167800 ps
T1258 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2391962938 Mar 10 12:28:23 PM PDT 24 Mar 10 12:36:00 PM PDT 24 1641667500 ps
T341 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2624583138 Mar 10 12:26:17 PM PDT 24 Mar 10 12:32:43 PM PDT 24 185443400 ps
T1259 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3523696552 Mar 10 12:26:37 PM PDT 24 Mar 10 12:26:50 PM PDT 24 18669600 ps
T1260 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1039681985 Mar 10 12:26:02 PM PDT 24 Mar 10 12:26:37 PM PDT 24 120833500 ps
T1261 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.284593706 Mar 10 12:26:19 PM PDT 24 Mar 10 12:26:33 PM PDT 24 11991300 ps
T1262 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3154625692 Mar 10 12:26:33 PM PDT 24 Mar 10 12:26:49 PM PDT 24 56840600 ps
T1263 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3830362901 Mar 10 12:26:44 PM PDT 24 Mar 10 12:27:30 PM PDT 24 247191100 ps
T340 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.129520898 Mar 10 12:25:46 PM PDT 24 Mar 10 12:33:18 PM PDT 24 171172600 ps
T1264 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4149330435 Mar 10 12:26:06 PM PDT 24 Mar 10 12:26:20 PM PDT 24 48945300 ps
T1265 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2811375147 Mar 10 12:26:29 PM PDT 24 Mar 10 12:26:49 PM PDT 24 39668200 ps
T1266 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2255955994 Mar 10 12:26:38 PM PDT 24 Mar 10 12:26:55 PM PDT 24 58045800 ps
T1267 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2693582730 Mar 10 12:26:14 PM PDT 24 Mar 10 12:26:32 PM PDT 24 267080100 ps
T1268 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3526215022 Mar 10 12:26:21 PM PDT 24 Mar 10 12:34:06 PM PDT 24 1633013800 ps
T1269 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3493776675 Mar 10 12:25:56 PM PDT 24 Mar 10 12:26:10 PM PDT 24 110560600 ps
T1270 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.498038146 Mar 10 12:26:11 PM PDT 24 Mar 10 12:26:28 PM PDT 24 13197900 ps
T1271 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1052951153 Mar 10 12:26:23 PM PDT 24 Mar 10 12:26:40 PM PDT 24 54712600 ps
T1272 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1589492550 Mar 10 12:26:19 PM PDT 24 Mar 10 12:26:33 PM PDT 24 44865500 ps
T1273 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2212972827 Mar 10 12:26:13 PM PDT 24 Mar 10 12:26:29 PM PDT 24 89013900 ps
T1274 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.367812249 Mar 10 12:25:47 PM PDT 24 Mar 10 12:26:22 PM PDT 24 228253800 ps
T338 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.864669012 Mar 10 12:26:01 PM PDT 24 Mar 10 12:33:35 PM PDT 24 358676900 ps
T1275 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1869427754 Mar 10 12:26:02 PM PDT 24 Mar 10 12:26:20 PM PDT 24 354925400 ps
T1276 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2379143167 Mar 10 12:25:56 PM PDT 24 Mar 10 12:26:15 PM PDT 24 206533000 ps
T1277 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3319728200 Mar 10 12:26:46 PM PDT 24 Mar 10 12:27:04 PM PDT 24 91906700 ps

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.3097008095
Short name T17
Test name
Test status
Simulation time 32446420200 ps
CPU time 644.9 seconds
Started Mar 10 12:37:27 PM PDT 24
Finished Mar 10 12:48:12 PM PDT 24
Peak memory 273716 kb
Host smart-87350e95-b8ab-49a5-943d-46c2fcfda7d0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097008095 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.3097008095
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.2211526642
Short name T6
Test name
Test status
Simulation time 1091016300 ps
CPU time 149.87 seconds
Started Mar 10 12:35:53 PM PDT 24
Finished Mar 10 12:38:23 PM PDT 24
Peak memory 293084 kb
Host smart-f7938099-cef8-4ad8-87f2-1961c7a8b9ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211526642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.2211526642
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.419221668
Short name T217
Test name
Test status
Simulation time 549847500 ps
CPU time 450.75 seconds
Started Mar 10 12:26:24 PM PDT 24
Finished Mar 10 12:33:55 PM PDT 24
Peak memory 263288 kb
Host smart-656c19a7-bb70-403c-8895-5f462c2cccd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419221668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl
_tl_intg_err.419221668
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.96602715
Short name T92
Test name
Test status
Simulation time 80153278200 ps
CPU time 738.78 seconds
Started Mar 10 12:36:22 PM PDT 24
Finished Mar 10 12:48:41 PM PDT 24
Peak memory 262424 kb
Host smart-11b4476c-b5a1-4378-b2e2-6e07b9c8a5c9
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96602715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.flash_ctrl_hw_rma_reset.96602715
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.1937555439
Short name T114
Test name
Test status
Simulation time 77439500 ps
CPU time 132.29 seconds
Started Mar 10 12:39:39 PM PDT 24
Finished Mar 10 12:41:51 PM PDT 24
Peak memory 258980 kb
Host smart-6faf4f76-2c08-4171-9358-bb5a58afcdeb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937555439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.1937555439
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.2149950686
Short name T14
Test name
Test status
Simulation time 7550279200 ps
CPU time 4768.23 seconds
Started Mar 10 12:35:31 PM PDT 24
Finished Mar 10 01:55:00 PM PDT 24
Peak memory 294172 kb
Host smart-48e72039-dea7-450a-9967-520987fd8acd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149950686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.2149950686
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.1286203286
Short name T49
Test name
Test status
Simulation time 7696180900 ps
CPU time 78.14 seconds
Started Mar 10 12:39:18 PM PDT 24
Finished Mar 10 12:40:37 PM PDT 24
Peak memory 258520 kb
Host smart-760ea0b5-30c8-4b2a-a0fb-52fec8bdd4b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286203286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.1286203286
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.3587593129
Short name T37
Test name
Test status
Simulation time 16923859200 ps
CPU time 506.72 seconds
Started Mar 10 12:35:15 PM PDT 24
Finished Mar 10 12:43:42 PM PDT 24
Peak memory 327704 kb
Host smart-6b3d248e-8acd-4ec1-ae79-b43e27fde199
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587593129 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.3587593129
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.3044189157
Short name T120
Test name
Test status
Simulation time 8174937800 ps
CPU time 419.7 seconds
Started Mar 10 12:35:38 PM PDT 24
Finished Mar 10 12:42:40 PM PDT 24
Peak memory 260400 kb
Host smart-6fa8e0b3-4b68-4d78-9a74-a5bf341ba660
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3044189157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3044189157
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3058301286
Short name T215
Test name
Test status
Simulation time 38323700 ps
CPU time 15.78 seconds
Started Mar 10 12:26:21 PM PDT 24
Finished Mar 10 12:26:37 PM PDT 24
Peak memory 263240 kb
Host smart-c86683fb-5410-48fb-9ba9-4dd899832742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058301286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
3058301286
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.2067288368
Short name T9
Test name
Test status
Simulation time 81412100 ps
CPU time 13.87 seconds
Started Mar 10 12:35:13 PM PDT 24
Finished Mar 10 12:35:27 PM PDT 24
Peak memory 264880 kb
Host smart-eadb1bdd-6469-45f1-93e3-7cf3307fbbf4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067288368 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2067288368
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.3412789565
Short name T11
Test name
Test status
Simulation time 14255600 ps
CPU time 13.82 seconds
Started Mar 10 12:35:15 PM PDT 24
Finished Mar 10 12:35:29 PM PDT 24
Peak memory 264748 kb
Host smart-7001bc1f-3bbf-446b-8f3d-956e1789f67c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412789565 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3412789565
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.1450124525
Short name T116
Test name
Test status
Simulation time 839866400 ps
CPU time 70.33 seconds
Started Mar 10 12:35:20 PM PDT 24
Finished Mar 10 12:36:30 PM PDT 24
Peak memory 259244 kb
Host smart-125a971f-dd76-4cdd-8eb5-bded420eceeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450124525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.1450124525
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.3715683293
Short name T145
Test name
Test status
Simulation time 48728700 ps
CPU time 114.94 seconds
Started Mar 10 12:39:23 PM PDT 24
Finished Mar 10 12:41:19 PM PDT 24
Peak memory 263380 kb
Host smart-c9cd7487-8409-492e-bf62-011f85c04b3c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715683293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.3715683293
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2153850688
Short name T177
Test name
Test status
Simulation time 7244705500 ps
CPU time 882.43 seconds
Started Mar 10 12:26:01 PM PDT 24
Finished Mar 10 12:40:45 PM PDT 24
Peak memory 259584 kb
Host smart-585882af-0284-4bb9-8220-0770ab28ec91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153850688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.2153850688
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.3129256946
Short name T130
Test name
Test status
Simulation time 130922500 ps
CPU time 130.32 seconds
Started Mar 10 12:39:39 PM PDT 24
Finished Mar 10 12:41:51 PM PDT 24
Peak memory 263268 kb
Host smart-59aeb5ee-088a-41c1-b817-5c37f2ba53b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129256946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.3129256946
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.367308853
Short name T320
Test name
Test status
Simulation time 84616300 ps
CPU time 13.59 seconds
Started Mar 10 12:25:55 PM PDT 24
Finished Mar 10 12:26:10 PM PDT 24
Peak memory 261472 kb
Host smart-220b25cf-5893-4e27-861c-4e414c43b1fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367308853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.367308853
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.1350985116
Short name T78
Test name
Test status
Simulation time 6170375100 ps
CPU time 4778.02 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 01:55:01 PM PDT 24
Peak memory 294556 kb
Host smart-03f70f22-fa03-4f31-9237-a94eb471d9cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350985116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.1350985116
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.3543200973
Short name T60
Test name
Test status
Simulation time 83835740600 ps
CPU time 862.04 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:49:44 PM PDT 24
Peak memory 258372 kb
Host smart-9d060b12-4982-45af-8afc-3d2180008f0c
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543200973 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.3543200973
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.2855745680
Short name T16
Test name
Test status
Simulation time 34508500 ps
CPU time 13.45 seconds
Started Mar 10 12:36:10 PM PDT 24
Finished Mar 10 12:36:25 PM PDT 24
Peak memory 263760 kb
Host smart-fa0dc670-bb4f-4030-8b4e-55c509627d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855745680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.2
855745680
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1391798328
Short name T142
Test name
Test status
Simulation time 10017126000 ps
CPU time 181.7 seconds
Started Mar 10 12:36:29 PM PDT 24
Finished Mar 10 12:39:31 PM PDT 24
Peak memory 265804 kb
Host smart-5447491f-6cf1-4e79-8cb2-4e2f1644e0e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391798328 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1391798328
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.4005413009
Short name T1
Test name
Test status
Simulation time 17726229000 ps
CPU time 74.66 seconds
Started Mar 10 12:36:09 PM PDT 24
Finished Mar 10 12:37:26 PM PDT 24
Peak memory 263592 kb
Host smart-c9dd3a2f-672a-4e48-a21d-290fb3e4642c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005413009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.4005413009
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.3974049669
Short name T80
Test name
Test status
Simulation time 246600575000 ps
CPU time 2593.21 seconds
Started Mar 10 12:35:23 PM PDT 24
Finished Mar 10 01:18:37 PM PDT 24
Peak memory 264780 kb
Host smart-adbafd31-cf98-47c3-bacb-2df9cc7942df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974049669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.3974049669
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.1262657253
Short name T115
Test name
Test status
Simulation time 644902300 ps
CPU time 70.26 seconds
Started Mar 10 12:35:34 PM PDT 24
Finished Mar 10 12:36:44 PM PDT 24
Peak memory 260080 kb
Host smart-073c46a1-cceb-457b-a746-cf780fe94dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262657253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1262657253
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.3835942847
Short name T127
Test name
Test status
Simulation time 674263000 ps
CPU time 38.39 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:36:06 PM PDT 24
Peak memory 264840 kb
Host smart-38a7d94e-5508-4f11-bd45-913b9210ccb3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835942847 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3835942847
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.1309840221
Short name T136
Test name
Test status
Simulation time 144300000 ps
CPU time 130.77 seconds
Started Mar 10 12:38:19 PM PDT 24
Finished Mar 10 12:40:30 PM PDT 24
Peak memory 258976 kb
Host smart-618adfed-7b60-4a94-8e02-9165348234a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309840221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.1309840221
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.3839684726
Short name T583
Test name
Test status
Simulation time 581809900 ps
CPU time 112.99 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:37:20 PM PDT 24
Peak memory 263488 kb
Host smart-6f523342-4fce-4284-bf58-1a160308b565
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839684726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.3839684726
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.546947264
Short name T22
Test name
Test status
Simulation time 251709400 ps
CPU time 22.21 seconds
Started Mar 10 12:35:56 PM PDT 24
Finished Mar 10 12:36:18 PM PDT 24
Peak memory 264756 kb
Host smart-07e4fac8-a322-43a4-87e0-b5067143a411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546947264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.546947264
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2170702356
Short name T118
Test name
Test status
Simulation time 8292567300 ps
CPU time 211.1 seconds
Started Mar 10 12:39:05 PM PDT 24
Finished Mar 10 12:42:37 PM PDT 24
Peak memory 289388 kb
Host smart-05d97f89-ae88-4462-b5c1-41a832757a4a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170702356 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.2170702356
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3416735993
Short name T256
Test name
Test status
Simulation time 93293100 ps
CPU time 18.09 seconds
Started Mar 10 12:26:26 PM PDT 24
Finished Mar 10 12:26:45 PM PDT 24
Peak memory 263228 kb
Host smart-8763f45b-0279-4f0d-849b-a849cf352971
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416735993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
3416735993
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.4020470995
Short name T25
Test name
Test status
Simulation time 648755500 ps
CPU time 35.54 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:36:03 PM PDT 24
Peak memory 265964 kb
Host smart-d6a1b934-e261-4b54-9a4f-38e0618018db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020470995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.4020470995
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.964132937
Short name T52
Test name
Test status
Simulation time 22568240000 ps
CPU time 524.15 seconds
Started Mar 10 12:35:39 PM PDT 24
Finished Mar 10 12:44:24 PM PDT 24
Peak memory 321592 kb
Host smart-1c3c9df0-9db6-4c34-b5ea-b59b48baeac7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964132937 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.flash_ctrl_integrity.964132937
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3256640701
Short name T238
Test name
Test status
Simulation time 61404500 ps
CPU time 13.6 seconds
Started Mar 10 12:26:00 PM PDT 24
Finished Mar 10 12:26:14 PM PDT 24
Peak memory 263132 kb
Host smart-4b56905a-b8fc-4859-b2c4-dc6451284234
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256640701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.3256640701
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.3625200190
Short name T7
Test name
Test status
Simulation time 2457569200 ps
CPU time 201.05 seconds
Started Mar 10 12:36:17 PM PDT 24
Finished Mar 10 12:39:38 PM PDT 24
Peak memory 294108 kb
Host smart-011f3b3a-aa6b-4ef8-b143-0f22d213bf93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625200190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.3625200190
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.221092380
Short name T598
Test name
Test status
Simulation time 10012481800 ps
CPU time 108.07 seconds
Started Mar 10 12:36:38 PM PDT 24
Finished Mar 10 12:38:27 PM PDT 24
Peak memory 321256 kb
Host smart-0f319822-c078-4bf9-b357-7e69012c147d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221092380 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.221092380
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1781672845
Short name T56
Test name
Test status
Simulation time 2836399500 ps
CPU time 892.75 seconds
Started Mar 10 12:26:25 PM PDT 24
Finished Mar 10 12:41:19 PM PDT 24
Peak memory 263356 kb
Host smart-8b36f499-b64a-4e5b-a644-bfa0aadd8775
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781672845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.1781672845
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.1111733595
Short name T314
Test name
Test status
Simulation time 36696100 ps
CPU time 13.39 seconds
Started Mar 10 12:36:42 PM PDT 24
Finished Mar 10 12:36:56 PM PDT 24
Peak memory 264732 kb
Host smart-a27f2825-5855-4b94-8894-7e8def0e68e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111733595 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.1111733595
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.2246969403
Short name T13
Test name
Test status
Simulation time 159706100 ps
CPU time 13.87 seconds
Started Mar 10 12:35:19 PM PDT 24
Finished Mar 10 12:35:33 PM PDT 24
Peak memory 264880 kb
Host smart-38f5c3a4-cd01-4e47-aab8-92c24a3da7c9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246969403 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.2246969403
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.3736690013
Short name T379
Test name
Test status
Simulation time 32922686900 ps
CPU time 100.91 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:37:03 PM PDT 24
Peak memory 262392 kb
Host smart-2401b40e-3c46-4e20-b15f-edb3c8737e4c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736690013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.3736690013
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.2354414493
Short name T18
Test name
Test status
Simulation time 19422934600 ps
CPU time 1214.19 seconds
Started Mar 10 12:37:34 PM PDT 24
Finished Mar 10 12:57:48 PM PDT 24
Peak memory 272672 kb
Host smart-2332a475-76aa-4a98-afa5-8779ef813ebd
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354414493 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.2354414493
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.415929028
Short name T69
Test name
Test status
Simulation time 3964272400 ps
CPU time 154.89 seconds
Started Mar 10 12:35:20 PM PDT 24
Finished Mar 10 12:37:56 PM PDT 24
Peak memory 281268 kb
Host smart-3aeb15d2-b6a5-4f8f-8bf9-efd0f85ef435
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415929028 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.415929028
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2044011495
Short name T322
Test name
Test status
Simulation time 48366100 ps
CPU time 13.32 seconds
Started Mar 10 12:26:41 PM PDT 24
Finished Mar 10 12:26:54 PM PDT 24
Peak memory 261472 kb
Host smart-dd0a61d4-624f-402a-be1e-7c8a719a0a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044011495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
2044011495
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.316597033
Short name T94
Test name
Test status
Simulation time 199522900 ps
CPU time 35.14 seconds
Started Mar 10 12:36:13 PM PDT 24
Finished Mar 10 12:36:49 PM PDT 24
Peak memory 272956 kb
Host smart-0747c7a4-db4f-4724-aa4a-e599ecfa9ed7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316597033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_re_evict.316597033
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.1358751949
Short name T172
Test name
Test status
Simulation time 161083500 ps
CPU time 14.38 seconds
Started Mar 10 12:35:26 PM PDT 24
Finished Mar 10 12:35:41 PM PDT 24
Peak memory 264764 kb
Host smart-250fe24f-2aaa-46ba-bf7f-a26e70465c9f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358751949 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.1358751949
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.821192767
Short name T209
Test name
Test status
Simulation time 2632369400 ps
CPU time 330.1 seconds
Started Mar 10 12:37:54 PM PDT 24
Finished Mar 10 12:43:24 PM PDT 24
Peak memory 308596 kb
Host smart-25807072-11c7-409b-bd9d-88df874e9ff1
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821192767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ct
rl_rw.821192767
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1578917159
Short name T214
Test name
Test status
Simulation time 96380500 ps
CPU time 18.93 seconds
Started Mar 10 12:26:09 PM PDT 24
Finished Mar 10 12:26:28 PM PDT 24
Peak memory 271424 kb
Host smart-d2ca850b-91bd-4cc8-9790-ef75cfa10b6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578917159 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.1578917159
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.1017480396
Short name T350
Test name
Test status
Simulation time 17456600 ps
CPU time 22.3 seconds
Started Mar 10 12:37:27 PM PDT 24
Finished Mar 10 12:37:50 PM PDT 24
Peak memory 273120 kb
Host smart-45d466dc-117c-4e68-a79f-0c67cdf9d20a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017480396 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.1017480396
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.2711974298
Short name T1123
Test name
Test status
Simulation time 192002400 ps
CPU time 36.74 seconds
Started Mar 10 12:38:53 PM PDT 24
Finished Mar 10 12:39:30 PM PDT 24
Peak memory 277076 kb
Host smart-05d74105-7656-4615-9aa5-14f26746f3ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711974298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.2711974298
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1394182595
Short name T334
Test name
Test status
Simulation time 654052500 ps
CPU time 884.23 seconds
Started Mar 10 12:26:07 PM PDT 24
Finished Mar 10 12:40:52 PM PDT 24
Peak memory 260628 kb
Host smart-6cb678c1-a086-4af0-a1a6-e1fffe617008
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394182595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.1394182595
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.1215752819
Short name T383
Test name
Test status
Simulation time 265993500 ps
CPU time 33.4 seconds
Started Mar 10 12:37:45 PM PDT 24
Finished Mar 10 12:38:19 PM PDT 24
Peak memory 272984 kb
Host smart-367d3477-d241-4cbb-95c9-83379c17ed08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215752819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.1215752819
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.3118840119
Short name T59
Test name
Test status
Simulation time 402009416800 ps
CPU time 1746.49 seconds
Started Mar 10 12:35:18 PM PDT 24
Finished Mar 10 01:04:25 PM PDT 24
Peak memory 258500 kb
Host smart-97612b9a-39a6-4964-bee2-7bfe59eb9aef
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118840119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.3118840119
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.2200650551
Short name T76
Test name
Test status
Simulation time 44430100 ps
CPU time 13.74 seconds
Started Mar 10 12:35:26 PM PDT 24
Finished Mar 10 12:35:40 PM PDT 24
Peak memory 277716 kb
Host smart-dbef3428-e551-452a-b29e-51be4923bff3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2200650551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2200650551
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.4102696993
Short name T981
Test name
Test status
Simulation time 2695366300 ps
CPU time 447.23 seconds
Started Mar 10 12:36:28 PM PDT 24
Finished Mar 10 12:43:55 PM PDT 24
Peak memory 320192 kb
Host smart-3e53661f-8900-4031-8250-ce962cf95184
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102696993 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_rw_derr.4102696993
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3765503671
Short name T392
Test name
Test status
Simulation time 31383800 ps
CPU time 29.75 seconds
Started Mar 10 12:35:48 PM PDT 24
Finished Mar 10 12:36:18 PM PDT 24
Peak memory 265956 kb
Host smart-71d8c4ee-7ffa-48d6-a3b0-7b364871ed95
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765503671 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.3765503671
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.1054998974
Short name T167
Test name
Test status
Simulation time 1118210100 ps
CPU time 32.52 seconds
Started Mar 10 12:35:34 PM PDT 24
Finished Mar 10 12:36:07 PM PDT 24
Peak memory 275328 kb
Host smart-d8008d4a-6b4e-445b-8472-7aa70ccde9a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054998974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.1054998974
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2973692636
Short name T333
Test name
Test status
Simulation time 25532000 ps
CPU time 13.41 seconds
Started Mar 10 12:35:25 PM PDT 24
Finished Mar 10 12:35:38 PM PDT 24
Peak memory 264744 kb
Host smart-d9168bc1-4743-4a34-8e25-32eedd10c6aa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973692636 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2973692636
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.2771064552
Short name T362
Test name
Test status
Simulation time 7510837300 ps
CPU time 75.96 seconds
Started Mar 10 12:38:25 PM PDT 24
Finished Mar 10 12:39:41 PM PDT 24
Peak memory 264532 kb
Host smart-0a9d2460-a180-482a-9979-aca82959d4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771064552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.2771064552
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.3274891307
Short name T97
Test name
Test status
Simulation time 2199924800 ps
CPU time 118.89 seconds
Started Mar 10 12:36:14 PM PDT 24
Finished Mar 10 12:38:14 PM PDT 24
Peak memory 264684 kb
Host smart-2ed224ec-daae-4bc0-971f-c37e1166a458
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274891307 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.3274891307
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.1758756968
Short name T303
Test name
Test status
Simulation time 28098500 ps
CPU time 15.99 seconds
Started Mar 10 12:37:04 PM PDT 24
Finished Mar 10 12:37:20 PM PDT 24
Peak memory 273932 kb
Host smart-900fa52b-f901-4cc1-bce0-05259c3c9cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758756968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.1758756968
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.3096527769
Short name T200
Test name
Test status
Simulation time 25871200 ps
CPU time 13.91 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:35:41 PM PDT 24
Peak memory 264880 kb
Host smart-e55e3747-5769-4ac2-a2a2-466e7b9dbcb4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096527769 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.3096527769
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.4220242628
Short name T164
Test name
Test status
Simulation time 859554000 ps
CPU time 1797.85 seconds
Started Mar 10 12:35:03 PM PDT 24
Finished Mar 10 01:05:01 PM PDT 24
Peak memory 264716 kb
Host smart-215fa29c-2e1f-4033-ad1c-5cde82fefc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220242628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.4220242628
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1751907864
Short name T337
Test name
Test status
Simulation time 13218352400 ps
CPU time 921.25 seconds
Started Mar 10 12:26:19 PM PDT 24
Finished Mar 10 12:41:40 PM PDT 24
Peak memory 263324 kb
Host smart-fbc359b5-9ac1-46c1-a1ae-1c88522d2fac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751907864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.1751907864
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.800658765
Short name T311
Test name
Test status
Simulation time 11901521700 ps
CPU time 204.56 seconds
Started Mar 10 12:38:26 PM PDT 24
Finished Mar 10 12:41:51 PM PDT 24
Peak memory 289428 kb
Host smart-e7c7113f-1fa7-4892-b9b5-99b599811e1d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800658765 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.800658765
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.3184648057
Short name T431
Test name
Test status
Simulation time 4255067000 ps
CPU time 953.88 seconds
Started Mar 10 12:35:14 PM PDT 24
Finished Mar 10 12:51:08 PM PDT 24
Peak memory 273912 kb
Host smart-865f9a1c-4ccc-4d29-b14d-0c236ff486c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184648057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3184648057
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2562780448
Short name T475
Test name
Test status
Simulation time 10012043100 ps
CPU time 105.24 seconds
Started Mar 10 12:35:12 PM PDT 24
Finished Mar 10 12:36:57 PM PDT 24
Peak memory 290976 kb
Host smart-bfa2c6be-4e86-4c82-a292-1b105e4ec768
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562780448 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.2562780448
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.1757274601
Short name T553
Test name
Test status
Simulation time 58122900 ps
CPU time 13.45 seconds
Started Mar 10 12:36:43 PM PDT 24
Finished Mar 10 12:36:57 PM PDT 24
Peak memory 264956 kb
Host smart-e7306666-2891-42b4-ab1f-60dee0b889db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757274601 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.1757274601
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.2761740855
Short name T680
Test name
Test status
Simulation time 83702600 ps
CPU time 31.65 seconds
Started Mar 10 12:37:01 PM PDT 24
Finished Mar 10 12:37:33 PM PDT 24
Peak memory 275424 kb
Host smart-5d0c4c60-56f2-4a94-b521-2cd919737769
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761740855 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.2761740855
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.3165956082
Short name T361
Test name
Test status
Simulation time 1433392300 ps
CPU time 60.34 seconds
Started Mar 10 12:38:15 PM PDT 24
Finished Mar 10 12:39:16 PM PDT 24
Peak memory 263540 kb
Host smart-3e6b716d-a782-461b-9cd1-dab10f2436d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165956082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.3165956082
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.3766344941
Short name T365
Test name
Test status
Simulation time 2529298200 ps
CPU time 67.7 seconds
Started Mar 10 12:35:32 PM PDT 24
Finished Mar 10 12:36:40 PM PDT 24
Peak memory 258936 kb
Host smart-f0b88fbb-18b6-4072-b4fd-f6b2c581038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766344941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.3766344941
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.1512690889
Short name T374
Test name
Test status
Simulation time 402124100 ps
CPU time 56.35 seconds
Started Mar 10 12:38:54 PM PDT 24
Finished Mar 10 12:39:50 PM PDT 24
Peak memory 258856 kb
Host smart-2f38e3d3-8749-4388-95fa-8c7ed02fb2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512690889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.1512690889
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.1156225554
Short name T566
Test name
Test status
Simulation time 19480800 ps
CPU time 13.22 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:35:35 PM PDT 24
Peak memory 264792 kb
Host smart-df042376-fff2-4b76-8a84-b56f14789c9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156225554 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.1156225554
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.1507573170
Short name T106
Test name
Test status
Simulation time 4782357200 ps
CPU time 59.73 seconds
Started Mar 10 12:37:28 PM PDT 24
Finished Mar 10 12:38:28 PM PDT 24
Peak memory 262252 kb
Host smart-89efcaf9-6687-4e8e-b1ea-a3d102b8cf8d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507573170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1
507573170
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.812391144
Short name T255
Test name
Test status
Simulation time 63536700 ps
CPU time 18.77 seconds
Started Mar 10 12:25:51 PM PDT 24
Finished Mar 10 12:26:10 PM PDT 24
Peak memory 263224 kb
Host smart-20c1bc34-20a8-44e6-92f8-33a0a6dc2073
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812391144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.812391144
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.3997465329
Short name T223
Test name
Test status
Simulation time 10286500 ps
CPU time 20.2 seconds
Started Mar 10 12:37:34 PM PDT 24
Finished Mar 10 12:37:54 PM PDT 24
Peak memory 273120 kb
Host smart-4132299c-59d3-4ee4-8f21-f1158fafcc82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997465329 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.3997465329
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.3952757492
Short name T683
Test name
Test status
Simulation time 77550200 ps
CPU time 13.8 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:35:36 PM PDT 24
Peak memory 263940 kb
Host smart-dba56b2d-106f-44e7-96f8-adbc43b91eb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952757492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.3952757492
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.1922970940
Short name T1053
Test name
Test status
Simulation time 20522851300 ps
CPU time 216.39 seconds
Started Mar 10 12:37:01 PM PDT 24
Finished Mar 10 12:40:38 PM PDT 24
Peak memory 289372 kb
Host smart-25304e3b-70d7-4d96-a5a1-f0a376a6c995
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922970940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.1922970940
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.1969622229
Short name T109
Test name
Test status
Simulation time 2470526400 ps
CPU time 4802.62 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 01:55:31 PM PDT 24
Peak memory 285744 kb
Host smart-20485c43-cef9-46b5-aec3-5920de861023
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969622229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.1969622229
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.3035512254
Short name T36
Test name
Test status
Simulation time 488648900 ps
CPU time 114.31 seconds
Started Mar 10 12:35:24 PM PDT 24
Finished Mar 10 12:37:19 PM PDT 24
Peak memory 293584 kb
Host smart-86a63974-924e-49cd-85ce-96a34d96b254
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035512254 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.3035512254
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2785789173
Short name T339
Test name
Test status
Simulation time 3261076900 ps
CPU time 383.69 seconds
Started Mar 10 12:26:15 PM PDT 24
Finished Mar 10 12:32:39 PM PDT 24
Peak memory 260748 kb
Host smart-2ca9de0a-9ad5-4673-a4e2-a3fdb8c83269
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785789173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.2785789173
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.691404970
Short name T262
Test name
Test status
Simulation time 183554100 ps
CPU time 19.09 seconds
Started Mar 10 12:26:36 PM PDT 24
Finished Mar 10 12:26:55 PM PDT 24
Peak memory 263224 kb
Host smart-69bf0eef-8d23-464d-b3f9-d776d6a6e186
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691404970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.691404970
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.170446956
Short name T293
Test name
Test status
Simulation time 879778000 ps
CPU time 454.67 seconds
Started Mar 10 12:26:02 PM PDT 24
Finished Mar 10 12:33:38 PM PDT 24
Peak memory 263328 kb
Host smart-19cdbee0-53a9-414a-80ce-e07fedc29182
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170446956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
tl_intg_err.170446956
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.2048810499
Short name T158
Test name
Test status
Simulation time 11275200 ps
CPU time 22.25 seconds
Started Mar 10 12:35:12 PM PDT 24
Finished Mar 10 12:35:35 PM PDT 24
Peak memory 272964 kb
Host smart-8c695730-0d6d-4ce6-af61-7a891f398c4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048810499 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.2048810499
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.1236935386
Short name T349
Test name
Test status
Simulation time 37052800 ps
CPU time 22.27 seconds
Started Mar 10 12:36:43 PM PDT 24
Finished Mar 10 12:37:06 PM PDT 24
Peak memory 279976 kb
Host smart-8eb095cf-a979-4c24-a0a1-1cbb2c2f8dd5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236935386 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.1236935386
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.706698057
Short name T741
Test name
Test status
Simulation time 7760189500 ps
CPU time 68.96 seconds
Started Mar 10 12:36:43 PM PDT 24
Finished Mar 10 12:37:52 PM PDT 24
Peak memory 264064 kb
Host smart-4037f95a-956e-416a-865c-238d278920a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706698057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.706698057
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.1412716300
Short name T159
Test name
Test status
Simulation time 10720700 ps
CPU time 21.51 seconds
Started Mar 10 12:36:53 PM PDT 24
Finished Mar 10 12:37:16 PM PDT 24
Peak memory 279800 kb
Host smart-5d933711-2bf1-466f-82bc-00570416b611
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412716300 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.1412716300
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.4004225293
Short name T390
Test name
Test status
Simulation time 37197000 ps
CPU time 28.56 seconds
Started Mar 10 12:36:47 PM PDT 24
Finished Mar 10 12:37:15 PM PDT 24
Peak memory 273052 kb
Host smart-c931f2d2-d06a-4bdc-b68b-4d529e0c59fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004225293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.4004225293
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.1653578147
Short name T79
Test name
Test status
Simulation time 24188000 ps
CPU time 21.83 seconds
Started Mar 10 12:37:04 PM PDT 24
Finished Mar 10 12:37:26 PM PDT 24
Peak memory 273032 kb
Host smart-2f178598-90a0-4eac-b4c8-8cff5543084b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653578147 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.1653578147
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.1212658288
Short name T358
Test name
Test status
Simulation time 15906700 ps
CPU time 21.59 seconds
Started Mar 10 12:37:44 PM PDT 24
Finished Mar 10 12:38:06 PM PDT 24
Peak memory 273116 kb
Host smart-1a6bb564-19f4-4e32-9068-a9bd7a7a75da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212658288 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.1212658288
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.1983618951
Short name T364
Test name
Test status
Simulation time 2173400000 ps
CPU time 68.95 seconds
Started Mar 10 12:39:16 PM PDT 24
Finished Mar 10 12:40:25 PM PDT 24
Peak memory 258908 kb
Host smart-8296777c-4c68-45fa-800b-f5b38b44917f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983618951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.1983618951
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.33394506
Short name T165
Test name
Test status
Simulation time 63997700 ps
CPU time 132.38 seconds
Started Mar 10 12:38:51 PM PDT 24
Finished Mar 10 12:41:03 PM PDT 24
Peak memory 263304 kb
Host smart-48e986e9-6b77-49f2-a020-17c0ccdb68fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33394506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp
_reset.33394506
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.2102864670
Short name T276
Test name
Test status
Simulation time 64678000 ps
CPU time 69.2 seconds
Started Mar 10 12:35:07 PM PDT 24
Finished Mar 10 12:36:17 PM PDT 24
Peak memory 261632 kb
Host smart-7b7f25a6-907b-4150-8bd1-a8830e651d2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102864670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2102864670
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.740318279
Short name T519
Test name
Test status
Simulation time 40468570700 ps
CPU time 291.51 seconds
Started Mar 10 12:35:17 PM PDT 24
Finished Mar 10 12:40:09 PM PDT 24
Peak memory 264692 kb
Host smart-ac14b997-0e19-4fb7-9bbc-bb0a5e8605b6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740
318279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.740318279
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.4068101151
Short name T190
Test name
Test status
Simulation time 5704499000 ps
CPU time 427.91 seconds
Started Mar 10 12:35:16 PM PDT 24
Finished Mar 10 12:42:25 PM PDT 24
Peak memory 323800 kb
Host smart-20c96832-7d01-46bf-bc69-e8dd6bde7652
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068101151 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_rw_derr.4068101151
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.1953669506
Short name T140
Test name
Test status
Simulation time 160169036000 ps
CPU time 777.63 seconds
Started Mar 10 12:37:36 PM PDT 24
Finished Mar 10 12:50:33 PM PDT 24
Peak memory 258356 kb
Host smart-8538c634-56e0-4382-bfb7-472cb9a6f41e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953669506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.1953669506
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.3422945406
Short name T225
Test name
Test status
Simulation time 18302100 ps
CPU time 13.76 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:35:41 PM PDT 24
Peak memory 264880 kb
Host smart-914030af-e627-4f5a-aa1f-d7899b0e0df2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3422945406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.3422945406
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2518373950
Short name T263
Test name
Test status
Simulation time 3066560600 ps
CPU time 902.83 seconds
Started Mar 10 12:26:04 PM PDT 24
Finished Mar 10 12:41:07 PM PDT 24
Peak memory 263336 kb
Host smart-7a6036ce-447a-4c44-8e40-5169cd7e393e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518373950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.2518373950
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.4185416624
Short name T700
Test name
Test status
Simulation time 24885563400 ps
CPU time 2271.25 seconds
Started Mar 10 12:34:59 PM PDT 24
Finished Mar 10 01:12:53 PM PDT 24
Peak memory 263540 kb
Host smart-87af0958-dc7a-4b22-8000-54ed09fb983b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185416624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.4185416624
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.3270637169
Short name T179
Test name
Test status
Simulation time 247146714300 ps
CPU time 2382.1 seconds
Started Mar 10 12:35:16 PM PDT 24
Finished Mar 10 01:14:58 PM PDT 24
Peak memory 264716 kb
Host smart-3183da04-7c53-4418-b9f5-6dbe751f8102
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270637169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.3270637169
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.1273437004
Short name T126
Test name
Test status
Simulation time 9191511500 ps
CPU time 74.01 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:36:35 PM PDT 24
Peak memory 259212 kb
Host smart-b680d6f2-d72a-47bc-9014-019c16517156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273437004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.1273437004
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.2580239608
Short name T45
Test name
Test status
Simulation time 21797500 ps
CPU time 13.61 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:35:41 PM PDT 24
Peak memory 264880 kb
Host smart-44e4d009-2f80-4ffa-94ec-468e0ee096da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580239608 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.2580239608
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.3211972512
Short name T184
Test name
Test status
Simulation time 45944200 ps
CPU time 80.77 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:36:42 PM PDT 24
Peak memory 261704 kb
Host smart-1cbe51b0-d847-404b-a82b-151e178a3704
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211972512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3211972512
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.2195817588
Short name T199
Test name
Test status
Simulation time 257081916800 ps
CPU time 2790.69 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 01:22:00 PM PDT 24
Peak memory 264540 kb
Host smart-d8dddc31-1378-4dd6-818f-7b3bf17d102d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195817588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.2195817588
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.140263374
Short name T872
Test name
Test status
Simulation time 80820100 ps
CPU time 31.03 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:36:01 PM PDT 24
Peak memory 273048 kb
Host smart-08eff84a-00da-45f7-b1c5-2ed0720715c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140263374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rd_intg.140263374
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.3270927989
Short name T10
Test name
Test status
Simulation time 365017000 ps
CPU time 14.43 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:35:45 PM PDT 24
Peak memory 264764 kb
Host smart-24301195-9318-4f51-8b9d-fd44e734b961
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270927989 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.3270927989
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.487676988
Short name T197
Test name
Test status
Simulation time 251636684400 ps
CPU time 2385.97 seconds
Started Mar 10 12:35:33 PM PDT 24
Finished Mar 10 01:15:20 PM PDT 24
Peak memory 264496 kb
Host smart-1796167c-950c-4407-8baa-6d714c6670bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487676988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.flash_ctrl_host_ctrl_arb.487676988
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.367812249
Short name T1274
Test name
Test status
Simulation time 228253800 ps
CPU time 33.46 seconds
Started Mar 10 12:25:47 PM PDT 24
Finished Mar 10 12:26:22 PM PDT 24
Peak memory 259456 kb
Host smart-304520b6-ab14-477f-901c-e4a3ae770845
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367812249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_aliasing.367812249
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3572043758
Short name T319
Test name
Test status
Simulation time 2480343900 ps
CPU time 69.73 seconds
Started Mar 10 12:25:56 PM PDT 24
Finished Mar 10 12:27:07 PM PDT 24
Peak memory 262128 kb
Host smart-3c736b8e-1e9f-4f21-8cd3-095e57451347
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572043758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.3572043758
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4280254086
Short name T1196
Test name
Test status
Simulation time 66427100 ps
CPU time 25.84 seconds
Started Mar 10 12:25:55 PM PDT 24
Finished Mar 10 12:26:22 PM PDT 24
Peak memory 259524 kb
Host smart-cf0d43b5-2001-4057-9f12-dd6495ecabb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280254086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.4280254086
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.889323557
Short name T1209
Test name
Test status
Simulation time 57873200 ps
CPU time 17.18 seconds
Started Mar 10 12:25:54 PM PDT 24
Finished Mar 10 12:26:12 PM PDT 24
Peak memory 271480 kb
Host smart-a9cb10ba-93ce-46e7-8f57-7570ae8e7a2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889323557 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.889323557
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.672416205
Short name T1186
Test name
Test status
Simulation time 66520600 ps
CPU time 16.32 seconds
Started Mar 10 12:25:53 PM PDT 24
Finished Mar 10 12:26:10 PM PDT 24
Peak memory 259612 kb
Host smart-3eb7e0c2-7d1f-491d-9267-a40be35ca324
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672416205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_csr_rw.672416205
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3980122012
Short name T1244
Test name
Test status
Simulation time 67302100 ps
CPU time 13.57 seconds
Started Mar 10 12:25:56 PM PDT 24
Finished Mar 10 12:26:10 PM PDT 24
Peak memory 259988 kb
Host smart-a6197048-d07d-4496-991d-d1c2006d28b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980122012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3
980122012
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3493776675
Short name T1269
Test name
Test status
Simulation time 110560600 ps
CPU time 13.42 seconds
Started Mar 10 12:25:56 PM PDT 24
Finished Mar 10 12:26:10 PM PDT 24
Peak memory 261624 kb
Host smart-ff911341-c6ac-4f50-a712-8643cff6fef5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493776675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.3493776675
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.901352872
Short name T298
Test name
Test status
Simulation time 396613000 ps
CPU time 18.38 seconds
Started Mar 10 12:25:56 PM PDT 24
Finished Mar 10 12:26:15 PM PDT 24
Peak memory 259540 kb
Host smart-ad25dfa6-f5ac-46e1-b19b-b18e133697b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901352872 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.901352872
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2268243033
Short name T1206
Test name
Test status
Simulation time 21941800 ps
CPU time 15.47 seconds
Started Mar 10 12:25:57 PM PDT 24
Finished Mar 10 12:26:13 PM PDT 24
Peak memory 259292 kb
Host smart-9c933699-d540-4d77-bf4e-602892b7bb76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268243033 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.2268243033
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3955712941
Short name T1147
Test name
Test status
Simulation time 45172400 ps
CPU time 15.4 seconds
Started Mar 10 12:25:46 PM PDT 24
Finished Mar 10 12:26:02 PM PDT 24
Peak memory 259312 kb
Host smart-e8fbfb73-7f82-4823-9785-c1b5169923be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955712941 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.3955712941
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2188189175
Short name T267
Test name
Test status
Simulation time 107209900 ps
CPU time 15.93 seconds
Started Mar 10 12:25:57 PM PDT 24
Finished Mar 10 12:26:13 PM PDT 24
Peak memory 263144 kb
Host smart-5e2cf899-2415-41cf-a004-3607e3649e2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188189175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.2
188189175
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.129520898
Short name T340
Test name
Test status
Simulation time 171172600 ps
CPU time 451.45 seconds
Started Mar 10 12:25:46 PM PDT 24
Finished Mar 10 12:33:18 PM PDT 24
Peak memory 263280 kb
Host smart-53e20348-26f8-47c6-b48b-d0499ac9dead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129520898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
tl_intg_err.129520898
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3095264948
Short name T1214
Test name
Test status
Simulation time 4437817700 ps
CPU time 38.31 seconds
Started Mar 10 12:26:19 PM PDT 24
Finished Mar 10 12:26:58 PM PDT 24
Peak memory 259464 kb
Host smart-0b8f9aeb-f56b-40dd-9fac-c643762c8faa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095264948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.3095264948
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1903628542
Short name T1220
Test name
Test status
Simulation time 5286524600 ps
CPU time 61.22 seconds
Started Mar 10 12:26:04 PM PDT 24
Finished Mar 10 12:27:05 PM PDT 24
Peak memory 259328 kb
Host smart-8a79ea6a-a5d3-4c27-bc08-53c48c03e7e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903628542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.1903628542
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3546293207
Short name T1221
Test name
Test status
Simulation time 50783900 ps
CPU time 30.9 seconds
Started Mar 10 12:25:59 PM PDT 24
Finished Mar 10 12:26:30 PM PDT 24
Peak memory 259516 kb
Host smart-bea552b8-a026-497f-aa22-eb9b28a23bc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546293207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.3546293207
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3237381338
Short name T229
Test name
Test status
Simulation time 49082400 ps
CPU time 15.16 seconds
Started Mar 10 12:26:02 PM PDT 24
Finished Mar 10 12:26:18 PM PDT 24
Peak memory 271460 kb
Host smart-777f1cf0-05de-48c3-a84e-7fd87800a14c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237381338 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3237381338
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1401899275
Short name T1245
Test name
Test status
Simulation time 74881500 ps
CPU time 13.89 seconds
Started Mar 10 12:26:01 PM PDT 24
Finished Mar 10 12:26:16 PM PDT 24
Peak memory 259668 kb
Host smart-263d4701-2fd4-4298-83a1-fc82cb215223
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401899275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.1401899275
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.241924748
Short name T239
Test name
Test status
Simulation time 34475100 ps
CPU time 13.39 seconds
Started Mar 10 12:26:07 PM PDT 24
Finished Mar 10 12:26:21 PM PDT 24
Peak memory 263232 kb
Host smart-582814a4-02e8-4dd7-be16-078c78d3fa6d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241924748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_mem_partial_access.241924748
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4177536046
Short name T1145
Test name
Test status
Simulation time 15363100 ps
CPU time 13.46 seconds
Started Mar 10 12:25:53 PM PDT 24
Finished Mar 10 12:26:07 PM PDT 24
Peak memory 260704 kb
Host smart-8c9e1055-cb0b-48df-9f98-66b0ec52127d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177536046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.4177536046
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3091851524
Short name T1255
Test name
Test status
Simulation time 196517300 ps
CPU time 29.88 seconds
Started Mar 10 12:26:04 PM PDT 24
Finished Mar 10 12:26:34 PM PDT 24
Peak memory 262192 kb
Host smart-5528df62-493a-45c8-b8e3-68b2a5496f41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091851524 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.3091851524
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.94226363
Short name T1184
Test name
Test status
Simulation time 23973400 ps
CPU time 12.88 seconds
Started Mar 10 12:25:59 PM PDT 24
Finished Mar 10 12:26:12 PM PDT 24
Peak memory 259340 kb
Host smart-a4e3430b-5033-48de-b87b-96e89310e6d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94226363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.94226363
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1372931893
Short name T1150
Test name
Test status
Simulation time 35029000 ps
CPU time 15.29 seconds
Started Mar 10 12:25:58 PM PDT 24
Finished Mar 10 12:26:13 PM PDT 24
Peak memory 259392 kb
Host smart-9e9c9cc4-5ba0-4dbd-8fcc-608942a7e29e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372931893 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.1372931893
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3672014040
Short name T1251
Test name
Test status
Simulation time 1366149000 ps
CPU time 758.92 seconds
Started Mar 10 12:25:52 PM PDT 24
Finished Mar 10 12:38:32 PM PDT 24
Peak memory 263316 kb
Host smart-6710ab47-bca6-4fe3-99af-5408bf56236d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672014040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.3672014040
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1999406707
Short name T233
Test name
Test status
Simulation time 50959100 ps
CPU time 14.9 seconds
Started Mar 10 12:26:52 PM PDT 24
Finished Mar 10 12:27:07 PM PDT 24
Peak memory 271572 kb
Host smart-778dbb37-3e69-4911-91e2-6235f4128562
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999406707 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.1999406707
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2693582730
Short name T1267
Test name
Test status
Simulation time 267080100 ps
CPU time 17.53 seconds
Started Mar 10 12:26:14 PM PDT 24
Finished Mar 10 12:26:32 PM PDT 24
Peak memory 259496 kb
Host smart-786729ff-e108-42ea-aec9-d6f32d1e3a4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693582730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.2693582730
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.4113816325
Short name T1217
Test name
Test status
Simulation time 61558700 ps
CPU time 13.57 seconds
Started Mar 10 12:26:06 PM PDT 24
Finished Mar 10 12:26:19 PM PDT 24
Peak memory 261620 kb
Host smart-cc6b4cf3-5c78-481d-8dd5-e3f71bf96468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113816325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
4113816325
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2662164432
Short name T1226
Test name
Test status
Simulation time 998083000 ps
CPU time 34.05 seconds
Started Mar 10 12:26:46 PM PDT 24
Finished Mar 10 12:27:20 PM PDT 24
Peak memory 259624 kb
Host smart-8bbfa69c-8d85-4e81-b0be-a95fd3ae09a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662164432 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.2662164432
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2815339355
Short name T1248
Test name
Test status
Simulation time 12407400 ps
CPU time 15.59 seconds
Started Mar 10 12:26:12 PM PDT 24
Finished Mar 10 12:26:28 PM PDT 24
Peak memory 259428 kb
Host smart-ca4d99c3-e953-4212-9e17-7227fc0bab20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815339355 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.2815339355
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3929808981
Short name T1192
Test name
Test status
Simulation time 47871100 ps
CPU time 15.33 seconds
Started Mar 10 12:26:13 PM PDT 24
Finished Mar 10 12:26:29 PM PDT 24
Peak memory 259428 kb
Host smart-ff8aa96c-cc84-4f4a-bb79-614dd03c7822
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929808981 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.3929808981
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3433329734
Short name T1173
Test name
Test status
Simulation time 360384400 ps
CPU time 15.75 seconds
Started Mar 10 12:26:56 PM PDT 24
Finished Mar 10 12:27:11 PM PDT 24
Peak memory 263228 kb
Host smart-3d0436da-7e6e-4c1b-ae2c-20dbe0f8cc76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433329734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
3433329734
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1933902499
Short name T234
Test name
Test status
Simulation time 1436982400 ps
CPU time 19.02 seconds
Started Mar 10 12:26:11 PM PDT 24
Finished Mar 10 12:26:31 PM PDT 24
Peak memory 276908 kb
Host smart-d4f71288-4afc-46e7-9d5f-28a90b2d0378
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933902499 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1933902499
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3104845122
Short name T1138
Test name
Test status
Simulation time 33457400 ps
CPU time 13.97 seconds
Started Mar 10 12:26:26 PM PDT 24
Finished Mar 10 12:26:41 PM PDT 24
Peak memory 259540 kb
Host smart-1d5278d0-a168-4419-bbfb-bffb36f046f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104845122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.3104845122
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4142489327
Short name T324
Test name
Test status
Simulation time 16612800 ps
CPU time 13.32 seconds
Started Mar 10 12:26:45 PM PDT 24
Finished Mar 10 12:26:58 PM PDT 24
Peak memory 261424 kb
Host smart-0063c013-dedc-40fc-9eb0-06b3e97108c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142489327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
4142489327
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1636541253
Short name T1132
Test name
Test status
Simulation time 305785200 ps
CPU time 19.14 seconds
Started Mar 10 12:26:17 PM PDT 24
Finished Mar 10 12:26:36 PM PDT 24
Peak memory 261640 kb
Host smart-69024c57-f24c-4d4e-b6be-e8580a21373d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636541253 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.1636541253
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1429099787
Short name T1232
Test name
Test status
Simulation time 166714800 ps
CPU time 15.71 seconds
Started Mar 10 12:26:01 PM PDT 24
Finished Mar 10 12:26:23 PM PDT 24
Peak memory 259340 kb
Host smart-34841e14-9555-4fb9-be6c-876533b461b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429099787 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.1429099787
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1566353323
Short name T1216
Test name
Test status
Simulation time 37036900 ps
CPU time 15.3 seconds
Started Mar 10 12:26:16 PM PDT 24
Finished Mar 10 12:26:31 PM PDT 24
Peak memory 259420 kb
Host smart-53ea67b0-0b18-4020-8396-a20b8ef24c75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566353323 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.1566353323
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4034914912
Short name T269
Test name
Test status
Simulation time 32226600 ps
CPU time 15.81 seconds
Started Mar 10 12:26:43 PM PDT 24
Finished Mar 10 12:26:58 PM PDT 24
Peak memory 263308 kb
Host smart-d3e9480f-e605-4c8a-b50d-a31ef8e49b62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034914912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
4034914912
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1096491498
Short name T335
Test name
Test status
Simulation time 742537900 ps
CPU time 459.41 seconds
Started Mar 10 12:26:00 PM PDT 24
Finished Mar 10 12:33:41 PM PDT 24
Peak memory 263284 kb
Host smart-2cad5c16-7317-48ff-bddc-85f4d3ed0baa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096491498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.1096491498
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2488288041
Short name T297
Test name
Test status
Simulation time 807215800 ps
CPU time 17.54 seconds
Started Mar 10 12:26:09 PM PDT 24
Finished Mar 10 12:26:27 PM PDT 24
Peak memory 261504 kb
Host smart-69512772-8929-4aab-99f9-3a63ea6caa3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488288041 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2488288041
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2376014328
Short name T1143
Test name
Test status
Simulation time 53230300 ps
CPU time 17.45 seconds
Started Mar 10 12:26:06 PM PDT 24
Finished Mar 10 12:26:24 PM PDT 24
Peak memory 259424 kb
Host smart-bb8b5bec-aee8-4b48-bb19-ac1178de3afb
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376014328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.2376014328
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.990344812
Short name T1187
Test name
Test status
Simulation time 17600900 ps
CPU time 13.31 seconds
Started Mar 10 12:26:15 PM PDT 24
Finished Mar 10 12:26:28 PM PDT 24
Peak memory 260712 kb
Host smart-f3f2b9da-3905-4587-89fa-7c9dee163dfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990344812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.990344812
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1686944077
Short name T1159
Test name
Test status
Simulation time 379035600 ps
CPU time 33.7 seconds
Started Mar 10 12:26:23 PM PDT 24
Finished Mar 10 12:26:58 PM PDT 24
Peak memory 259644 kb
Host smart-38cad745-140a-42f9-a078-d176f3471f94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686944077 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.1686944077
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1976343513
Short name T1176
Test name
Test status
Simulation time 17538200 ps
CPU time 15.64 seconds
Started Mar 10 12:26:06 PM PDT 24
Finished Mar 10 12:26:22 PM PDT 24
Peak memory 259356 kb
Host smart-20fdaebc-b42c-445f-bb90-911a9ac0ed20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976343513 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1976343513
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2427441984
Short name T1128
Test name
Test status
Simulation time 33511200 ps
CPU time 13.13 seconds
Started Mar 10 12:26:19 PM PDT 24
Finished Mar 10 12:26:33 PM PDT 24
Peak memory 259424 kb
Host smart-db21e5cd-1c13-4769-97d3-873a2380b25f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427441984 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.2427441984
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2212972827
Short name T1273
Test name
Test status
Simulation time 89013900 ps
CPU time 16.17 seconds
Started Mar 10 12:26:13 PM PDT 24
Finished Mar 10 12:26:29 PM PDT 24
Peak memory 263236 kb
Host smart-209b19f5-da77-49c5-bc84-f76680a311f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212972827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
2212972827
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2389063492
Short name T270
Test name
Test status
Simulation time 1291101500 ps
CPU time 751.9 seconds
Started Mar 10 12:26:07 PM PDT 24
Finished Mar 10 12:38:39 PM PDT 24
Peak memory 263184 kb
Host smart-14d412ad-b292-4764-b8ef-1aef0a159361
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389063492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.2389063492
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.138788087
Short name T232
Test name
Test status
Simulation time 245035300 ps
CPU time 17.32 seconds
Started Mar 10 12:26:17 PM PDT 24
Finished Mar 10 12:26:34 PM PDT 24
Peak memory 270664 kb
Host smart-260399b4-6c79-456f-96a5-ace123c5f3ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138788087 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.138788087
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1866169091
Short name T1246
Test name
Test status
Simulation time 35170100 ps
CPU time 16.28 seconds
Started Mar 10 12:26:08 PM PDT 24
Finished Mar 10 12:26:25 PM PDT 24
Peak memory 259500 kb
Host smart-c4b821e7-88af-41ae-8cb2-5b7ac25109c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866169091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.1866169091
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.135773033
Short name T1157
Test name
Test status
Simulation time 39918600 ps
CPU time 13.43 seconds
Started Mar 10 12:26:11 PM PDT 24
Finished Mar 10 12:26:25 PM PDT 24
Peak memory 261544 kb
Host smart-84374082-d4a5-4d88-8e4a-76aa30ce733f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135773033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.135773033
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1969626346
Short name T1165
Test name
Test status
Simulation time 36690700 ps
CPU time 14.86 seconds
Started Mar 10 12:26:11 PM PDT 24
Finished Mar 10 12:26:26 PM PDT 24
Peak memory 263032 kb
Host smart-ff44f419-dc78-4277-b999-368e8c40180c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969626346 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1969626346
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2881022268
Short name T1235
Test name
Test status
Simulation time 18057800 ps
CPU time 15.4 seconds
Started Mar 10 12:26:19 PM PDT 24
Finished Mar 10 12:26:35 PM PDT 24
Peak memory 259420 kb
Host smart-53f2eef1-8b23-4355-9482-75a579eda75e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881022268 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.2881022268
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.498038146
Short name T1270
Test name
Test status
Simulation time 13197900 ps
CPU time 15.98 seconds
Started Mar 10 12:26:11 PM PDT 24
Finished Mar 10 12:26:28 PM PDT 24
Peak memory 259428 kb
Host smart-f4c79489-1dae-403c-acf2-948116c0bfb8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498038146 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.498038146
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3421302047
Short name T268
Test name
Test status
Simulation time 47119800 ps
CPU time 18.15 seconds
Started Mar 10 12:26:08 PM PDT 24
Finished Mar 10 12:26:27 PM PDT 24
Peak memory 263260 kb
Host smart-5d1bacbb-2ae5-4f6e-9d11-86865898d90e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421302047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
3421302047
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1453354347
Short name T1190
Test name
Test status
Simulation time 326355200 ps
CPU time 17.07 seconds
Started Mar 10 12:26:18 PM PDT 24
Finished Mar 10 12:26:35 PM PDT 24
Peak memory 271728 kb
Host smart-5ed60c1d-a8c2-4ca3-8111-038fa0852322
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453354347 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.1453354347
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2357849752
Short name T1208
Test name
Test status
Simulation time 284857400 ps
CPU time 16.69 seconds
Started Mar 10 12:26:33 PM PDT 24
Finished Mar 10 12:26:50 PM PDT 24
Peak memory 259512 kb
Host smart-6e99ad10-be66-44c9-8085-096521e731af
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357849752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.2357849752
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1589492550
Short name T1272
Test name
Test status
Simulation time 44865500 ps
CPU time 13.53 seconds
Started Mar 10 12:26:19 PM PDT 24
Finished Mar 10 12:26:33 PM PDT 24
Peak memory 261760 kb
Host smart-98c0fb95-7449-44d6-b2ad-7a8f677e82eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589492550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
1589492550
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3319728200
Short name T1277
Test name
Test status
Simulation time 91906700 ps
CPU time 17.45 seconds
Started Mar 10 12:26:46 PM PDT 24
Finished Mar 10 12:27:04 PM PDT 24
Peak memory 260976 kb
Host smart-2a2e2c0a-bc02-414f-a20a-bf4746155851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319728200 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.3319728200
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.416477425
Short name T1129
Test name
Test status
Simulation time 40676000 ps
CPU time 15.26 seconds
Started Mar 10 12:26:09 PM PDT 24
Finished Mar 10 12:26:25 PM PDT 24
Peak memory 259544 kb
Host smart-eec71c17-865f-46d0-8df0-f9692f803811
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416477425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.416477425
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3276809396
Short name T1230
Test name
Test status
Simulation time 13795000 ps
CPU time 15.69 seconds
Started Mar 10 12:26:19 PM PDT 24
Finished Mar 10 12:26:35 PM PDT 24
Peak memory 259424 kb
Host smart-2d49f92c-d8a0-4745-b7fe-894f5823ffc7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276809396 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.3276809396
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2541667650
Short name T264
Test name
Test status
Simulation time 99868700 ps
CPU time 18.56 seconds
Started Mar 10 12:26:09 PM PDT 24
Finished Mar 10 12:26:29 PM PDT 24
Peak memory 263200 kb
Host smart-cb81c6ed-91c0-47b3-a238-b2fc0e2fb36b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541667650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
2541667650
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.876689798
Short name T1215
Test name
Test status
Simulation time 192253700 ps
CPU time 16.77 seconds
Started Mar 10 12:26:18 PM PDT 24
Finished Mar 10 12:26:35 PM PDT 24
Peak memory 263236 kb
Host smart-26d5e392-bf11-441a-b3fd-27f37173326d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876689798 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.876689798
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3065977554
Short name T1205
Test name
Test status
Simulation time 145395400 ps
CPU time 14.29 seconds
Started Mar 10 12:26:26 PM PDT 24
Finished Mar 10 12:26:42 PM PDT 24
Peak memory 263288 kb
Host smart-78c41bea-aa78-4966-8847-49af763bca08
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065977554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.3065977554
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3529217389
Short name T1207
Test name
Test status
Simulation time 58954000 ps
CPU time 13.75 seconds
Started Mar 10 12:26:22 PM PDT 24
Finished Mar 10 12:26:36 PM PDT 24
Peak memory 260768 kb
Host smart-f92ceb9a-6d88-451b-b0fe-db255399413e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529217389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
3529217389
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1673554519
Short name T58
Test name
Test status
Simulation time 348317500 ps
CPU time 35.96 seconds
Started Mar 10 12:26:31 PM PDT 24
Finished Mar 10 12:27:08 PM PDT 24
Peak memory 259548 kb
Host smart-eb2cbfd7-b699-4514-be68-f6c1f55455c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673554519 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.1673554519
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.284593706
Short name T1261
Test name
Test status
Simulation time 11991300 ps
CPU time 13.34 seconds
Started Mar 10 12:26:19 PM PDT 24
Finished Mar 10 12:26:33 PM PDT 24
Peak memory 259400 kb
Host smart-62016801-ea35-4838-b25f-874a035e6437
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284593706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.284593706
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2286292075
Short name T1127
Test name
Test status
Simulation time 15098600 ps
CPU time 15.7 seconds
Started Mar 10 12:26:40 PM PDT 24
Finished Mar 10 12:26:56 PM PDT 24
Peak memory 259392 kb
Host smart-d1369dc6-261a-42ea-b249-2a68ff72307e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286292075 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.2286292075
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.208189780
Short name T266
Test name
Test status
Simulation time 37907700 ps
CPU time 16.24 seconds
Started Mar 10 12:26:27 PM PDT 24
Finished Mar 10 12:26:43 PM PDT 24
Peak memory 263184 kb
Host smart-d3d5ffb3-9273-46f3-be2c-306ca3ea36ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208189780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.208189780
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3526215022
Short name T1268
Test name
Test status
Simulation time 1633013800 ps
CPU time 464.48 seconds
Started Mar 10 12:26:21 PM PDT 24
Finished Mar 10 12:34:06 PM PDT 24
Peak memory 263336 kb
Host smart-41998b07-f545-478c-97bc-0a191f65b2be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526215022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.3526215022
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3495233237
Short name T265
Test name
Test status
Simulation time 214732300 ps
CPU time 14.94 seconds
Started Mar 10 12:26:30 PM PDT 24
Finished Mar 10 12:26:46 PM PDT 24
Peak memory 263272 kb
Host smart-cf6e0804-280a-465f-9f87-6f33907155f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495233237 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.3495233237
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1519415628
Short name T1249
Test name
Test status
Simulation time 126753900 ps
CPU time 16.75 seconds
Started Mar 10 12:26:26 PM PDT 24
Finished Mar 10 12:26:44 PM PDT 24
Peak memory 259544 kb
Host smart-0d8d9b9a-f8ae-4c67-b03a-d1ee2d7232fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519415628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.1519415628
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1955566402
Short name T1167
Test name
Test status
Simulation time 14328000 ps
CPU time 13.13 seconds
Started Mar 10 12:26:25 PM PDT 24
Finished Mar 10 12:26:40 PM PDT 24
Peak memory 261700 kb
Host smart-9a8fc8f5-8d80-434e-81a3-0141f6383100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955566402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
1955566402
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1728403911
Short name T57
Test name
Test status
Simulation time 69878700 ps
CPU time 34.56 seconds
Started Mar 10 12:26:26 PM PDT 24
Finished Mar 10 12:27:02 PM PDT 24
Peak memory 259584 kb
Host smart-60a489fe-f74b-43c8-b926-19c78d5d7791
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728403911 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.1728403911
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.435814933
Short name T1199
Test name
Test status
Simulation time 20207900 ps
CPU time 13.18 seconds
Started Mar 10 12:26:17 PM PDT 24
Finished Mar 10 12:26:30 PM PDT 24
Peak memory 259420 kb
Host smart-70d6e09c-a5c3-44f4-bef9-b1fc31a16280
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435814933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.435814933
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1332243885
Short name T1164
Test name
Test status
Simulation time 13149600 ps
CPU time 15.8 seconds
Started Mar 10 12:26:36 PM PDT 24
Finished Mar 10 12:26:52 PM PDT 24
Peak memory 259416 kb
Host smart-123c40ec-de9f-41f5-8ff8-cab053b1e665
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332243885 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.1332243885
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2624583138
Short name T341
Test name
Test status
Simulation time 185443400 ps
CPU time 386.3 seconds
Started Mar 10 12:26:17 PM PDT 24
Finished Mar 10 12:32:43 PM PDT 24
Peak memory 263296 kb
Host smart-c7570e4c-8798-4caa-a714-a5183fa8a12d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624583138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.2624583138
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3844922884
Short name T1239
Test name
Test status
Simulation time 50574000 ps
CPU time 14.72 seconds
Started Mar 10 12:26:19 PM PDT 24
Finished Mar 10 12:26:33 PM PDT 24
Peak memory 270484 kb
Host smart-693626bf-33bf-4fab-abad-3ef2bce53d5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844922884 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.3844922884
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1052951153
Short name T1271
Test name
Test status
Simulation time 54712600 ps
CPU time 17.21 seconds
Started Mar 10 12:26:23 PM PDT 24
Finished Mar 10 12:26:40 PM PDT 24
Peak memory 259660 kb
Host smart-2c952384-3752-48ea-86c4-6791250f8581
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052951153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.1052951153
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1606384379
Short name T1242
Test name
Test status
Simulation time 47772700 ps
CPU time 13.41 seconds
Started Mar 10 12:26:37 PM PDT 24
Finished Mar 10 12:26:50 PM PDT 24
Peak memory 261468 kb
Host smart-891071e5-a077-4a5a-b6c9-ccb063f14e68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606384379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
1606384379
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2888633917
Short name T296
Test name
Test status
Simulation time 833413500 ps
CPU time 19.16 seconds
Started Mar 10 12:26:33 PM PDT 24
Finished Mar 10 12:26:53 PM PDT 24
Peak memory 261048 kb
Host smart-0918c792-848d-4d00-8c7d-1e2db03ba352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888633917 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.2888633917
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.351543849
Short name T1153
Test name
Test status
Simulation time 12379800 ps
CPU time 15.69 seconds
Started Mar 10 12:26:42 PM PDT 24
Finished Mar 10 12:26:57 PM PDT 24
Peak memory 259372 kb
Host smart-42bd6db8-5e11-418e-bbdd-04b4f83fa342
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351543849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.351543849
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3154625692
Short name T1262
Test name
Test status
Simulation time 56840600 ps
CPU time 15.87 seconds
Started Mar 10 12:26:33 PM PDT 24
Finished Mar 10 12:26:49 PM PDT 24
Peak memory 259372 kb
Host smart-8527ff9d-11b0-4b50-9531-daaf65a886a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154625692 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.3154625692
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2270890919
Short name T261
Test name
Test status
Simulation time 298565200 ps
CPU time 18.85 seconds
Started Mar 10 12:26:23 PM PDT 24
Finished Mar 10 12:26:43 PM PDT 24
Peak memory 263216 kb
Host smart-477bf89f-548c-4dc8-814f-279073c4b672
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270890919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
2270890919
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3065594081
Short name T1250
Test name
Test status
Simulation time 732997300 ps
CPU time 378.09 seconds
Started Mar 10 12:26:13 PM PDT 24
Finished Mar 10 12:32:31 PM PDT 24
Peak memory 263296 kb
Host smart-7f6b9591-16c4-4f42-926f-f860ce8ef41d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065594081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.3065594081
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2811375147
Short name T1265
Test name
Test status
Simulation time 39668200 ps
CPU time 19.44 seconds
Started Mar 10 12:26:29 PM PDT 24
Finished Mar 10 12:26:49 PM PDT 24
Peak memory 278128 kb
Host smart-c8a1cbb5-85c0-4698-b542-ffb1dbaa94d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811375147 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.2811375147
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1270068912
Short name T176
Test name
Test status
Simulation time 102085700 ps
CPU time 14.55 seconds
Started Mar 10 12:26:39 PM PDT 24
Finished Mar 10 12:26:54 PM PDT 24
Peak memory 259544 kb
Host smart-94fd1075-e054-4a3e-b08c-5fab35caff8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270068912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.1270068912
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3003542639
Short name T1222
Test name
Test status
Simulation time 19822500 ps
CPU time 13.39 seconds
Started Mar 10 12:26:46 PM PDT 24
Finished Mar 10 12:26:59 PM PDT 24
Peak memory 261620 kb
Host smart-8216d4cb-c6b4-40ef-9dd6-4b1aee219f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003542639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3003542639
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3927663395
Short name T1179
Test name
Test status
Simulation time 108232400 ps
CPU time 19.1 seconds
Started Mar 10 12:26:20 PM PDT 24
Finished Mar 10 12:26:40 PM PDT 24
Peak memory 261276 kb
Host smart-81100e96-90df-4121-9e77-3ba4364eee0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927663395 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.3927663395
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2580401585
Short name T1195
Test name
Test status
Simulation time 33843000 ps
CPU time 15.58 seconds
Started Mar 10 12:26:26 PM PDT 24
Finished Mar 10 12:26:43 PM PDT 24
Peak memory 259384 kb
Host smart-0b5bcef0-10e3-4176-ab6a-8c59869aa58a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580401585 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.2580401585
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3091999892
Short name T1233
Test name
Test status
Simulation time 30617200 ps
CPU time 13.12 seconds
Started Mar 10 12:26:36 PM PDT 24
Finished Mar 10 12:26:49 PM PDT 24
Peak memory 259436 kb
Host smart-d2233ba3-fb7c-4945-b29d-ea8cec85fb2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091999892 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.3091999892
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3868705197
Short name T216
Test name
Test status
Simulation time 3001036600 ps
CPU time 756.75 seconds
Started Mar 10 12:26:34 PM PDT 24
Finished Mar 10 12:39:11 PM PDT 24
Peak memory 263308 kb
Host smart-1b6f43df-b5d8-4adc-afb5-b0b5b87dfd44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868705197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.3868705197
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.612742734
Short name T1252
Test name
Test status
Simulation time 284993200 ps
CPU time 18.93 seconds
Started Mar 10 12:26:37 PM PDT 24
Finished Mar 10 12:26:56 PM PDT 24
Peak memory 271528 kb
Host smart-bee7630e-889a-43ef-ac5c-a1b8ff0a8ca7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612742734 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.612742734
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2924816017
Short name T1201
Test name
Test status
Simulation time 54194800 ps
CPU time 14.63 seconds
Started Mar 10 12:26:32 PM PDT 24
Finished Mar 10 12:26:47 PM PDT 24
Peak memory 259556 kb
Host smart-65f716df-917e-496a-ad5a-39c323ecad8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924816017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.2924816017
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4017189957
Short name T1204
Test name
Test status
Simulation time 31332800 ps
CPU time 13.3 seconds
Started Mar 10 12:26:33 PM PDT 24
Finished Mar 10 12:26:47 PM PDT 24
Peak memory 261500 kb
Host smart-d37e9014-d761-440a-b43c-fdd4c6003d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017189957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
4017189957
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2033978025
Short name T1155
Test name
Test status
Simulation time 130158200 ps
CPU time 18.03 seconds
Started Mar 10 12:26:41 PM PDT 24
Finished Mar 10 12:26:59 PM PDT 24
Peak memory 261512 kb
Host smart-6d59e222-7e12-4dfc-a45e-ce46a01ddba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033978025 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.2033978025
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1497575543
Short name T1203
Test name
Test status
Simulation time 23015500 ps
CPU time 15.74 seconds
Started Mar 10 12:26:26 PM PDT 24
Finished Mar 10 12:26:43 PM PDT 24
Peak memory 259408 kb
Host smart-38b87955-6f35-4bff-8b2a-c5690fee2f03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497575543 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.1497575543
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2074439523
Short name T1225
Test name
Test status
Simulation time 32397200 ps
CPU time 15.52 seconds
Started Mar 10 12:26:31 PM PDT 24
Finished Mar 10 12:26:47 PM PDT 24
Peak memory 259676 kb
Host smart-562e5d38-c3c6-414d-9e58-414b70680cd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074439523 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2074439523
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2290608275
Short name T292
Test name
Test status
Simulation time 813233800 ps
CPU time 38.65 seconds
Started Mar 10 12:25:57 PM PDT 24
Finished Mar 10 12:26:36 PM PDT 24
Peak memory 259556 kb
Host smart-05ed6dae-4b38-4d77-9f41-f7347153e9b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290608275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.2290608275
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4268122382
Short name T1254
Test name
Test status
Simulation time 1283074400 ps
CPU time 36.74 seconds
Started Mar 10 12:26:37 PM PDT 24
Finished Mar 10 12:27:14 PM PDT 24
Peak memory 259544 kb
Host smart-9cb288ef-6107-480e-aab8-980b0621fb26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268122382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.4268122382
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1487633159
Short name T1169
Test name
Test status
Simulation time 48513200 ps
CPU time 45.54 seconds
Started Mar 10 12:26:01 PM PDT 24
Finished Mar 10 12:26:48 PM PDT 24
Peak memory 259516 kb
Host smart-95e81c06-9f6b-4b2a-98a8-da8e0f45b0f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487633159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.1487633159
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2652919321
Short name T228
Test name
Test status
Simulation time 142564200 ps
CPU time 18.66 seconds
Started Mar 10 12:25:57 PM PDT 24
Finished Mar 10 12:26:16 PM PDT 24
Peak memory 271404 kb
Host smart-49986da1-cfd0-4beb-970a-933a7ad2d2b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652919321 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2652919321
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3884639154
Short name T1191
Test name
Test status
Simulation time 147637600 ps
CPU time 16.33 seconds
Started Mar 10 12:26:01 PM PDT 24
Finished Mar 10 12:26:18 PM PDT 24
Peak memory 259808 kb
Host smart-83a8c451-3103-4868-bcfd-adc65d30a956
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884639154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.3884639154
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3897621995
Short name T1202
Test name
Test status
Simulation time 108198300 ps
CPU time 13.45 seconds
Started Mar 10 12:25:57 PM PDT 24
Finished Mar 10 12:26:10 PM PDT 24
Peak memory 261676 kb
Host smart-0aaeb526-df74-485c-80bb-0a47958e248e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897621995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.3
897621995
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2502485421
Short name T240
Test name
Test status
Simulation time 30984000 ps
CPU time 13.14 seconds
Started Mar 10 12:26:02 PM PDT 24
Finished Mar 10 12:26:16 PM PDT 24
Peak memory 263160 kb
Host smart-b30a3950-501f-476c-b4b3-6f4e4cd7cf78
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502485421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.2502485421
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4149330435
Short name T1264
Test name
Test status
Simulation time 48945300 ps
CPU time 13.27 seconds
Started Mar 10 12:26:06 PM PDT 24
Finished Mar 10 12:26:20 PM PDT 24
Peak memory 261640 kb
Host smart-f424f4d6-ccef-46ba-9381-28df831f34bf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149330435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.4149330435
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3299231283
Short name T1200
Test name
Test status
Simulation time 248931800 ps
CPU time 33.67 seconds
Started Mar 10 12:26:01 PM PDT 24
Finished Mar 10 12:26:36 PM PDT 24
Peak memory 261504 kb
Host smart-0ff63818-f73c-4702-b4af-fbbc7594c04a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299231283 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.3299231283
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2654685008
Short name T1193
Test name
Test status
Simulation time 15507700 ps
CPU time 15.37 seconds
Started Mar 10 12:26:02 PM PDT 24
Finished Mar 10 12:26:18 PM PDT 24
Peak memory 259352 kb
Host smart-78729c8b-9b0a-4a08-9ccd-9f642762aa0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654685008 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2654685008
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2097474856
Short name T1171
Test name
Test status
Simulation time 24115900 ps
CPU time 12.94 seconds
Started Mar 10 12:26:03 PM PDT 24
Finished Mar 10 12:26:16 PM PDT 24
Peak memory 259412 kb
Host smart-54da2cc3-14e2-4960-b15a-836eeda48ec0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097474856 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2097474856
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2036542989
Short name T1213
Test name
Test status
Simulation time 248890500 ps
CPU time 17.84 seconds
Started Mar 10 12:26:02 PM PDT 24
Finished Mar 10 12:26:21 PM PDT 24
Peak memory 260108 kb
Host smart-4e9d369b-1d58-4696-8838-b46b35326f86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036542989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.2
036542989
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3153651153
Short name T342
Test name
Test status
Simulation time 2997690000 ps
CPU time 385.51 seconds
Started Mar 10 12:26:09 PM PDT 24
Finished Mar 10 12:32:36 PM PDT 24
Peak memory 263308 kb
Host smart-bb129d33-100a-48ef-a98d-dbe82d67da5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153651153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.3153651153
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3654646409
Short name T1140
Test name
Test status
Simulation time 42858200 ps
CPU time 13.72 seconds
Started Mar 10 12:26:27 PM PDT 24
Finished Mar 10 12:26:42 PM PDT 24
Peak memory 261424 kb
Host smart-6b2f041c-1095-4ee7-abec-b490572909bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654646409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
3654646409
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2516158289
Short name T1152
Test name
Test status
Simulation time 36783300 ps
CPU time 13.76 seconds
Started Mar 10 12:26:32 PM PDT 24
Finished Mar 10 12:26:46 PM PDT 24
Peak memory 261460 kb
Host smart-93f1da86-2712-4f32-bff1-032b45ca74f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516158289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
2516158289
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3876964879
Short name T1234
Test name
Test status
Simulation time 44369500 ps
CPU time 13.36 seconds
Started Mar 10 12:26:36 PM PDT 24
Finished Mar 10 12:26:50 PM PDT 24
Peak memory 261572 kb
Host smart-6af01058-dcee-4517-8c37-b98129f7c646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876964879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
3876964879
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2713007926
Short name T1156
Test name
Test status
Simulation time 36150800 ps
CPU time 13.37 seconds
Started Mar 10 12:26:38 PM PDT 24
Finished Mar 10 12:26:52 PM PDT 24
Peak memory 261588 kb
Host smart-4dcfda6f-c718-4eb9-a3e9-2b12c2d4988b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713007926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
2713007926
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4285957921
Short name T1158
Test name
Test status
Simulation time 16325700 ps
CPU time 13.91 seconds
Started Mar 10 12:26:34 PM PDT 24
Finished Mar 10 12:26:48 PM PDT 24
Peak memory 261472 kb
Host smart-4b7d9ca5-5328-4ff6-b3fb-9465a3bac355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285957921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
4285957921
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.4238773284
Short name T1238
Test name
Test status
Simulation time 52557000 ps
CPU time 13.35 seconds
Started Mar 10 12:26:37 PM PDT 24
Finished Mar 10 12:26:51 PM PDT 24
Peak memory 261612 kb
Host smart-784a5cda-55e2-4730-87dd-5c89d834435d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238773284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
4238773284
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.4125676165
Short name T1142
Test name
Test status
Simulation time 42314900 ps
CPU time 13.45 seconds
Started Mar 10 12:26:29 PM PDT 24
Finished Mar 10 12:26:43 PM PDT 24
Peak memory 261584 kb
Host smart-fb8f7d2e-c22a-431c-91ba-79a5915e241d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125676165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
4125676165
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2514789657
Short name T258
Test name
Test status
Simulation time 46354200 ps
CPU time 13.4 seconds
Started Mar 10 12:26:30 PM PDT 24
Finished Mar 10 12:26:44 PM PDT 24
Peak memory 261612 kb
Host smart-15930160-fa9f-4974-a271-58bf6a00f99a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514789657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
2514789657
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2425188316
Short name T1182
Test name
Test status
Simulation time 32565100 ps
CPU time 13.6 seconds
Started Mar 10 12:26:35 PM PDT 24
Finished Mar 10 12:26:49 PM PDT 24
Peak memory 261572 kb
Host smart-c1fa7262-7fb4-4f08-95e3-10255eec5dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425188316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
2425188316
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.790449228
Short name T1185
Test name
Test status
Simulation time 18295000 ps
CPU time 13.25 seconds
Started Mar 10 12:26:36 PM PDT 24
Finished Mar 10 12:26:50 PM PDT 24
Peak memory 261660 kb
Host smart-68eaa6df-c3de-465c-9af7-6d5681a903a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790449228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.790449228
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.4251358691
Short name T1177
Test name
Test status
Simulation time 7266527400 ps
CPU time 34.94 seconds
Started Mar 10 12:26:07 PM PDT 24
Finished Mar 10 12:26:42 PM PDT 24
Peak memory 259584 kb
Host smart-b2e3ef7e-3b01-4099-b753-e4ff8039368a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251358691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.4251358691
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.122555549
Short name T1148
Test name
Test status
Simulation time 4608420000 ps
CPU time 43.59 seconds
Started Mar 10 12:25:59 PM PDT 24
Finished Mar 10 12:26:42 PM PDT 24
Peak memory 259600 kb
Host smart-17d6c409-c926-450f-8e0d-beb98bdbaed3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122555549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_bit_bash.122555549
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3768473236
Short name T1160
Test name
Test status
Simulation time 40447800 ps
CPU time 30.67 seconds
Started Mar 10 12:26:13 PM PDT 24
Finished Mar 10 12:26:44 PM PDT 24
Peak memory 259652 kb
Host smart-ecb3885a-a73e-4485-a478-61f672a22d83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768473236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3768473236
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3004987118
Short name T1183
Test name
Test status
Simulation time 318435700 ps
CPU time 16.44 seconds
Started Mar 10 12:25:57 PM PDT 24
Finished Mar 10 12:26:14 PM PDT 24
Peak memory 271524 kb
Host smart-5efda33e-fa07-418c-a77b-7f20197ab58c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004987118 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.3004987118
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2190780788
Short name T1197
Test name
Test status
Simulation time 134494100 ps
CPU time 15.02 seconds
Started Mar 10 12:26:06 PM PDT 24
Finished Mar 10 12:26:21 PM PDT 24
Peak memory 259556 kb
Host smart-4e7c726e-9d45-4aff-a1b3-1f2e1482eec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190780788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.2190780788
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1008918696
Short name T323
Test name
Test status
Simulation time 52045600 ps
CPU time 13.67 seconds
Started Mar 10 12:25:59 PM PDT 24
Finished Mar 10 12:26:13 PM PDT 24
Peak memory 261768 kb
Host smart-c6417c57-9c79-49c5-a36b-ed82d16c6b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008918696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.1
008918696
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1766052478
Short name T242
Test name
Test status
Simulation time 58824000 ps
CPU time 13.88 seconds
Started Mar 10 12:25:56 PM PDT 24
Finished Mar 10 12:26:10 PM PDT 24
Peak memory 263096 kb
Host smart-8a311f0c-27d4-4cc2-9777-88f5b6bb85bb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766052478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.1766052478
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.258632430
Short name T1131
Test name
Test status
Simulation time 23474900 ps
CPU time 13.26 seconds
Started Mar 10 12:26:04 PM PDT 24
Finished Mar 10 12:26:18 PM PDT 24
Peak memory 261612 kb
Host smart-6906bd3c-010f-48a2-8924-4aebe0a50bc0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258632430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem
_walk.258632430
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3335800649
Short name T291
Test name
Test status
Simulation time 849432000 ps
CPU time 19.52 seconds
Started Mar 10 12:26:35 PM PDT 24
Finished Mar 10 12:26:55 PM PDT 24
Peak memory 259488 kb
Host smart-016cb63d-5e5d-4562-872f-d259d06aa0b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335800649 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.3335800649
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1793166633
Short name T1144
Test name
Test status
Simulation time 14388400 ps
CPU time 15.78 seconds
Started Mar 10 12:25:56 PM PDT 24
Finished Mar 10 12:26:12 PM PDT 24
Peak memory 259416 kb
Host smart-de433e2b-c4bb-4bff-95cb-ad0a7e8a5973
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793166633 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.1793166633
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.222185672
Short name T1224
Test name
Test status
Simulation time 40333800 ps
CPU time 15.49 seconds
Started Mar 10 12:25:58 PM PDT 24
Finished Mar 10 12:26:14 PM PDT 24
Peak memory 259412 kb
Host smart-a0561d5e-e3dd-4284-b1d3-b35e4bc47800
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222185672 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.222185672
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.467440679
Short name T1223
Test name
Test status
Simulation time 61516400 ps
CPU time 19.1 seconds
Started Mar 10 12:25:59 PM PDT 24
Finished Mar 10 12:26:19 PM PDT 24
Peak memory 263256 kb
Host smart-0deebdbb-b24d-4321-bdcc-d4a994c3f93e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467440679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.467440679
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.864669012
Short name T338
Test name
Test status
Simulation time 358676900 ps
CPU time 452.46 seconds
Started Mar 10 12:26:01 PM PDT 24
Finished Mar 10 12:33:35 PM PDT 24
Peak memory 263428 kb
Host smart-fb4ff90f-28ba-4ea3-aa6e-628b8c11acdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864669012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_
tl_intg_err.864669012
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3338508149
Short name T1211
Test name
Test status
Simulation time 30412200 ps
CPU time 13.84 seconds
Started Mar 10 12:26:34 PM PDT 24
Finished Mar 10 12:26:48 PM PDT 24
Peak memory 259924 kb
Host smart-08a2b972-00a2-4a3b-92ec-240f7533ea86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338508149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
3338508149
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.773733534
Short name T1130
Test name
Test status
Simulation time 26556100 ps
CPU time 13.08 seconds
Started Mar 10 12:28:25 PM PDT 24
Finished Mar 10 12:28:38 PM PDT 24
Peak memory 261640 kb
Host smart-dd50577c-5ea0-4d30-9ee0-5e14dd2d3853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773733534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.773733534
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3538404995
Short name T1194
Test name
Test status
Simulation time 149722400 ps
CPU time 13.71 seconds
Started Mar 10 12:26:42 PM PDT 24
Finished Mar 10 12:26:56 PM PDT 24
Peak memory 261680 kb
Host smart-3c7aaef9-f471-495b-8431-eb107566d117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538404995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
3538404995
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3920278603
Short name T1236
Test name
Test status
Simulation time 14652800 ps
CPU time 13.38 seconds
Started Mar 10 12:26:35 PM PDT 24
Finished Mar 10 12:26:49 PM PDT 24
Peak memory 261436 kb
Host smart-2b73e9a0-2096-4638-809b-14c27e60cd93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920278603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
3920278603
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3523696552
Short name T1259
Test name
Test status
Simulation time 18669600 ps
CPU time 13.35 seconds
Started Mar 10 12:26:37 PM PDT 24
Finished Mar 10 12:26:50 PM PDT 24
Peak memory 259852 kb
Host smart-df8c115a-09ae-4b2a-907d-a08bce25deee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523696552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
3523696552
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1600901149
Short name T1189
Test name
Test status
Simulation time 16060900 ps
CPU time 13.53 seconds
Started Mar 10 12:26:35 PM PDT 24
Finished Mar 10 12:26:49 PM PDT 24
Peak memory 261632 kb
Host smart-f83bb580-0f67-447d-88ba-36550ee9e27f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600901149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
1600901149
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.744968790
Short name T1146
Test name
Test status
Simulation time 49908900 ps
CPU time 13.57 seconds
Started Mar 10 12:26:31 PM PDT 24
Finished Mar 10 12:26:45 PM PDT 24
Peak memory 261476 kb
Host smart-2ef420af-dee6-4d51-b688-90678587c1af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744968790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.744968790
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3972419229
Short name T321
Test name
Test status
Simulation time 198594100 ps
CPU time 13.6 seconds
Started Mar 10 12:26:33 PM PDT 24
Finished Mar 10 12:26:47 PM PDT 24
Peak memory 261520 kb
Host smart-71d5bdf3-3b5b-413a-b4d5-18d57d0a5f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972419229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
3972419229
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1743764258
Short name T1163
Test name
Test status
Simulation time 46209000 ps
CPU time 13.3 seconds
Started Mar 10 12:26:35 PM PDT 24
Finished Mar 10 12:26:48 PM PDT 24
Peak memory 261600 kb
Host smart-2e36cba1-6526-4f48-94af-a22c7735586d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743764258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
1743764258
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3180456999
Short name T1180
Test name
Test status
Simulation time 1711425900 ps
CPU time 37.22 seconds
Started Mar 10 12:26:41 PM PDT 24
Finished Mar 10 12:27:18 PM PDT 24
Peak memory 259552 kb
Host smart-5881dbc9-b653-4df4-9f8d-1182c0f114e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180456999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.3180456999
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2819917081
Short name T1181
Test name
Test status
Simulation time 2381102800 ps
CPU time 67.03 seconds
Started Mar 10 12:26:40 PM PDT 24
Finished Mar 10 12:27:47 PM PDT 24
Peak memory 259524 kb
Host smart-31ec0076-bd79-4cad-a608-3fe3ce89e6fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819917081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.2819917081
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3830362901
Short name T1263
Test name
Test status
Simulation time 247191100 ps
CPU time 45.86 seconds
Started Mar 10 12:26:44 PM PDT 24
Finished Mar 10 12:27:30 PM PDT 24
Peak memory 259648 kb
Host smart-b7757951-16b8-4aef-8bd4-1a055823e4aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830362901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.3830362901
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2242967317
Short name T178
Test name
Test status
Simulation time 92754600 ps
CPU time 17.85 seconds
Started Mar 10 12:26:00 PM PDT 24
Finished Mar 10 12:26:20 PM PDT 24
Peak memory 276456 kb
Host smart-bad16154-fd87-4086-8d3a-7d6f9e4af550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242967317 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.2242967317
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1402437316
Short name T1229
Test name
Test status
Simulation time 92618000 ps
CPU time 16.28 seconds
Started Mar 10 12:26:00 PM PDT 24
Finished Mar 10 12:26:18 PM PDT 24
Peak memory 259560 kb
Host smart-05ab5625-c041-4e28-93ea-a73723d235b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402437316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.1402437316
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2276923880
Short name T1174
Test name
Test status
Simulation time 15728900 ps
CPU time 13.55 seconds
Started Mar 10 12:26:40 PM PDT 24
Finished Mar 10 12:26:54 PM PDT 24
Peak memory 259976 kb
Host smart-5849c5ae-419f-4f2e-9eeb-6c9f4a2c6c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276923880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2
276923880
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3534522026
Short name T241
Test name
Test status
Simulation time 17699500 ps
CPU time 13.48 seconds
Started Mar 10 12:25:56 PM PDT 24
Finished Mar 10 12:26:10 PM PDT 24
Peak memory 262564 kb
Host smart-7ece2a11-5333-46ff-a710-c6f9c7fd4f41
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534522026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.3534522026
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3928818903
Short name T1141
Test name
Test status
Simulation time 84467100 ps
CPU time 13.03 seconds
Started Mar 10 12:26:01 PM PDT 24
Finished Mar 10 12:26:15 PM PDT 24
Peak memory 260796 kb
Host smart-cce60681-cfe9-49d4-9584-ab9bce99bd04
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928818903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.3928818903
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1869427754
Short name T1275
Test name
Test status
Simulation time 354925400 ps
CPU time 17.84 seconds
Started Mar 10 12:26:02 PM PDT 24
Finished Mar 10 12:26:20 PM PDT 24
Peak memory 259580 kb
Host smart-da7d96d8-c130-429a-bb94-d666dac80109
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869427754 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.1869427754
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.388558220
Short name T1228
Test name
Test status
Simulation time 16389200 ps
CPU time 13.47 seconds
Started Mar 10 12:26:06 PM PDT 24
Finished Mar 10 12:26:20 PM PDT 24
Peak memory 259372 kb
Host smart-fd8f858d-e51c-4f77-82d7-3ad436d1e5b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388558220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.388558220
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3976417045
Short name T1161
Test name
Test status
Simulation time 153190000 ps
CPU time 12.94 seconds
Started Mar 10 12:26:22 PM PDT 24
Finished Mar 10 12:26:36 PM PDT 24
Peak memory 259472 kb
Host smart-d30c52f2-25cd-417a-9824-c0d76e755739
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976417045 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.3976417045
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.4182953385
Short name T1247
Test name
Test status
Simulation time 28452500 ps
CPU time 15.3 seconds
Started Mar 10 12:26:02 PM PDT 24
Finished Mar 10 12:26:18 PM PDT 24
Peak memory 263224 kb
Host smart-8bfe6f78-39ca-49b9-bbdb-8b9d0d294c48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182953385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.4
182953385
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2986794391
Short name T1151
Test name
Test status
Simulation time 24953900 ps
CPU time 13.64 seconds
Started Mar 10 12:26:37 PM PDT 24
Finished Mar 10 12:26:50 PM PDT 24
Peak memory 259980 kb
Host smart-8d462d77-b2e3-42fc-9029-2b35958fe148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986794391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
2986794391
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.181248512
Short name T1257
Test name
Test status
Simulation time 28167800 ps
CPU time 13.53 seconds
Started Mar 10 12:26:38 PM PDT 24
Finished Mar 10 12:26:52 PM PDT 24
Peak memory 261812 kb
Host smart-78e5866e-5615-4482-a8b0-fbef04873ed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181248512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.181248512
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.103060219
Short name T1137
Test name
Test status
Simulation time 191391800 ps
CPU time 13.57 seconds
Started Mar 10 12:26:39 PM PDT 24
Finished Mar 10 12:26:53 PM PDT 24
Peak memory 261556 kb
Host smart-a89d6e0a-d727-466a-a51c-b4dde649d31d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103060219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.103060219
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.617855551
Short name T325
Test name
Test status
Simulation time 28260700 ps
CPU time 14.22 seconds
Started Mar 10 12:26:31 PM PDT 24
Finished Mar 10 12:26:46 PM PDT 24
Peak memory 259992 kb
Host smart-bc4ec431-bb8a-4eb4-851a-ece727f3a369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617855551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.617855551
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3715518483
Short name T1256
Test name
Test status
Simulation time 30875100 ps
CPU time 13.35 seconds
Started Mar 10 12:28:08 PM PDT 24
Finished Mar 10 12:28:21 PM PDT 24
Peak memory 260328 kb
Host smart-d3dc6f43-9434-4ff1-b314-d1e0c0744af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715518483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
3715518483
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2163794636
Short name T259
Test name
Test status
Simulation time 23537900 ps
CPU time 13.08 seconds
Started Mar 10 12:28:25 PM PDT 24
Finished Mar 10 12:28:38 PM PDT 24
Peak memory 261588 kb
Host smart-1c2e6363-d65a-497e-ad8c-bf84e21f07dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163794636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
2163794636
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2017262930
Short name T1237
Test name
Test status
Simulation time 17335700 ps
CPU time 13.25 seconds
Started Mar 10 12:26:38 PM PDT 24
Finished Mar 10 12:26:51 PM PDT 24
Peak memory 261752 kb
Host smart-5518e41d-7543-45d5-98b0-b31cc7cdbd51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017262930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
2017262930
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.53407455
Short name T326
Test name
Test status
Simulation time 16207400 ps
CPU time 13.92 seconds
Started Mar 10 12:26:36 PM PDT 24
Finished Mar 10 12:26:50 PM PDT 24
Peak memory 261560 kb
Host smart-0fd931f9-f253-41ed-a852-ee4930de3b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53407455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.53407455
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2460480640
Short name T1178
Test name
Test status
Simulation time 124143000 ps
CPU time 13.47 seconds
Started Mar 10 12:26:30 PM PDT 24
Finished Mar 10 12:26:44 PM PDT 24
Peak memory 259836 kb
Host smart-b52855bc-0a6d-450a-b5c7-b744d750a7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460480640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
2460480640
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2830409715
Short name T260
Test name
Test status
Simulation time 14222900 ps
CPU time 13.34 seconds
Started Mar 10 12:28:08 PM PDT 24
Finished Mar 10 12:28:21 PM PDT 24
Peak memory 260540 kb
Host smart-656693aa-4266-4347-8d58-af2406a9913a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830409715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
2830409715
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2379143167
Short name T1276
Test name
Test status
Simulation time 206533000 ps
CPU time 18.68 seconds
Started Mar 10 12:25:56 PM PDT 24
Finished Mar 10 12:26:15 PM PDT 24
Peak memory 271512 kb
Host smart-c93887d1-625c-493b-9567-8f508fe43797
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379143167 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.2379143167
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2441634910
Short name T1253
Test name
Test status
Simulation time 98681100 ps
CPU time 16.16 seconds
Started Mar 10 12:25:47 PM PDT 24
Finished Mar 10 12:26:03 PM PDT 24
Peak memory 259504 kb
Host smart-4cd6825d-7fa8-428c-9850-3e34eb9fd59b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441634910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.2441634910
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4123095995
Short name T1243
Test name
Test status
Simulation time 78445400 ps
CPU time 13.46 seconds
Started Mar 10 12:26:43 PM PDT 24
Finished Mar 10 12:26:57 PM PDT 24
Peak memory 261868 kb
Host smart-075e77c5-76ca-4cbe-8cc7-0239a9d74321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123095995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.4
123095995
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1116437800
Short name T294
Test name
Test status
Simulation time 874606900 ps
CPU time 36.43 seconds
Started Mar 10 12:26:01 PM PDT 24
Finished Mar 10 12:26:39 PM PDT 24
Peak memory 259552 kb
Host smart-d142b42d-a1ea-4fdd-8f69-cef10d1bf0a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116437800 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1116437800
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.997199516
Short name T1139
Test name
Test status
Simulation time 18178900 ps
CPU time 12.9 seconds
Started Mar 10 12:26:01 PM PDT 24
Finished Mar 10 12:26:15 PM PDT 24
Peak memory 259492 kb
Host smart-d86b3dbb-1acc-45c2-acff-6ec695bdf44b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997199516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.997199516
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2118913503
Short name T1149
Test name
Test status
Simulation time 11746400 ps
CPU time 13.78 seconds
Started Mar 10 12:26:41 PM PDT 24
Finished Mar 10 12:26:55 PM PDT 24
Peak memory 259428 kb
Host smart-c1256c1d-bab4-481e-81d3-85134408fcc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118913503 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.2118913503
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.54906678
Short name T1188
Test name
Test status
Simulation time 52304900 ps
CPU time 14.78 seconds
Started Mar 10 12:26:02 PM PDT 24
Finished Mar 10 12:26:17 PM PDT 24
Peak memory 263324 kb
Host smart-ed5c5d76-d83d-4078-b6a7-f3b1fb9bcb2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54906678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.54906678
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2906379071
Short name T290
Test name
Test status
Simulation time 301746100 ps
CPU time 17.39 seconds
Started Mar 10 12:26:09 PM PDT 24
Finished Mar 10 12:26:27 PM PDT 24
Peak memory 260976 kb
Host smart-97637017-dac4-4e8c-82b2-e967766fcffd
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906379071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.2906379071
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2547600805
Short name T1210
Test name
Test status
Simulation time 57104000 ps
CPU time 13.72 seconds
Started Mar 10 12:26:05 PM PDT 24
Finished Mar 10 12:26:19 PM PDT 24
Peak memory 260528 kb
Host smart-5cb0c3b4-c884-44f5-96fe-9f8ff87ffb89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547600805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2
547600805
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2350286473
Short name T295
Test name
Test status
Simulation time 826853800 ps
CPU time 35.97 seconds
Started Mar 10 12:26:06 PM PDT 24
Finished Mar 10 12:26:42 PM PDT 24
Peak memory 259552 kb
Host smart-6bc25357-7bae-4a7f-b934-295f4bef1e1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350286473 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.2350286473
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.70200904
Short name T1231
Test name
Test status
Simulation time 14785600 ps
CPU time 15.73 seconds
Started Mar 10 12:26:04 PM PDT 24
Finished Mar 10 12:26:20 PM PDT 24
Peak memory 259460 kb
Host smart-4abe877d-b17e-4c51-8eb3-ce1e70f100c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70200904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.70200904
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4222649367
Short name T1240
Test name
Test status
Simulation time 35785300 ps
CPU time 13.05 seconds
Started Mar 10 12:26:07 PM PDT 24
Finished Mar 10 12:26:20 PM PDT 24
Peak memory 259436 kb
Host smart-b2196f44-0f01-459c-a628-832e0a407a2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222649367 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.4222649367
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3691195184
Short name T1198
Test name
Test status
Simulation time 115892000 ps
CPU time 18.58 seconds
Started Mar 10 12:26:01 PM PDT 24
Finished Mar 10 12:26:21 PM PDT 24
Peak memory 263168 kb
Host smart-f6dba896-e5ab-46aa-9d7e-bea65105b57c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691195184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.3
691195184
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1204699108
Short name T1154
Test name
Test status
Simulation time 27749800 ps
CPU time 16.89 seconds
Started Mar 10 12:26:13 PM PDT 24
Finished Mar 10 12:26:30 PM PDT 24
Peak memory 269512 kb
Host smart-19581771-2a25-49fe-9b45-0b432dc3cb3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204699108 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.1204699108
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2281944237
Short name T1135
Test name
Test status
Simulation time 639293000 ps
CPU time 17.35 seconds
Started Mar 10 12:26:08 PM PDT 24
Finished Mar 10 12:26:25 PM PDT 24
Peak memory 259556 kb
Host smart-3a696380-9d7e-492c-a192-16b81cc3a793
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281944237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.2281944237
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3245316118
Short name T1136
Test name
Test status
Simulation time 49467600 ps
CPU time 13.45 seconds
Started Mar 10 12:26:02 PM PDT 24
Finished Mar 10 12:26:16 PM PDT 24
Peak memory 261600 kb
Host smart-acddb7b6-61ef-4be6-8609-245da3cd64e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245316118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.3
245316118
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1039681985
Short name T1260
Test name
Test status
Simulation time 120833500 ps
CPU time 33.98 seconds
Started Mar 10 12:26:02 PM PDT 24
Finished Mar 10 12:26:37 PM PDT 24
Peak memory 259576 kb
Host smart-73b258aa-6fae-4a5c-8a63-ccb1b270f07c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039681985 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1039681985
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2647020200
Short name T1172
Test name
Test status
Simulation time 39384000 ps
CPU time 13.28 seconds
Started Mar 10 12:26:16 PM PDT 24
Finished Mar 10 12:26:30 PM PDT 24
Peak memory 259396 kb
Host smart-46b7e0e1-b2a8-4efa-9e1b-d7b39e22ef7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647020200 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2647020200
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1828639542
Short name T1219
Test name
Test status
Simulation time 33000500 ps
CPU time 15.49 seconds
Started Mar 10 12:26:04 PM PDT 24
Finished Mar 10 12:26:20 PM PDT 24
Peak memory 259392 kb
Host smart-a7de3ad9-0604-42b4-ac90-6f54932f0b3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828639542 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.1828639542
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1273463333
Short name T257
Test name
Test status
Simulation time 83379600 ps
CPU time 17.98 seconds
Started Mar 10 12:26:00 PM PDT 24
Finished Mar 10 12:26:20 PM PDT 24
Peak memory 263212 kb
Host smart-93c614ab-d60d-4b95-9ef4-6c7f1ef7a5bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273463333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.1
273463333
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.183177165
Short name T230
Test name
Test status
Simulation time 149410900 ps
CPU time 20.09 seconds
Started Mar 10 12:26:03 PM PDT 24
Finished Mar 10 12:26:24 PM PDT 24
Peak memory 270616 kb
Host smart-e105ecca-a248-4c3c-b1a5-3995cb347de1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183177165 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.183177165
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2345892407
Short name T1162
Test name
Test status
Simulation time 69420700 ps
CPU time 17.44 seconds
Started Mar 10 12:25:58 PM PDT 24
Finished Mar 10 12:26:16 PM PDT 24
Peak memory 259416 kb
Host smart-023f4793-1fa5-4fdf-8a0b-8797d792574b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345892407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.2345892407
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2598785493
Short name T1133
Test name
Test status
Simulation time 16116300 ps
CPU time 13.6 seconds
Started Mar 10 12:26:05 PM PDT 24
Finished Mar 10 12:26:19 PM PDT 24
Peak memory 261488 kb
Host smart-d7a6e035-abdf-4936-931f-312b53f48b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598785493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.2
598785493
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2766903137
Short name T1166
Test name
Test status
Simulation time 643986700 ps
CPU time 18.98 seconds
Started Mar 10 12:26:23 PM PDT 24
Finished Mar 10 12:26:43 PM PDT 24
Peak memory 259532 kb
Host smart-933ecf76-09ac-45bd-be77-24ed62805167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766903137 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.2766903137
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.530785563
Short name T1168
Test name
Test status
Simulation time 21199700 ps
CPU time 13.47 seconds
Started Mar 10 12:26:00 PM PDT 24
Finished Mar 10 12:26:13 PM PDT 24
Peak memory 259392 kb
Host smart-1e38d4f1-0e7e-41e9-b862-0f98927ce34a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530785563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.530785563
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2601614991
Short name T1134
Test name
Test status
Simulation time 12208400 ps
CPU time 13.22 seconds
Started Mar 10 12:26:16 PM PDT 24
Finished Mar 10 12:26:30 PM PDT 24
Peak memory 259380 kb
Host smart-76511ae8-a0a5-4f09-99f8-a6603abe50a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601614991 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.2601614991
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3470174134
Short name T1241
Test name
Test status
Simulation time 193084200 ps
CPU time 15.94 seconds
Started Mar 10 12:26:07 PM PDT 24
Finished Mar 10 12:26:23 PM PDT 24
Peak memory 263280 kb
Host smart-bd2bd431-54c3-4a9d-a324-81c170ef54ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470174134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3
470174134
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1700363485
Short name T336
Test name
Test status
Simulation time 10808240200 ps
CPU time 900.29 seconds
Started Mar 10 12:26:03 PM PDT 24
Finished Mar 10 12:41:04 PM PDT 24
Peak memory 263240 kb
Host smart-679c9262-b556-4eb8-8bf6-932fada9b90e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700363485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.1700363485
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2255955994
Short name T1266
Test name
Test status
Simulation time 58045800 ps
CPU time 17.16 seconds
Started Mar 10 12:26:38 PM PDT 24
Finished Mar 10 12:26:55 PM PDT 24
Peak memory 263220 kb
Host smart-45f8d1ad-26ba-47e7-be0f-b3c73da2390e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255955994 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.2255955994
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.888792186
Short name T1218
Test name
Test status
Simulation time 26511600 ps
CPU time 14.52 seconds
Started Mar 10 12:27:39 PM PDT 24
Finished Mar 10 12:27:54 PM PDT 24
Peak memory 259492 kb
Host smart-3ce127cb-5e7d-4767-a9f7-7afd834dd3bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888792186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_csr_rw.888792186
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3776762059
Short name T1227
Test name
Test status
Simulation time 127601200 ps
CPU time 13.47 seconds
Started Mar 10 12:26:04 PM PDT 24
Finished Mar 10 12:26:18 PM PDT 24
Peak memory 261788 kb
Host smart-7013a63d-0595-457c-b5d8-6be7d27da6e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776762059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.3
776762059
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2205947091
Short name T1170
Test name
Test status
Simulation time 169256500 ps
CPU time 18.29 seconds
Started Mar 10 12:26:45 PM PDT 24
Finished Mar 10 12:27:04 PM PDT 24
Peak memory 259480 kb
Host smart-50aff2e9-0602-443e-8a16-ef1bdb5872aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205947091 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.2205947091
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3127096674
Short name T1175
Test name
Test status
Simulation time 20044400 ps
CPU time 15.6 seconds
Started Mar 10 12:25:58 PM PDT 24
Finished Mar 10 12:26:14 PM PDT 24
Peak memory 259444 kb
Host smart-2f31fdf5-b9e8-4f0f-a8ed-42e009fb2161
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127096674 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.3127096674
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3481555788
Short name T1212
Test name
Test status
Simulation time 13194900 ps
CPU time 15.66 seconds
Started Mar 10 12:26:19 PM PDT 24
Finished Mar 10 12:26:35 PM PDT 24
Peak memory 259380 kb
Host smart-3025fb24-4b1e-427c-a1a0-c07d9cb5c16c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481555788 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.3481555788
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2258914093
Short name T231
Test name
Test status
Simulation time 98676700 ps
CPU time 19.34 seconds
Started Mar 10 12:25:59 PM PDT 24
Finished Mar 10 12:26:19 PM PDT 24
Peak memory 263184 kb
Host smart-5adf0ac1-45bb-44e1-add1-e3aeca49ec06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258914093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.2
258914093
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2391962938
Short name T1258
Test name
Test status
Simulation time 1641667500 ps
CPU time 456.46 seconds
Started Mar 10 12:28:23 PM PDT 24
Finished Mar 10 12:36:00 PM PDT 24
Peak memory 263196 kb
Host smart-a7e0aac7-45e4-4722-b02b-a0c88397f942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391962938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.2391962938
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.411459376
Short name T449
Test name
Test status
Simulation time 310258600 ps
CPU time 13.34 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:35:35 PM PDT 24
Peak memory 264736 kb
Host smart-31803305-48d7-472f-9dee-ae240149f4e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411459376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.411459376
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.3240981958
Short name T408
Test name
Test status
Simulation time 54482100 ps
CPU time 15.59 seconds
Started Mar 10 12:35:24 PM PDT 24
Finished Mar 10 12:35:40 PM PDT 24
Peak memory 273788 kb
Host smart-e05506c0-c6b8-41b0-b3ab-dd0dee47ddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240981958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.3240981958
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.2518630394
Short name T195
Test name
Test status
Simulation time 317093600 ps
CPU time 105.13 seconds
Started Mar 10 12:35:16 PM PDT 24
Finished Mar 10 12:37:02 PM PDT 24
Peak memory 270932 kb
Host smart-f1e4d673-cec0-42ea-984b-a47d75e8a9c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518630394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.2518630394
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.4188031286
Short name T947
Test name
Test status
Simulation time 5762627100 ps
CPU time 544.31 seconds
Started Mar 10 12:35:06 PM PDT 24
Finished Mar 10 12:44:12 PM PDT 24
Peak memory 260548 kb
Host smart-be3fa4ca-41ab-409f-9dcf-8c4558d8770f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188031286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.4188031286
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.3436429059
Short name T54
Test name
Test status
Simulation time 2655493300 ps
CPU time 23.49 seconds
Started Mar 10 12:35:20 PM PDT 24
Finished Mar 10 12:35:44 PM PDT 24
Peak memory 264616 kb
Host smart-ee6617a5-7f2f-4df2-b562-428c0520c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436429059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.3436429059
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.329813358
Short name T168
Test name
Test status
Simulation time 1056316900 ps
CPU time 34.21 seconds
Started Mar 10 12:35:10 PM PDT 24
Finished Mar 10 12:35:46 PM PDT 24
Peak memory 272864 kb
Host smart-912185b9-687b-44ce-9f97-aa47242b2c07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329813358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_fs_sup.329813358
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.3329659404
Short name T763
Test name
Test status
Simulation time 156568781700 ps
CPU time 2803.63 seconds
Started Mar 10 12:35:04 PM PDT 24
Finished Mar 10 01:21:49 PM PDT 24
Peak memory 264484 kb
Host smart-2f4df6f0-f97f-47d2-b23b-d301c5428991
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329659404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.3329659404
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.3957144396
Short name T1079
Test name
Test status
Simulation time 119220400 ps
CPU time 13.58 seconds
Started Mar 10 12:35:18 PM PDT 24
Finished Mar 10 12:35:32 PM PDT 24
Peak memory 264672 kb
Host smart-997f76e2-089b-4d95-9188-d53a17ceee16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957144396 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.3957144396
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.597179139
Short name T1031
Test name
Test status
Simulation time 140180203000 ps
CPU time 877.36 seconds
Started Mar 10 12:35:08 PM PDT 24
Finished Mar 10 12:49:46 PM PDT 24
Peak memory 261916 kb
Host smart-b9274768-81bd-4724-b080-2b10d80bf9e8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597179139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_hw_rma_reset.597179139
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.520389665
Short name T47
Test name
Test status
Simulation time 1987075800 ps
CPU time 141.18 seconds
Started Mar 10 12:35:17 PM PDT 24
Finished Mar 10 12:37:39 PM PDT 24
Peak memory 261792 kb
Host smart-c28937ff-310d-48fd-8adc-431cd06f3826
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520389665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw
_sec_otp.520389665
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.2063067026
Short name T250
Test name
Test status
Simulation time 7029301200 ps
CPU time 530.64 seconds
Started Mar 10 12:35:16 PM PDT 24
Finished Mar 10 12:44:08 PM PDT 24
Peak memory 328812 kb
Host smart-720619b4-3534-448c-831a-94076c1b0e32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063067026 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.2063067026
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.2571103240
Short name T911
Test name
Test status
Simulation time 1080168100 ps
CPU time 156.55 seconds
Started Mar 10 12:35:10 PM PDT 24
Finished Mar 10 12:37:48 PM PDT 24
Peak memory 293548 kb
Host smart-6aa5be35-7bc6-4fd0-8ae9-924f9abff6f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571103240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.2571103240
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.3289148104
Short name T991
Test name
Test status
Simulation time 15861379800 ps
CPU time 212.46 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:38:55 PM PDT 24
Peak memory 290364 kb
Host smart-5d2a49a1-0577-4636-8e7c-c22bf7672a87
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289148104 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.3289148104
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.3458358977
Short name T1058
Test name
Test status
Simulation time 33105006500 ps
CPU time 119.03 seconds
Started Mar 10 12:35:19 PM PDT 24
Finished Mar 10 12:37:18 PM PDT 24
Peak memory 264640 kb
Host smart-26cc6e59-370f-48ce-afd1-adbde3812f6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458358977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.3458358977
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.3014012591
Short name T1067
Test name
Test status
Simulation time 44075433400 ps
CPU time 328.71 seconds
Started Mar 10 12:35:11 PM PDT 24
Finished Mar 10 12:40:40 PM PDT 24
Peak memory 264696 kb
Host smart-ed561f33-a7ec-463e-a59a-eb6542344c35
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301
4012591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.3014012591
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1387990903
Short name T1004
Test name
Test status
Simulation time 127485700 ps
CPU time 13.35 seconds
Started Mar 10 12:35:13 PM PDT 24
Finished Mar 10 12:35:27 PM PDT 24
Peak memory 264760 kb
Host smart-ec888c0b-ebbf-455b-98c5-d676ff5d91c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387990903 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1387990903
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.3580090613
Short name T104
Test name
Test status
Simulation time 7875575000 ps
CPU time 603.15 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:45:24 PM PDT 24
Peak memory 273100 kb
Host smart-348c33ca-e9e9-4635-a985-83a83622f915
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580090613 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.3580090613
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.1457408339
Short name T586
Test name
Test status
Simulation time 59390200 ps
CPU time 130.6 seconds
Started Mar 10 12:35:26 PM PDT 24
Finished Mar 10 12:37:36 PM PDT 24
Peak memory 263632 kb
Host smart-c3d8af9b-b325-430b-a702-01a585c12a3c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457408339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.1457408339
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.1245311426
Short name T791
Test name
Test status
Simulation time 47722700 ps
CPU time 153.07 seconds
Started Mar 10 12:35:14 PM PDT 24
Finished Mar 10 12:37:47 PM PDT 24
Peak memory 264536 kb
Host smart-9a120774-b349-4d38-8e03-11bd12ee7113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245311426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.1245311426
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.3229968765
Short name T307
Test name
Test status
Simulation time 4070908100 ps
CPU time 324.76 seconds
Started Mar 10 12:35:13 PM PDT 24
Finished Mar 10 12:40:38 PM PDT 24
Peak memory 264728 kb
Host smart-56f98327-74d5-4623-a704-26df7c0d5811
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229968765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.3229968765
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.3768098388
Short name T910
Test name
Test status
Simulation time 784416100 ps
CPU time 885.3 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:50:08 PM PDT 24
Peak memory 284840 kb
Host smart-7887ad3a-ef6e-4aa3-97be-f255f89873fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768098388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3768098388
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1438365214
Short name T958
Test name
Test status
Simulation time 732030800 ps
CPU time 138.8 seconds
Started Mar 10 12:35:16 PM PDT 24
Finished Mar 10 12:37:36 PM PDT 24
Peak memory 264752 kb
Host smart-96e0292b-8cca-4c83-81ed-e517f036e99a
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1438365214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1438365214
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.3913284959
Short name T279
Test name
Test status
Simulation time 207878700 ps
CPU time 31.43 seconds
Started Mar 10 12:35:18 PM PDT 24
Finished Mar 10 12:35:49 PM PDT 24
Peak memory 273056 kb
Host smart-8c3b29e4-bd95-46f4-80dd-f598a3422c75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913284959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.3913284959
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.2709670932
Short name T614
Test name
Test status
Simulation time 129866400 ps
CPU time 42.21 seconds
Started Mar 10 12:35:15 PM PDT 24
Finished Mar 10 12:35:58 PM PDT 24
Peak memory 273132 kb
Host smart-89a8362f-695f-461f-87b2-ec1cfb9b080b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709670932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.2709670932
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.3888165001
Short name T111
Test name
Test status
Simulation time 124485400 ps
CPU time 38.18 seconds
Started Mar 10 12:35:25 PM PDT 24
Finished Mar 10 12:36:03 PM PDT 24
Peak memory 273440 kb
Host smart-96893721-d765-4302-a444-4a989354dd86
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888165001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.3888165001
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.1596038266
Short name T650
Test name
Test status
Simulation time 14552800 ps
CPU time 13.24 seconds
Started Mar 10 12:35:06 PM PDT 24
Finished Mar 10 12:35:21 PM PDT 24
Peak memory 265024 kb
Host smart-8bba22f9-9103-4b41-9224-ce80925490b1
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1596038266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.1596038266
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.3960626286
Short name T762
Test name
Test status
Simulation time 59090900 ps
CPU time 22.32 seconds
Started Mar 10 12:35:09 PM PDT 24
Finished Mar 10 12:35:31 PM PDT 24
Peak memory 264788 kb
Host smart-c2e3836b-72e1-43cf-8cc0-8dc86f58df3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960626286 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.3960626286
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.2454209753
Short name T1045
Test name
Test status
Simulation time 23321000 ps
CPU time 22.23 seconds
Started Mar 10 12:35:14 PM PDT 24
Finished Mar 10 12:35:37 PM PDT 24
Peak memory 264816 kb
Host smart-f6acc807-a638-498e-9d5d-92580b8b1a6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454209753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.2454209753
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.1343751344
Short name T154
Test name
Test status
Simulation time 166565820500 ps
CPU time 916.68 seconds
Started Mar 10 12:35:11 PM PDT 24
Finished Mar 10 12:50:28 PM PDT 24
Peak memory 258484 kb
Host smart-7122a45a-8639-4c68-98c5-8c4d1ec14100
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343751344 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.1343751344
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.1775496513
Short name T211
Test name
Test status
Simulation time 782826700 ps
CPU time 83.14 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:36:51 PM PDT 24
Peak memory 280252 kb
Host smart-61fafb2e-adb0-4f4e-b9c7-ac0b661af56d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775496513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_ro.1775496513
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.615094219
Short name T206
Test name
Test status
Simulation time 482381500 ps
CPU time 111.2 seconds
Started Mar 10 12:35:12 PM PDT 24
Finished Mar 10 12:37:03 PM PDT 24
Peak memory 281136 kb
Host smart-b8ebf0be-03a3-4a5a-87d7-9ef9d0988c21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
615094219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.615094219
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.4177979582
Short name T237
Test name
Test status
Simulation time 645550900 ps
CPU time 120.72 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:37:22 PM PDT 24
Peak memory 281248 kb
Host smart-d6949105-5f3d-4ced-b52e-3b2679638f40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177979582 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.4177979582
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.3032111722
Short name T1018
Test name
Test status
Simulation time 9077423400 ps
CPU time 402.55 seconds
Started Mar 10 12:35:26 PM PDT 24
Finished Mar 10 12:42:09 PM PDT 24
Peak memory 313256 kb
Host smart-86c4678e-6794-4e18-b575-870b178f5e0e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032111722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_rw.3032111722
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.262136885
Short name T26
Test name
Test status
Simulation time 144008000 ps
CPU time 28.54 seconds
Started Mar 10 12:35:19 PM PDT 24
Finished Mar 10 12:35:49 PM PDT 24
Peak memory 273020 kb
Host smart-7114fe16-1bbd-4a68-b4ef-03b8e7b1e665
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262136885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_rw_evict.262136885
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.2557854602
Short name T831
Test name
Test status
Simulation time 69847900 ps
CPU time 30.16 seconds
Started Mar 10 12:35:12 PM PDT 24
Finished Mar 10 12:35:43 PM PDT 24
Peak memory 271908 kb
Host smart-74a6c5c7-61f2-457f-a7ae-b56681c40778
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557854602 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.2557854602
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.54171214
Short name T493
Test name
Test status
Simulation time 3091804400 ps
CPU time 456.71 seconds
Started Mar 10 12:35:25 PM PDT 24
Finished Mar 10 12:43:02 PM PDT 24
Peak memory 313956 kb
Host smart-387caf30-4ace-4030-ba1a-ad242b31ca79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54171214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash
_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_ser
r.54171214
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.2964225386
Short name T15
Test name
Test status
Simulation time 5774048300 ps
CPU time 4777.18 seconds
Started Mar 10 12:35:08 PM PDT 24
Finished Mar 10 01:54:46 PM PDT 24
Peak memory 286324 kb
Host smart-ecab2b0e-812e-48b6-9f82-4f2ca9ec27c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964225386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.2964225386
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.1479652535
Short name T309
Test name
Test status
Simulation time 5311407300 ps
CPU time 59.84 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:36:22 PM PDT 24
Peak memory 264460 kb
Host smart-83a8c75b-240b-4111-8805-af46acfd0ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479652535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.1479652535
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.3130350088
Short name T698
Test name
Test status
Simulation time 514417500 ps
CPU time 54.56 seconds
Started Mar 10 12:35:14 PM PDT 24
Finished Mar 10 12:36:09 PM PDT 24
Peak memory 264828 kb
Host smart-202b9883-d571-475e-823b-c510a10a2562
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130350088 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.3130350088
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.3624675875
Short name T479
Test name
Test status
Simulation time 474125200 ps
CPU time 58.95 seconds
Started Mar 10 12:35:19 PM PDT 24
Finished Mar 10 12:36:18 PM PDT 24
Peak memory 272952 kb
Host smart-d7899540-d6da-400a-be70-58c5008032e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624675875 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.3624675875
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.3774828974
Short name T1044
Test name
Test status
Simulation time 81923200 ps
CPU time 169.49 seconds
Started Mar 10 12:35:25 PM PDT 24
Finished Mar 10 12:38:15 PM PDT 24
Peak memory 275768 kb
Host smart-36ea9f0f-ba70-4d2e-9f89-b43e0c6d027b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774828974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.3774828974
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.2431773873
Short name T1065
Test name
Test status
Simulation time 17085900 ps
CPU time 23.54 seconds
Started Mar 10 12:35:05 PM PDT 24
Finished Mar 10 12:35:29 PM PDT 24
Peak memory 258376 kb
Host smart-c96cc057-818e-4028-a224-6d84f3824dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431773873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.2431773873
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.2592275778
Short name T644
Test name
Test status
Simulation time 82740600 ps
CPU time 402.64 seconds
Started Mar 10 12:35:12 PM PDT 24
Finished Mar 10 12:41:55 PM PDT 24
Peak memory 275976 kb
Host smart-df41f64f-6d1e-4e94-a9b4-a538a5c48333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592275778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.2592275778
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.890459847
Short name T802
Test name
Test status
Simulation time 51439400 ps
CPU time 26.43 seconds
Started Mar 10 12:35:06 PM PDT 24
Finished Mar 10 12:35:34 PM PDT 24
Peak memory 258724 kb
Host smart-bb847b6d-9e9d-44ca-b61a-952258afea91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890459847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.890459847
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.3109569826
Short name T582
Test name
Test status
Simulation time 6070721700 ps
CPU time 122.31 seconds
Started Mar 10 12:35:06 PM PDT 24
Finished Mar 10 12:37:10 PM PDT 24
Peak memory 264688 kb
Host smart-f16edc2c-4b10-421d-891c-04c5b3ca34bd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109569826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.flash_ctrl_wo.3109569826
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.1894171440
Short name T8
Test name
Test status
Simulation time 221149100 ps
CPU time 14.73 seconds
Started Mar 10 12:35:11 PM PDT 24
Finished Mar 10 12:35:26 PM PDT 24
Peak memory 263988 kb
Host smart-42f1763f-9c2d-45e8-be26-1114baabcf39
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894171440 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.1894171440
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.3855084358
Short name T785
Test name
Test status
Simulation time 212508300 ps
CPU time 16.35 seconds
Started Mar 10 12:35:11 PM PDT 24
Finished Mar 10 12:35:28 PM PDT 24
Peak memory 264032 kb
Host smart-6256fdef-7ff7-43b6-bb2c-e04fb2dca103
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3855084358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.3855084358
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.590161178
Short name T961
Test name
Test status
Simulation time 374337300 ps
CPU time 14.12 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:35:42 PM PDT 24
Peak memory 263756 kb
Host smart-7699698e-2d26-44ae-8da1-f5d5cce1071b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590161178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.590161178
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.623482295
Short name T20
Test name
Test status
Simulation time 72191200 ps
CPU time 13.52 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:35:35 PM PDT 24
Peak memory 264732 kb
Host smart-6494b3af-2d1b-436c-8c50-5c03ed4c22c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623482295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
flash_ctrl_config_regwen.623482295
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.4134621247
Short name T929
Test name
Test status
Simulation time 46355800 ps
CPU time 15.88 seconds
Started Mar 10 12:35:24 PM PDT 24
Finished Mar 10 12:35:40 PM PDT 24
Peak memory 273740 kb
Host smart-f9d80daf-cb2e-4cdc-b7ae-072d57e411b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134621247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.4134621247
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.3936042288
Short name T684
Test name
Test status
Simulation time 693246400 ps
CPU time 104.05 seconds
Started Mar 10 12:35:24 PM PDT 24
Finished Mar 10 12:37:08 PM PDT 24
Peak memory 273020 kb
Host smart-e60f430d-74d3-4bb0-9db8-4ee1bf380bc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936042288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.3936042288
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.528997231
Short name T746
Test name
Test status
Simulation time 60995800 ps
CPU time 21.61 seconds
Started Mar 10 12:35:17 PM PDT 24
Finished Mar 10 12:35:40 PM PDT 24
Peak memory 273116 kb
Host smart-9825f6b0-ee5c-46ba-a3da-fd789c76ec0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528997231 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.528997231
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.3509589872
Short name T122
Test name
Test status
Simulation time 1565714300 ps
CPU time 356.02 seconds
Started Mar 10 12:35:24 PM PDT 24
Finished Mar 10 12:41:20 PM PDT 24
Peak memory 260492 kb
Host smart-f5828c0f-3a9a-4c6c-b26c-e3acf9e28a45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509589872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3509589872
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.1823439201
Short name T85
Test name
Test status
Simulation time 38884139600 ps
CPU time 2126.38 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 01:10:54 PM PDT 24
Peak memory 263340 kb
Host smart-fb2a02ba-31ef-4f6a-b76a-e39246a1fff9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823439201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.1823439201
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.2043626924
Short name T655
Test name
Test status
Simulation time 970409800 ps
CPU time 2898.74 seconds
Started Mar 10 12:35:23 PM PDT 24
Finished Mar 10 01:23:43 PM PDT 24
Peak memory 265032 kb
Host smart-65a24011-aadc-4c73-84aa-08c1ef824e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043626924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.2043626924
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.3241649392
Short name T245
Test name
Test status
Simulation time 318732300 ps
CPU time 774.41 seconds
Started Mar 10 12:35:23 PM PDT 24
Finished Mar 10 12:48:18 PM PDT 24
Peak memory 264640 kb
Host smart-c210cff5-c0ae-42c3-8ba9-5abc73146834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241649392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.3241649392
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.1204783200
Short name T982
Test name
Test status
Simulation time 1395357400 ps
CPU time 23.64 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:35:51 PM PDT 24
Peak memory 264656 kb
Host smart-478b8065-9083-4750-89b0-4ce16bda0be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204783200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.1204783200
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.1550982247
Short name T699
Test name
Test status
Simulation time 278152500 ps
CPU time 33.62 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:35:56 PM PDT 24
Peak memory 274924 kb
Host smart-3bae91b5-003e-452a-9c1f-8b99613393fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550982247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.1550982247
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.1269758969
Short name T1117
Test name
Test status
Simulation time 49891766700 ps
CPU time 4266.1 seconds
Started Mar 10 12:35:23 PM PDT 24
Finished Mar 10 01:46:30 PM PDT 24
Peak memory 264464 kb
Host smart-030aa608-dc44-4205-9e15-74e0f237dcc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269758969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.1269758969
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1955840902
Short name T161
Test name
Test status
Simulation time 10012453100 ps
CPU time 125.88 seconds
Started Mar 10 12:38:51 PM PDT 24
Finished Mar 10 12:40:57 PM PDT 24
Peak memory 329916 kb
Host smart-9473c235-9dc6-4ee8-8519-27f26594e81a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955840902 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.1955840902
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.2081958637
Short name T662
Test name
Test status
Simulation time 549483685900 ps
CPU time 1767.1 seconds
Started Mar 10 12:35:20 PM PDT 24
Finished Mar 10 01:04:48 PM PDT 24
Peak memory 258672 kb
Host smart-aac8a9ab-adab-4066-8500-c4d3fc754479
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081958637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.2081958637
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2992008701
Short name T469
Test name
Test status
Simulation time 80136614900 ps
CPU time 718.75 seconds
Started Mar 10 12:35:25 PM PDT 24
Finished Mar 10 12:47:24 PM PDT 24
Peak memory 262756 kb
Host smart-9f3ffc40-9b94-4801-9cef-55d6c13efd57
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992008701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.2992008701
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.353378415
Short name T457
Test name
Test status
Simulation time 2259150200 ps
CPU time 153.25 seconds
Started Mar 10 12:35:17 PM PDT 24
Finished Mar 10 12:37:51 PM PDT 24
Peak memory 258388 kb
Host smart-64d8d089-d4e6-4c21-ad0e-e72af1fca497
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353378415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw
_sec_otp.353378415
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.4238353132
Short name T247
Test name
Test status
Simulation time 2044594900 ps
CPU time 324.76 seconds
Started Mar 10 12:38:58 PM PDT 24
Finished Mar 10 12:44:23 PM PDT 24
Peak memory 313840 kb
Host smart-c1a70045-da05-47bf-abc2-bb63f491ef9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238353132 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.4238353132
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.2235416677
Short name T1000
Test name
Test status
Simulation time 4675735800 ps
CPU time 157.87 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:38:08 PM PDT 24
Peak memory 292396 kb
Host smart-dea45fea-c0de-4a6f-a18b-bac603d2f936
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235416677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.2235416677
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.1949925201
Short name T784
Test name
Test status
Simulation time 17078586300 ps
CPU time 219.47 seconds
Started Mar 10 12:35:15 PM PDT 24
Finished Mar 10 12:38:55 PM PDT 24
Peak memory 289324 kb
Host smart-ec59ebe7-e3e0-49ee-9853-013a9ea80ca4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949925201 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.1949925201
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.2909456308
Short name T718
Test name
Test status
Simulation time 16296453600 ps
CPU time 103.68 seconds
Started Mar 10 12:35:19 PM PDT 24
Finished Mar 10 12:37:03 PM PDT 24
Peak memory 264664 kb
Host smart-e6ce9f55-8dbe-48c6-858e-d0eadf3012a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909456308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.2909456308
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.3919445586
Short name T985
Test name
Test status
Simulation time 4061537700 ps
CPU time 87.53 seconds
Started Mar 10 12:35:25 PM PDT 24
Finished Mar 10 12:36:53 PM PDT 24
Peak memory 258844 kb
Host smart-fedf3b3e-742b-446f-89df-6f1c183405ef
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919445586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.3919445586
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.1719239026
Short name T861
Test name
Test status
Simulation time 19306521100 ps
CPU time 140.31 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:37:43 PM PDT 24
Peak memory 264768 kb
Host smart-e8ebc6de-83ec-4df5-af5b-694a40238116
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719239026 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.1719239026
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.754684572
Short name T611
Test name
Test status
Simulation time 40918700 ps
CPU time 133.34 seconds
Started Mar 10 12:35:15 PM PDT 24
Finished Mar 10 12:37:29 PM PDT 24
Peak memory 259196 kb
Host smart-60b64f1d-744e-45a1-9dc4-28363b831d02
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754684572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp
_reset.754684572
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.3894786029
Short name T42
Test name
Test status
Simulation time 2165325600 ps
CPU time 136.23 seconds
Started Mar 10 12:38:52 PM PDT 24
Finished Mar 10 12:41:08 PM PDT 24
Peak memory 289356 kb
Host smart-0a3d41d0-9539-4d0b-9396-6a5b4fff8424
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894786029 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.3894786029
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.305866060
Short name T77
Test name
Test status
Simulation time 25712100 ps
CPU time 14.03 seconds
Started Mar 10 12:35:19 PM PDT 24
Finished Mar 10 12:35:33 PM PDT 24
Peak memory 277616 kb
Host smart-50aa8cd3-2dcc-4b04-ad18-48352fba7632
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=305866060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.305866060
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.1404682723
Short name T989
Test name
Test status
Simulation time 1457718600 ps
CPU time 553.76 seconds
Started Mar 10 12:35:16 PM PDT 24
Finished Mar 10 12:44:31 PM PDT 24
Peak memory 260792 kb
Host smart-d843e195-1251-4f51-bb6f-f9b120f2ff89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404682723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.1404682723
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3560147125
Short name T129
Test name
Test status
Simulation time 826613600 ps
CPU time 40.25 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:36:04 PM PDT 24
Peak memory 264828 kb
Host smart-d718ae36-aaf9-4946-ae0d-83d1f7963a7b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560147125 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3560147125
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.1265117056
Short name T629
Test name
Test status
Simulation time 67385500 ps
CPU time 13.45 seconds
Started Mar 10 12:35:25 PM PDT 24
Finished Mar 10 12:35:38 PM PDT 24
Peak memory 264576 kb
Host smart-44b40689-53a5-44ca-a2ad-45f6790c020a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265117056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.1265117056
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.2686009889
Short name T107
Test name
Test status
Simulation time 6361191400 ps
CPU time 1030.06 seconds
Started Mar 10 12:35:24 PM PDT 24
Finished Mar 10 12:52:34 PM PDT 24
Peak memory 286260 kb
Host smart-75fa32c5-8410-4273-920a-c36347e054b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686009889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2686009889
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.4077550703
Short name T427
Test name
Test status
Simulation time 178985200 ps
CPU time 99.8 seconds
Started Mar 10 12:35:18 PM PDT 24
Finished Mar 10 12:36:58 PM PDT 24
Peak memory 264684 kb
Host smart-ad43a8ab-f640-480d-85bc-b560be15e81f
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4077550703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.4077550703
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.2857056038
Short name T1063
Test name
Test status
Simulation time 63215100 ps
CPU time 31.67 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:36:01 PM PDT 24
Peak memory 273136 kb
Host smart-69533cd4-57f6-4340-baf7-d53c0db54e4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857056038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.2857056038
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.787123690
Short name T522
Test name
Test status
Simulation time 118161800 ps
CPU time 37.02 seconds
Started Mar 10 12:35:34 PM PDT 24
Finished Mar 10 12:36:11 PM PDT 24
Peak memory 273052 kb
Host smart-ee24e842-b5d2-46e1-8837-07656942321b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787123690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_re_evict.787123690
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.892451978
Short name T1050
Test name
Test status
Simulation time 32777100 ps
CPU time 22.3 seconds
Started Mar 10 12:35:23 PM PDT 24
Finished Mar 10 12:35:46 PM PDT 24
Peak memory 264944 kb
Host smart-65c1afef-3364-4f97-adc5-0acbae9513de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892451978 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.892451978
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.801346857
Short name T437
Test name
Test status
Simulation time 97409900 ps
CPU time 20.8 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:35:51 PM PDT 24
Peak memory 264756 kb
Host smart-be4837df-9168-4577-a523-bad539e5bf79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801346857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_read_word_sweep_serr.801346857
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.213531357
Short name T143
Test name
Test status
Simulation time 42012922100 ps
CPU time 804.52 seconds
Started Mar 10 12:35:23 PM PDT 24
Finished Mar 10 12:48:48 PM PDT 24
Peak memory 258460 kb
Host smart-d3b8163e-30bb-413f-9afd-c2f5e0c46f69
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213531357 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.213531357
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.746576906
Short name T39
Test name
Test status
Simulation time 753676700 ps
CPU time 84.84 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:36:47 PM PDT 24
Peak memory 281220 kb
Host smart-8d0641de-3ea2-4312-b955-ca370b176edb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746576906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_ro.746576906
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.1823276704
Short name T203
Test name
Test status
Simulation time 1078327100 ps
CPU time 96.69 seconds
Started Mar 10 12:38:50 PM PDT 24
Finished Mar 10 12:40:27 PM PDT 24
Peak memory 281100 kb
Host smart-7cc54aaa-14f4-40f0-878c-9ac18f3b7932
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1823276704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1823276704
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.4195496224
Short name T902
Test name
Test status
Simulation time 5679838100 ps
CPU time 134.02 seconds
Started Mar 10 12:35:23 PM PDT 24
Finished Mar 10 12:37:38 PM PDT 24
Peak memory 293460 kb
Host smart-2208e3c6-520c-4407-97fa-ede6ff7fd945
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195496224 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.4195496224
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.700195547
Short name T976
Test name
Test status
Simulation time 12332734900 ps
CPU time 476.52 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:43:25 PM PDT 24
Peak memory 313316 kb
Host smart-fab930eb-0ff1-4c16-8811-e3be8f9494e4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700195547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctr
l_rw.700195547
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.3375275998
Short name T599
Test name
Test status
Simulation time 37899700 ps
CPU time 31.62 seconds
Started Mar 10 12:35:14 PM PDT 24
Finished Mar 10 12:35:46 PM PDT 24
Peak memory 274044 kb
Host smart-1e04937d-396e-4f9b-8bb8-8eaf9abaaef2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375275998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.3375275998
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.126327917
Short name T580
Test name
Test status
Simulation time 32853800 ps
CPU time 30.78 seconds
Started Mar 10 12:35:26 PM PDT 24
Finished Mar 10 12:35:57 PM PDT 24
Peak memory 273012 kb
Host smart-1ebe81a0-ddb9-49f2-8c06-cf156cf96c64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126327917 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.126327917
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.3637745741
Short name T213
Test name
Test status
Simulation time 2984680100 ps
CPU time 474.9 seconds
Started Mar 10 12:35:14 PM PDT 24
Finished Mar 10 12:43:09 PM PDT 24
Peak memory 319308 kb
Host smart-b274c25a-198e-49fa-9437-63bab4c7e8b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637745741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.3637745741
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.1204494939
Short name T368
Test name
Test status
Simulation time 996095500 ps
CPU time 53.92 seconds
Started Mar 10 12:35:26 PM PDT 24
Finished Mar 10 12:36:20 PM PDT 24
Peak memory 263608 kb
Host smart-8b010897-a0ba-483d-8921-c58942c481c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204494939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1204494939
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.403806890
Short name T1097
Test name
Test status
Simulation time 2268170800 ps
CPU time 62.93 seconds
Started Mar 10 12:35:33 PM PDT 24
Finished Mar 10 12:36:36 PM PDT 24
Peak memory 264788 kb
Host smart-c2a2db78-e730-43fa-8c0f-9bf4839bd739
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403806890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_serr_address.403806890
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.1103589674
Short name T421
Test name
Test status
Simulation time 1709872000 ps
CPU time 49.24 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:36:11 PM PDT 24
Peak memory 264760 kb
Host smart-4b945ee7-0889-4e54-8c65-73914adf4e52
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103589674 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.1103589674
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.2172007398
Short name T1016
Test name
Test status
Simulation time 28308400 ps
CPU time 168.97 seconds
Started Mar 10 12:35:07 PM PDT 24
Finished Mar 10 12:37:57 PM PDT 24
Peak memory 279204 kb
Host smart-569f42a2-49f6-4815-a6fe-bfac10760a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172007398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.2172007398
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.1351662396
Short name T301
Test name
Test status
Simulation time 23541800 ps
CPU time 26 seconds
Started Mar 10 12:35:20 PM PDT 24
Finished Mar 10 12:35:46 PM PDT 24
Peak memory 258448 kb
Host smart-6418c4ad-b57e-451c-b9f9-506e06ff9053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351662396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.1351662396
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1953528594
Short name T973
Test name
Test status
Simulation time 167335300 ps
CPU time 734.3 seconds
Started Mar 10 12:38:41 PM PDT 24
Finished Mar 10 12:50:56 PM PDT 24
Peak memory 279400 kb
Host smart-137de958-179f-4842-a442-a4e16595629f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953528594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1953528594
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.3879399776
Short name T739
Test name
Test status
Simulation time 20339200 ps
CPU time 27.76 seconds
Started Mar 10 12:35:26 PM PDT 24
Finished Mar 10 12:35:54 PM PDT 24
Peak memory 258748 kb
Host smart-1f04d349-5d38-4781-a22c-77148e4bef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879399776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.3879399776
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.750712081
Short name T880
Test name
Test status
Simulation time 11913727000 ps
CPU time 159.59 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:38:01 PM PDT 24
Peak memory 264620 kb
Host smart-f3ef0acf-b774-45dd-a5e5-8d6b20c84a6b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750712081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_wo.750712081
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.3776562071
Short name T783
Test name
Test status
Simulation time 204161600 ps
CPU time 14.27 seconds
Started Mar 10 12:36:44 PM PDT 24
Finished Mar 10 12:36:58 PM PDT 24
Peak memory 263488 kb
Host smart-f673bb14-27bd-48bb-bf1c-d547723cb9de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776562071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
3776562071
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.2669119098
Short name T455
Test name
Test status
Simulation time 33591000 ps
CPU time 15.49 seconds
Started Mar 10 12:36:45 PM PDT 24
Finished Mar 10 12:37:00 PM PDT 24
Peak memory 273904 kb
Host smart-9458b51a-ed94-49f5-ad45-41e45db27b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669119098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.2669119098
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2700497111
Short name T610
Test name
Test status
Simulation time 10012503500 ps
CPU time 103.63 seconds
Started Mar 10 12:36:42 PM PDT 24
Finished Mar 10 12:38:26 PM PDT 24
Peak memory 318756 kb
Host smart-efa14840-f286-4af5-aeee-24c490b3a853
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700497111 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2700497111
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.1575303260
Short name T723
Test name
Test status
Simulation time 40127789300 ps
CPU time 715.93 seconds
Started Mar 10 12:36:36 PM PDT 24
Finished Mar 10 12:48:33 PM PDT 24
Peak memory 258288 kb
Host smart-8ef5bdd3-b617-4d7f-8611-41de342f3168
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575303260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.1575303260
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.2366778276
Short name T653
Test name
Test status
Simulation time 4607935500 ps
CPU time 122.31 seconds
Started Mar 10 12:36:38 PM PDT 24
Finished Mar 10 12:38:40 PM PDT 24
Peak memory 258588 kb
Host smart-7e3763cd-37c0-4736-aea5-b33ccdcc7c6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366778276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.2366778276
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.1579381803
Short name T31
Test name
Test status
Simulation time 2639951700 ps
CPU time 159.22 seconds
Started Mar 10 12:36:42 PM PDT 24
Finished Mar 10 12:39:21 PM PDT 24
Peak memory 293524 kb
Host smart-76bab5b8-23bf-40a9-8cd4-e13a938f6096
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579381803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.1579381803
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.2151924556
Short name T894
Test name
Test status
Simulation time 35393403700 ps
CPU time 221.36 seconds
Started Mar 10 12:36:42 PM PDT 24
Finished Mar 10 12:40:24 PM PDT 24
Peak memory 289284 kb
Host smart-0e9713c6-03b3-442a-af70-e1a572c05711
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151924556 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.2151924556
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.531245363
Short name T891
Test name
Test status
Simulation time 2017943000 ps
CPU time 86.75 seconds
Started Mar 10 12:36:47 PM PDT 24
Finished Mar 10 12:38:15 PM PDT 24
Peak memory 261800 kb
Host smart-22be5af2-2bd9-46e0-acc9-3e5e15762c98
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531245363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.531245363
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.3387427368
Short name T89
Test name
Test status
Simulation time 28033539200 ps
CPU time 475.45 seconds
Started Mar 10 12:36:41 PM PDT 24
Finished Mar 10 12:44:37 PM PDT 24
Peak memory 273984 kb
Host smart-a1a3c767-6a66-4c8c-a9be-22f284dda3c6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387427368 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.3387427368
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.4083845850
Short name T980
Test name
Test status
Simulation time 156994000 ps
CPU time 109.65 seconds
Started Mar 10 12:36:38 PM PDT 24
Finished Mar 10 12:38:28 PM PDT 24
Peak memory 258840 kb
Host smart-13355557-4836-4955-82ab-26bf58c14527
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083845850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.4083845850
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.1631243385
Short name T3
Test name
Test status
Simulation time 3119102200 ps
CPU time 400.61 seconds
Started Mar 10 12:36:39 PM PDT 24
Finished Mar 10 12:43:21 PM PDT 24
Peak memory 260684 kb
Host smart-ea43ac84-f9c0-4f02-a5b5-c1f2ea2fe860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1631243385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.1631243385
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.3661707981
Short name T1112
Test name
Test status
Simulation time 30624700 ps
CPU time 13.38 seconds
Started Mar 10 12:36:44 PM PDT 24
Finished Mar 10 12:36:57 PM PDT 24
Peak memory 264828 kb
Host smart-83c2bb0b-e4cd-4c74-bd46-fded77fa686b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661707981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.3661707981
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.2020009749
Short name T472
Test name
Test status
Simulation time 81092900 ps
CPU time 223.44 seconds
Started Mar 10 12:36:37 PM PDT 24
Finished Mar 10 12:40:21 PM PDT 24
Peak memory 277280 kb
Host smart-1ec84117-e041-4226-b354-b4e71e880f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020009749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2020009749
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.3622561433
Short name T691
Test name
Test status
Simulation time 540526400 ps
CPU time 36.54 seconds
Started Mar 10 12:36:42 PM PDT 24
Finished Mar 10 12:37:19 PM PDT 24
Peak memory 271908 kb
Host smart-a89e6892-d954-40a9-a57d-eeac8ce665f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622561433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.3622561433
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.2409362165
Short name T1109
Test name
Test status
Simulation time 515131900 ps
CPU time 99.67 seconds
Started Mar 10 12:36:37 PM PDT 24
Finished Mar 10 12:38:17 PM PDT 24
Peak memory 280232 kb
Host smart-74c78ee7-ff07-40b1-a587-bdc1e88bfc15
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409362165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_ro.2409362165
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.1832848326
Short name T749
Test name
Test status
Simulation time 8188044200 ps
CPU time 479.66 seconds
Started Mar 10 12:36:38 PM PDT 24
Finished Mar 10 12:44:38 PM PDT 24
Peak memory 313744 kb
Host smart-a5f88d6f-ab81-40b1-8059-c9c364d524c2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832848326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw.1832848326
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.3717579383
Short name T1116
Test name
Test status
Simulation time 40593000 ps
CPU time 30.28 seconds
Started Mar 10 12:36:44 PM PDT 24
Finished Mar 10 12:37:15 PM PDT 24
Peak memory 265828 kb
Host smart-4bceb4d5-8c1f-464d-9fcd-d0d527889a6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717579383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_rw_evict.3717579383
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.1831829641
Short name T391
Test name
Test status
Simulation time 46367600 ps
CPU time 32.61 seconds
Started Mar 10 12:36:43 PM PDT 24
Finished Mar 10 12:37:16 PM PDT 24
Peak memory 273124 kb
Host smart-5280eb54-288f-462b-9a9f-1d475a8cf943
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831829641 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.1831829641
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.1211158748
Short name T466
Test name
Test status
Simulation time 132455200 ps
CPU time 74.48 seconds
Started Mar 10 12:36:37 PM PDT 24
Finished Mar 10 12:37:51 PM PDT 24
Peak memory 274224 kb
Host smart-bced1215-f267-484e-9f58-8668de09637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211158748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.1211158748
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.51624191
Short name T502
Test name
Test status
Simulation time 23042089500 ps
CPU time 173.45 seconds
Started Mar 10 12:36:39 PM PDT 24
Finished Mar 10 12:39:33 PM PDT 24
Peak memory 264624 kb
Host smart-cdfe1bd7-d348-452c-8404-31981669f2c5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51624191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.flash_ctrl_wo.51624191
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.1099329218
Short name T244
Test name
Test status
Simulation time 29899200 ps
CPU time 13.8 seconds
Started Mar 10 12:36:55 PM PDT 24
Finished Mar 10 12:37:09 PM PDT 24
Peak memory 264396 kb
Host smart-72584751-8bd1-465d-89ae-21a11d95a7d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099329218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
1099329218
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.62029179
Short name T631
Test name
Test status
Simulation time 14652600 ps
CPU time 13.37 seconds
Started Mar 10 12:36:54 PM PDT 24
Finished Mar 10 12:37:08 PM PDT 24
Peak memory 273912 kb
Host smart-865b63f4-100e-4baa-8915-941a8a19adda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62029179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.62029179
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.910871920
Short name T541
Test name
Test status
Simulation time 10037604500 ps
CPU time 54.46 seconds
Started Mar 10 12:36:55 PM PDT 24
Finished Mar 10 12:37:50 PM PDT 24
Peak memory 285656 kb
Host smart-3a3db5ba-4ba8-45e6-89c0-14488ef41f29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910871920 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.910871920
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.2273198642
Short name T743
Test name
Test status
Simulation time 45995000 ps
CPU time 13.5 seconds
Started Mar 10 12:36:56 PM PDT 24
Finished Mar 10 12:37:10 PM PDT 24
Peak memory 264820 kb
Host smart-3eae3050-876c-49b4-8abe-61ee5802d359
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273198642 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.2273198642
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3480094109
Short name T681
Test name
Test status
Simulation time 160195884500 ps
CPU time 818.42 seconds
Started Mar 10 12:36:49 PM PDT 24
Finished Mar 10 12:50:28 PM PDT 24
Peak memory 258640 kb
Host smart-909d2664-3201-4db7-9af9-8b03c4f7f210
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480094109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3480094109
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.541492709
Short name T811
Test name
Test status
Simulation time 1955463900 ps
CPU time 78.69 seconds
Started Mar 10 12:36:48 PM PDT 24
Finished Mar 10 12:38:07 PM PDT 24
Peak memory 261604 kb
Host smart-d86ec7dd-2d5b-419d-88b9-9987a45b862d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541492709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_h
w_sec_otp.541492709
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.1723249228
Short name T565
Test name
Test status
Simulation time 5079542000 ps
CPU time 165.8 seconds
Started Mar 10 12:36:48 PM PDT 24
Finished Mar 10 12:39:35 PM PDT 24
Peak memory 293484 kb
Host smart-513db048-5ad4-4bc2-b707-bf47e2d616b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723249228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.1723249228
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2496063969
Short name T841
Test name
Test status
Simulation time 30427664900 ps
CPU time 213.24 seconds
Started Mar 10 12:36:50 PM PDT 24
Finished Mar 10 12:40:24 PM PDT 24
Peak memory 284312 kb
Host smart-bbf2de47-314a-487e-a1bf-7173ce648dc8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496063969 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.2496063969
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.2218076499
Short name T556
Test name
Test status
Simulation time 1079928000 ps
CPU time 85.04 seconds
Started Mar 10 12:36:47 PM PDT 24
Finished Mar 10 12:38:12 PM PDT 24
Peak memory 258976 kb
Host smart-f66484b2-6254-4195-9ea3-0c7228492c23
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218076499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2
218076499
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.784596521
Short name T132
Test name
Test status
Simulation time 30519000 ps
CPU time 13.7 seconds
Started Mar 10 12:36:55 PM PDT 24
Finished Mar 10 12:37:09 PM PDT 24
Peak memory 264812 kb
Host smart-37032eea-0150-4934-9234-56058313cdbc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784596521 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.784596521
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.3446572413
Short name T1008
Test name
Test status
Simulation time 51702148600 ps
CPU time 678.87 seconds
Started Mar 10 12:36:49 PM PDT 24
Finished Mar 10 12:48:09 PM PDT 24
Peak memory 273136 kb
Host smart-f51264fe-d663-4bde-8bc1-1e3e105c90ab
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446572413 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.3446572413
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.89641254
Short name T825
Test name
Test status
Simulation time 41494700 ps
CPU time 111.18 seconds
Started Mar 10 12:36:49 PM PDT 24
Finished Mar 10 12:38:41 PM PDT 24
Peak memory 259016 kb
Host smart-45718a53-73d5-413e-addb-a84d1869c840
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89641254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp
_reset.89641254
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.2166487229
Short name T62
Test name
Test status
Simulation time 82914700 ps
CPU time 318.64 seconds
Started Mar 10 12:36:48 PM PDT 24
Finished Mar 10 12:42:08 PM PDT 24
Peak memory 260728 kb
Host smart-2c4c49dd-5d69-45c8-b375-84c9c47f6e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166487229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.2166487229
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.2878665886
Short name T959
Test name
Test status
Simulation time 1033370600 ps
CPU time 45.04 seconds
Started Mar 10 12:36:51 PM PDT 24
Finished Mar 10 12:37:36 PM PDT 24
Peak memory 264796 kb
Host smart-0de2a515-b30e-435f-9664-79fc7f571efb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878665886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.2878665886
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.2527862505
Short name T1025
Test name
Test status
Simulation time 3207539700 ps
CPU time 694.15 seconds
Started Mar 10 12:36:50 PM PDT 24
Finished Mar 10 12:48:25 PM PDT 24
Peak memory 283428 kb
Host smart-bb6655e2-0695-4153-b6c4-36bf8b9b2141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527862505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.2527862505
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.2748218379
Short name T706
Test name
Test status
Simulation time 60384600 ps
CPU time 33.34 seconds
Started Mar 10 12:36:56 PM PDT 24
Finished Mar 10 12:37:29 PM PDT 24
Peak memory 265876 kb
Host smart-d2c39c0f-f9d3-4116-a484-39928a230560
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748218379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.2748218379
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.3548761439
Short name T716
Test name
Test status
Simulation time 2480860100 ps
CPU time 103.3 seconds
Started Mar 10 12:36:49 PM PDT 24
Finished Mar 10 12:38:33 PM PDT 24
Peak memory 281160 kb
Host smart-fc8b3f88-1569-43e0-8bb5-ace11c34762b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548761439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_ro.3548761439
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.3316764236
Short name T819
Test name
Test status
Simulation time 11540963200 ps
CPU time 495.75 seconds
Started Mar 10 12:36:48 PM PDT 24
Finished Mar 10 12:45:04 PM PDT 24
Peak memory 313840 kb
Host smart-21f7162b-b47e-4a48-b106-6f357adc1212
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316764236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_rw.3316764236
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.291974685
Short name T863
Test name
Test status
Simulation time 57501600 ps
CPU time 31.56 seconds
Started Mar 10 12:36:53 PM PDT 24
Finished Mar 10 12:37:26 PM PDT 24
Peak memory 272980 kb
Host smart-7713eeb8-d3e7-4667-a6da-f744dbab7eba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291974685 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.291974685
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.1979091518
Short name T375
Test name
Test status
Simulation time 1278412000 ps
CPU time 62.13 seconds
Started Mar 10 12:36:52 PM PDT 24
Finished Mar 10 12:37:54 PM PDT 24
Peak memory 264540 kb
Host smart-d8f2e774-7bcf-4261-96d5-6984ca9989cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979091518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1979091518
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.3034550793
Short name T352
Test name
Test status
Simulation time 25773900 ps
CPU time 119.72 seconds
Started Mar 10 12:36:48 PM PDT 24
Finished Mar 10 12:38:49 PM PDT 24
Peak memory 274648 kb
Host smart-f92c6f0a-8764-456f-9479-6d49140f08af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034550793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.3034550793
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.4086200594
Short name T779
Test name
Test status
Simulation time 1823963200 ps
CPU time 158.12 seconds
Started Mar 10 12:36:48 PM PDT 24
Finished Mar 10 12:39:27 PM PDT 24
Peak memory 264744 kb
Host smart-38187edf-3b37-48f4-8377-28721c695e97
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086200594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.flash_ctrl_wo.4086200594
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.3955036169
Short name T826
Test name
Test status
Simulation time 58609900 ps
CPU time 14.03 seconds
Started Mar 10 12:37:03 PM PDT 24
Finished Mar 10 12:37:17 PM PDT 24
Peak memory 264448 kb
Host smart-a4d8a64b-a5ff-460d-81b2-8c5c99610e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955036169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
3955036169
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1034964278
Short name T282
Test name
Test status
Simulation time 10131039100 ps
CPU time 34.73 seconds
Started Mar 10 12:37:03 PM PDT 24
Finished Mar 10 12:37:38 PM PDT 24
Peak memory 264748 kb
Host smart-7242686c-d4cb-45d7-a7f8-0ba8ddb4cf83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034964278 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.1034964278
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.784447038
Short name T131
Test name
Test status
Simulation time 15408800 ps
CPU time 13.54 seconds
Started Mar 10 12:37:03 PM PDT 24
Finished Mar 10 12:37:17 PM PDT 24
Peak memory 264684 kb
Host smart-8234f7f4-d069-45de-aeb3-291ce009896a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784447038 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.784447038
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.730317265
Short name T685
Test name
Test status
Simulation time 50123737800 ps
CPU time 721 seconds
Started Mar 10 12:36:59 PM PDT 24
Finished Mar 10 12:49:00 PM PDT 24
Peak memory 264220 kb
Host smart-b64a7ad1-3e84-4f11-a31c-3db93ee2e640
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730317265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.flash_ctrl_hw_rma_reset.730317265
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.2760549203
Short name T316
Test name
Test status
Simulation time 3162810300 ps
CPU time 129.55 seconds
Started Mar 10 12:36:57 PM PDT 24
Finished Mar 10 12:39:07 PM PDT 24
Peak memory 261812 kb
Host smart-8c3452b3-24b8-42c7-af07-33f0e9f3f6f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760549203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.2760549203
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.1113196882
Short name T488
Test name
Test status
Simulation time 10008604000 ps
CPU time 220.34 seconds
Started Mar 10 12:36:58 PM PDT 24
Finished Mar 10 12:40:39 PM PDT 24
Peak memory 289388 kb
Host smart-9d9fd578-ee3f-465a-a22c-f8fc5e0a4f2d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113196882 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.1113196882
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.949063110
Short name T1035
Test name
Test status
Simulation time 1991244700 ps
CPU time 87.32 seconds
Started Mar 10 12:36:59 PM PDT 24
Finished Mar 10 12:38:27 PM PDT 24
Peak memory 262196 kb
Host smart-416908a9-9d8f-4432-a027-4c815bd1074d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949063110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.949063110
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.3962777003
Short name T640
Test name
Test status
Simulation time 25831000 ps
CPU time 13.23 seconds
Started Mar 10 12:37:04 PM PDT 24
Finished Mar 10 12:37:17 PM PDT 24
Peak memory 264736 kb
Host smart-495c7390-26a7-43eb-9cd4-346b0468a7c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962777003 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.3962777003
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.3159302497
Short name T105
Test name
Test status
Simulation time 15948331900 ps
CPU time 1049.6 seconds
Started Mar 10 12:36:58 PM PDT 24
Finished Mar 10 12:54:28 PM PDT 24
Peak memory 272716 kb
Host smart-3eaba08e-13cf-4829-a53d-150cb28cf3af
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159302497 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.3159302497
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.1329274226
Short name T113
Test name
Test status
Simulation time 131402800 ps
CPU time 133.89 seconds
Started Mar 10 12:37:00 PM PDT 24
Finished Mar 10 12:39:14 PM PDT 24
Peak memory 258988 kb
Host smart-d8bad3df-1243-4506-b5bd-c3c60c5c7899
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329274226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.1329274226
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.3913859877
Short name T446
Test name
Test status
Simulation time 46436300 ps
CPU time 154.01 seconds
Started Mar 10 12:36:55 PM PDT 24
Finished Mar 10 12:39:29 PM PDT 24
Peak memory 261480 kb
Host smart-a5413c6b-9a60-4530-85d4-b4de58e83e54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913859877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.3913859877
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3981677583
Short name T800
Test name
Test status
Simulation time 35600700 ps
CPU time 13.61 seconds
Started Mar 10 12:37:01 PM PDT 24
Finished Mar 10 12:37:14 PM PDT 24
Peak memory 264616 kb
Host smart-47522232-4a3c-4f2e-8589-769e590d6cab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981677583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.3981677583
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.1084021520
Short name T468
Test name
Test status
Simulation time 16870900 ps
CPU time 76.37 seconds
Started Mar 10 12:36:53 PM PDT 24
Finished Mar 10 12:38:10 PM PDT 24
Peak memory 267468 kb
Host smart-e8248830-9c0d-4d61-a144-4620a48cece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084021520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.1084021520
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.4233105161
Short name T752
Test name
Test status
Simulation time 149329000 ps
CPU time 29.97 seconds
Started Mar 10 12:37:01 PM PDT 24
Finished Mar 10 12:37:32 PM PDT 24
Peak memory 274096 kb
Host smart-9502f267-9710-4226-90ea-526c2871ded6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233105161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.4233105161
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.502485600
Short name T645
Test name
Test status
Simulation time 825892400 ps
CPU time 92.95 seconds
Started Mar 10 12:37:00 PM PDT 24
Finished Mar 10 12:38:34 PM PDT 24
Peak memory 281084 kb
Host smart-b754d994-a5e4-4025-aa37-9f9da0d14606
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502485600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.flash_ctrl_ro.502485600
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.1408122749
Short name T983
Test name
Test status
Simulation time 8452591500 ps
CPU time 493.84 seconds
Started Mar 10 12:36:57 PM PDT 24
Finished Mar 10 12:45:12 PM PDT 24
Peak memory 313292 kb
Host smart-f06b3c0d-0052-4e07-893e-2d0f54cec0e3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408122749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c
trl_rw.1408122749
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.1302994973
Short name T724
Test name
Test status
Simulation time 247068200 ps
CPU time 28.96 seconds
Started Mar 10 12:37:02 PM PDT 24
Finished Mar 10 12:37:31 PM PDT 24
Peak memory 274140 kb
Host smart-d5fc02f1-2064-45ee-a586-de60a115ab2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302994973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.1302994973
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.946329737
Short name T927
Test name
Test status
Simulation time 3210601800 ps
CPU time 69.04 seconds
Started Mar 10 12:37:03 PM PDT 24
Finished Mar 10 12:38:12 PM PDT 24
Peak memory 262652 kb
Host smart-1a416513-14c9-47e2-b3ba-b8b5271f17e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946329737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.946329737
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.1611683681
Short name T578
Test name
Test status
Simulation time 48532200 ps
CPU time 52.94 seconds
Started Mar 10 12:36:55 PM PDT 24
Finished Mar 10 12:37:48 PM PDT 24
Peak memory 269936 kb
Host smart-bba91538-e469-4608-8d72-6c29884c1ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611683681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1611683681
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.1487357159
Short name T946
Test name
Test status
Simulation time 8601589600 ps
CPU time 172.37 seconds
Started Mar 10 12:36:59 PM PDT 24
Finished Mar 10 12:39:52 PM PDT 24
Peak memory 264636 kb
Host smart-0cc89f94-6733-48b0-bfbe-216bb861987f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487357159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.flash_ctrl_wo.1487357159
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.1897577575
Short name T403
Test name
Test status
Simulation time 137355900 ps
CPU time 14.33 seconds
Started Mar 10 12:37:15 PM PDT 24
Finished Mar 10 12:37:30 PM PDT 24
Peak memory 264256 kb
Host smart-a11c1fc8-04b6-4646-a29b-24999388407d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897577575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
1897577575
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.3037955233
Short name T545
Test name
Test status
Simulation time 43590000 ps
CPU time 13.38 seconds
Started Mar 10 12:37:09 PM PDT 24
Finished Mar 10 12:37:22 PM PDT 24
Peak memory 274124 kb
Host smart-fbf9a7f2-045d-4765-94c4-ee2e39ea659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037955233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.3037955233
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.3030298640
Short name T803
Test name
Test status
Simulation time 17466400 ps
CPU time 21.69 seconds
Started Mar 10 12:37:09 PM PDT 24
Finished Mar 10 12:37:32 PM PDT 24
Peak memory 264724 kb
Host smart-bb1cfcab-9c59-40e3-845f-9d27edc472bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030298640 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.3030298640
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1692286498
Short name T144
Test name
Test status
Simulation time 10081976200 ps
CPU time 35.68 seconds
Started Mar 10 12:37:14 PM PDT 24
Finished Mar 10 12:37:50 PM PDT 24
Peak memory 264860 kb
Host smart-019d1363-6125-4620-a501-bbce17ccbeed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692286498 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.1692286498
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.2783195799
Short name T124
Test name
Test status
Simulation time 25869600 ps
CPU time 13.21 seconds
Started Mar 10 12:37:13 PM PDT 24
Finished Mar 10 12:37:26 PM PDT 24
Peak memory 264656 kb
Host smart-2ac6b33d-098c-4e11-9746-06676f2a148d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783195799 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.2783195799
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.902704084
Short name T462
Test name
Test status
Simulation time 160162238600 ps
CPU time 722.72 seconds
Started Mar 10 12:37:22 PM PDT 24
Finished Mar 10 12:49:25 PM PDT 24
Peak memory 263440 kb
Host smart-4682c58d-33e4-4d12-8fa7-22c5fe0f6c26
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902704084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.flash_ctrl_hw_rma_reset.902704084
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.2026322685
Short name T512
Test name
Test status
Simulation time 15440183100 ps
CPU time 143.23 seconds
Started Mar 10 12:37:19 PM PDT 24
Finished Mar 10 12:39:42 PM PDT 24
Peak memory 261284 kb
Host smart-54efc8e3-5143-4a11-b8cc-fd870034c18e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026322685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.2026322685
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.3379761705
Short name T756
Test name
Test status
Simulation time 3661947900 ps
CPU time 159.1 seconds
Started Mar 10 12:37:13 PM PDT 24
Finished Mar 10 12:39:52 PM PDT 24
Peak memory 289292 kb
Host smart-bde463df-1d38-491d-b3b1-b622da3a78fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379761705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.3379761705
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3022590365
Short name T870
Test name
Test status
Simulation time 10083940300 ps
CPU time 198.86 seconds
Started Mar 10 12:37:10 PM PDT 24
Finished Mar 10 12:40:30 PM PDT 24
Peak memory 284156 kb
Host smart-d3259ffa-0cc8-4a68-9674-9730083e9438
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022590365 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.3022590365
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.536781631
Short name T1043
Test name
Test status
Simulation time 1482234800 ps
CPU time 91.42 seconds
Started Mar 10 12:37:12 PM PDT 24
Finished Mar 10 12:38:43 PM PDT 24
Peak memory 259944 kb
Host smart-dec4a762-8ad7-4d49-bb74-44a47dd65cb9
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536781631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.536781631
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.4002220227
Short name T907
Test name
Test status
Simulation time 15069100 ps
CPU time 13.66 seconds
Started Mar 10 12:37:15 PM PDT 24
Finished Mar 10 12:37:29 PM PDT 24
Peak memory 264824 kb
Host smart-8e3ec846-306e-4c0c-89db-4d5176d93dce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002220227 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.4002220227
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.3062606324
Short name T494
Test name
Test status
Simulation time 2665463100 ps
CPU time 104.99 seconds
Started Mar 10 12:37:08 PM PDT 24
Finished Mar 10 12:38:54 PM PDT 24
Peak memory 264644 kb
Host smart-3e5ec919-1fa7-49e6-a66b-b28326daf99a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062606324 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.3062606324
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.2882929709
Short name T575
Test name
Test status
Simulation time 42405200 ps
CPU time 131 seconds
Started Mar 10 12:37:08 PM PDT 24
Finished Mar 10 12:39:19 PM PDT 24
Peak memory 259032 kb
Host smart-a560621a-efa0-4015-896a-016c397f65e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882929709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.2882929709
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.487738079
Short name T626
Test name
Test status
Simulation time 879836200 ps
CPU time 280.38 seconds
Started Mar 10 12:37:04 PM PDT 24
Finished Mar 10 12:41:45 PM PDT 24
Peak memory 264624 kb
Host smart-9f16ca8d-caed-4d5e-a8a8-29f52ba5ea15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487738079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.487738079
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.4271942509
Short name T830
Test name
Test status
Simulation time 74888300 ps
CPU time 14.03 seconds
Started Mar 10 12:37:12 PM PDT 24
Finished Mar 10 12:37:27 PM PDT 24
Peak memory 264748 kb
Host smart-1de17e47-d7a0-468b-bffc-7e9ee4b28598
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271942509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.4271942509
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.541855415
Short name T569
Test name
Test status
Simulation time 692364300 ps
CPU time 508.22 seconds
Started Mar 10 12:37:03 PM PDT 24
Finished Mar 10 12:45:32 PM PDT 24
Peak memory 276832 kb
Host smart-eb744806-c0c3-4673-9810-775dec91a449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541855415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.541855415
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.4057726083
Short name T24
Test name
Test status
Simulation time 174939600 ps
CPU time 33.86 seconds
Started Mar 10 12:37:10 PM PDT 24
Finished Mar 10 12:37:45 PM PDT 24
Peak memory 265916 kb
Host smart-dd8ac0ff-289b-41fd-baf4-4010dc0e9aef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057726083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.4057726083
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.1925239275
Short name T635
Test name
Test status
Simulation time 2395077000 ps
CPU time 94.93 seconds
Started Mar 10 12:37:08 PM PDT 24
Finished Mar 10 12:38:44 PM PDT 24
Peak memory 281100 kb
Host smart-c82bf9e0-78b5-424b-8959-798b4792db7e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925239275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_ro.1925239275
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.3477761799
Short name T68
Test name
Test status
Simulation time 5702493200 ps
CPU time 408.85 seconds
Started Mar 10 12:37:08 PM PDT 24
Finished Mar 10 12:43:58 PM PDT 24
Peak memory 308540 kb
Host smart-b05d56f3-ce58-494c-a833-c69c5b88fab4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477761799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c
trl_rw.3477761799
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.2515980721
Short name T641
Test name
Test status
Simulation time 52340400 ps
CPU time 31.45 seconds
Started Mar 10 12:37:07 PM PDT 24
Finished Mar 10 12:37:39 PM PDT 24
Peak memory 271880 kb
Host smart-33b67a6b-8a66-476c-8746-7ba1813f677e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515980721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.2515980721
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.409653816
Short name T857
Test name
Test status
Simulation time 2033308500 ps
CPU time 68.3 seconds
Started Mar 10 12:37:12 PM PDT 24
Finished Mar 10 12:38:20 PM PDT 24
Peak memory 263620 kb
Host smart-9f4fabbf-900e-4c5c-9a84-546973a92b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409653816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.409653816
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.2560171643
Short name T544
Test name
Test status
Simulation time 97159900 ps
CPU time 97.76 seconds
Started Mar 10 12:37:04 PM PDT 24
Finished Mar 10 12:38:42 PM PDT 24
Peak memory 274876 kb
Host smart-e59dd77d-5106-4fce-9cc1-be71c37eec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560171643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2560171643
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.1967451590
Short name T96
Test name
Test status
Simulation time 3801688400 ps
CPU time 153.35 seconds
Started Mar 10 12:37:10 PM PDT 24
Finished Mar 10 12:39:44 PM PDT 24
Peak memory 264696 kb
Host smart-ffbc1021-a7d5-4ec6-8c38-ae06f9399a6e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967451590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.flash_ctrl_wo.1967451590
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.3362812718
Short name T170
Test name
Test status
Simulation time 43181100 ps
CPU time 13.81 seconds
Started Mar 10 12:37:25 PM PDT 24
Finished Mar 10 12:37:39 PM PDT 24
Peak memory 264404 kb
Host smart-bf58fa42-7208-418d-ba54-cd374ed24f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362812718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
3362812718
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.1477383525
Short name T932
Test name
Test status
Simulation time 16676700 ps
CPU time 15.39 seconds
Started Mar 10 12:37:22 PM PDT 24
Finished Mar 10 12:37:37 PM PDT 24
Peak memory 273856 kb
Host smart-70825e88-94d8-428b-bf00-baa0a6739cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477383525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.1477383525
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.331142058
Short name T986
Test name
Test status
Simulation time 10019543900 ps
CPU time 85.63 seconds
Started Mar 10 12:37:20 PM PDT 24
Finished Mar 10 12:38:46 PM PDT 24
Peak memory 321184 kb
Host smart-cfe2b819-25d3-429e-a476-73578062bc40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331142058 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.331142058
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.2757805001
Short name T332
Test name
Test status
Simulation time 15211300 ps
CPU time 13.45 seconds
Started Mar 10 12:37:18 PM PDT 24
Finished Mar 10 12:37:32 PM PDT 24
Peak memory 264720 kb
Host smart-dc5b71d3-9b3c-4ea1-9d13-bd6fd90d243d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757805001 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.2757805001
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.711197853
Short name T757
Test name
Test status
Simulation time 60135022800 ps
CPU time 766.69 seconds
Started Mar 10 12:37:22 PM PDT 24
Finished Mar 10 12:50:09 PM PDT 24
Peak memory 258344 kb
Host smart-e2bdfb56-ea63-4c97-a427-4a6f79cd9e60
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711197853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.flash_ctrl_hw_rma_reset.711197853
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2769767711
Short name T1103
Test name
Test status
Simulation time 830627600 ps
CPU time 35.69 seconds
Started Mar 10 12:37:15 PM PDT 24
Finished Mar 10 12:37:51 PM PDT 24
Peak memory 258544 kb
Host smart-a9e20573-c7b4-4db7-83ed-8985e95b239f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769767711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.2769767711
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.3099589230
Short name T788
Test name
Test status
Simulation time 4544494100 ps
CPU time 172.75 seconds
Started Mar 10 12:37:18 PM PDT 24
Finished Mar 10 12:40:11 PM PDT 24
Peak memory 290452 kb
Host smart-f526ec00-ef57-42c5-92b1-25d6b7400fe2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099589230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.3099589230
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3554593661
Short name T950
Test name
Test status
Simulation time 16167426000 ps
CPU time 182.16 seconds
Started Mar 10 12:37:20 PM PDT 24
Finished Mar 10 12:40:22 PM PDT 24
Peak memory 284128 kb
Host smart-34081545-24e2-480d-8f93-f3f0859525d5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554593661 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.3554593661
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.3483364561
Short name T204
Test name
Test status
Simulation time 1067020200 ps
CPU time 77.66 seconds
Started Mar 10 12:37:19 PM PDT 24
Finished Mar 10 12:38:36 PM PDT 24
Peak memory 259076 kb
Host smart-114ea612-7566-43fb-bb2f-181700bc08ce
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483364561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.3
483364561
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.3126095593
Short name T186
Test name
Test status
Simulation time 60359200 ps
CPU time 13.25 seconds
Started Mar 10 12:37:19 PM PDT 24
Finished Mar 10 12:37:32 PM PDT 24
Peak memory 264652 kb
Host smart-b8866a28-60f2-4143-9a77-939bcd12b053
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126095593 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.3126095593
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.2353977663
Short name T88
Test name
Test status
Simulation time 17143119200 ps
CPU time 519.37 seconds
Started Mar 10 12:37:21 PM PDT 24
Finished Mar 10 12:46:01 PM PDT 24
Peak memory 272928 kb
Host smart-00258024-9850-4104-976e-5aad61d64f17
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353977663 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.2353977663
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.3816751145
Short name T712
Test name
Test status
Simulation time 77024700 ps
CPU time 130.61 seconds
Started Mar 10 12:37:18 PM PDT 24
Finished Mar 10 12:39:29 PM PDT 24
Peak memory 259148 kb
Host smart-69910af5-25e0-4ca4-ac17-5bc1a20f3bf4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816751145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.3816751145
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.1822063482
Short name T67
Test name
Test status
Simulation time 19614960700 ps
CPU time 490.31 seconds
Started Mar 10 12:37:14 PM PDT 24
Finished Mar 10 12:45:24 PM PDT 24
Peak memory 261532 kb
Host smart-e13d64d8-4d75-4a0f-bd86-a50c16150182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1822063482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.1822063482
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.1996668492
Short name T489
Test name
Test status
Simulation time 170190600 ps
CPU time 15.98 seconds
Started Mar 10 12:37:20 PM PDT 24
Finished Mar 10 12:37:36 PM PDT 24
Peak memory 264672 kb
Host smart-cf71f250-f3ae-4d3d-b2b0-103811f6b79d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996668492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.1996668492
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.3401658315
Short name T486
Test name
Test status
Simulation time 368706300 ps
CPU time 496.22 seconds
Started Mar 10 12:37:13 PM PDT 24
Finished Mar 10 12:45:30 PM PDT 24
Peak memory 282092 kb
Host smart-6364ff94-23d3-4726-b61b-da7b010b95b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401658315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3401658315
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3188008544
Short name T854
Test name
Test status
Simulation time 143141700 ps
CPU time 33.54 seconds
Started Mar 10 12:37:19 PM PDT 24
Finished Mar 10 12:37:53 PM PDT 24
Peak memory 274052 kb
Host smart-69b230d6-f881-4560-9e79-2d5b8260d243
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188008544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3188008544
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.3919030094
Short name T198
Test name
Test status
Simulation time 453485200 ps
CPU time 98.48 seconds
Started Mar 10 12:37:19 PM PDT 24
Finished Mar 10 12:38:58 PM PDT 24
Peak memory 280300 kb
Host smart-9c180690-f2cc-4d47-bb53-74e53a6f3588
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919030094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_ro.3919030094
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.254948827
Short name T837
Test name
Test status
Simulation time 7197145600 ps
CPU time 621.3 seconds
Started Mar 10 12:37:22 PM PDT 24
Finished Mar 10 12:47:43 PM PDT 24
Peak memory 313956 kb
Host smart-623d97ad-d3c2-4287-b4ca-1bd0ed5652b4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254948827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ct
rl_rw.254948827
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.3583090265
Short name T1110
Test name
Test status
Simulation time 99697500 ps
CPU time 32.02 seconds
Started Mar 10 12:37:20 PM PDT 24
Finished Mar 10 12:37:52 PM PDT 24
Peak memory 273028 kb
Host smart-2402121d-01ce-4329-ab49-c54f7395e112
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583090265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.3583090265
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.2330265655
Short name T1115
Test name
Test status
Simulation time 55429900 ps
CPU time 31.44 seconds
Started Mar 10 12:37:20 PM PDT 24
Finished Mar 10 12:37:51 PM PDT 24
Peak memory 273148 kb
Host smart-65002101-4f93-416c-a60b-ef2e74226703
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330265655 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.2330265655
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.3967018225
Short name T1011
Test name
Test status
Simulation time 2871282100 ps
CPU time 70.85 seconds
Started Mar 10 12:37:21 PM PDT 24
Finished Mar 10 12:38:32 PM PDT 24
Peak memory 258944 kb
Host smart-40e246a1-5022-40c7-b163-32446998ca6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967018225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3967018225
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.2168715655
Short name T970
Test name
Test status
Simulation time 29611900 ps
CPU time 123.35 seconds
Started Mar 10 12:37:13 PM PDT 24
Finished Mar 10 12:39:16 PM PDT 24
Peak memory 276112 kb
Host smart-36a055a0-4b70-488a-9ba6-386693b8a94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168715655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.2168715655
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.984560899
Short name T871
Test name
Test status
Simulation time 8377924700 ps
CPU time 157.61 seconds
Started Mar 10 12:37:20 PM PDT 24
Finished Mar 10 12:39:58 PM PDT 24
Peak memory 264640 kb
Host smart-216511c0-1071-4396-8c43-6cc1cfea752d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984560899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_wo.984560899
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.3300389972
Short name T775
Test name
Test status
Simulation time 30469000 ps
CPU time 13.6 seconds
Started Mar 10 12:37:35 PM PDT 24
Finished Mar 10 12:37:49 PM PDT 24
Peak memory 264208 kb
Host smart-277d6215-2d93-4748-b229-3311428d3409
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300389972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
3300389972
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.1633108881
Short name T844
Test name
Test status
Simulation time 16358300 ps
CPU time 15.62 seconds
Started Mar 10 12:37:33 PM PDT 24
Finished Mar 10 12:37:49 PM PDT 24
Peak memory 274824 kb
Host smart-75c8c86c-909f-4228-bf70-b6df93096f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633108881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1633108881
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.2277385481
Short name T2
Test name
Test status
Simulation time 73681200 ps
CPU time 21.89 seconds
Started Mar 10 12:37:38 PM PDT 24
Finished Mar 10 12:38:00 PM PDT 24
Peak memory 272956 kb
Host smart-50e577a7-f01d-4cab-94f0-c535b4c6d7a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277385481 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.2277385481
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.978299972
Short name T284
Test name
Test status
Simulation time 10012647400 ps
CPU time 306.75 seconds
Started Mar 10 12:37:31 PM PDT 24
Finished Mar 10 12:42:38 PM PDT 24
Peak memory 319536 kb
Host smart-8b5784c2-cbc8-40eb-b9e5-192ac5f00e9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978299972 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.978299972
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.185858888
Short name T1108
Test name
Test status
Simulation time 31871500 ps
CPU time 13.78 seconds
Started Mar 10 12:37:34 PM PDT 24
Finished Mar 10 12:37:48 PM PDT 24
Peak memory 264828 kb
Host smart-63c501c5-878e-4256-b706-f8b6156da08b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185858888 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.185858888
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.3799596432
Short name T160
Test name
Test status
Simulation time 130164565800 ps
CPU time 787.59 seconds
Started Mar 10 12:37:26 PM PDT 24
Finished Mar 10 12:50:35 PM PDT 24
Peak memory 263536 kb
Host smart-7827d819-bebf-4820-ab51-b2436ef34181
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799596432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.3799596432
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.2233945233
Short name T300
Test name
Test status
Simulation time 4673574300 ps
CPU time 106.91 seconds
Started Mar 10 12:37:28 PM PDT 24
Finished Mar 10 12:39:15 PM PDT 24
Peak memory 261604 kb
Host smart-92018536-26d3-4938-95eb-6c91035a2b2e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233945233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.2233945233
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.3404865787
Short name T776
Test name
Test status
Simulation time 2444029000 ps
CPU time 151.66 seconds
Started Mar 10 12:37:30 PM PDT 24
Finished Mar 10 12:40:02 PM PDT 24
Peak memory 289288 kb
Host smart-38927482-b7fb-4d0d-9126-391408034e55
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404865787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.3404865787
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2811417611
Short name T928
Test name
Test status
Simulation time 9445076200 ps
CPU time 328.13 seconds
Started Mar 10 12:37:26 PM PDT 24
Finished Mar 10 12:42:56 PM PDT 24
Peak memory 283996 kb
Host smart-f4848c5c-7408-4b25-99c3-e2bfbf234d35
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811417611 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.2811417611
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.1159636901
Short name T286
Test name
Test status
Simulation time 15375500 ps
CPU time 13.43 seconds
Started Mar 10 12:37:30 PM PDT 24
Finished Mar 10 12:37:43 PM PDT 24
Peak memory 264692 kb
Host smart-91fefa4e-ab49-464b-82f7-4de7c3ce944f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159636901 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.1159636901
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.2264806945
Short name T150
Test name
Test status
Simulation time 77412600 ps
CPU time 135.57 seconds
Started Mar 10 12:37:27 PM PDT 24
Finished Mar 10 12:39:43 PM PDT 24
Peak memory 258920 kb
Host smart-5258afc2-b791-4150-82dd-bbc6c371b9db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264806945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.2264806945
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.1830059150
Short name T859
Test name
Test status
Simulation time 735918900 ps
CPU time 301.02 seconds
Started Mar 10 12:37:26 PM PDT 24
Finished Mar 10 12:42:28 PM PDT 24
Peak memory 260796 kb
Host smart-bb5b1b07-8994-4104-8131-45a08edc7627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830059150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.1830059150
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.4057020261
Short name T695
Test name
Test status
Simulation time 314116600 ps
CPU time 24.38 seconds
Started Mar 10 12:37:27 PM PDT 24
Finished Mar 10 12:37:52 PM PDT 24
Peak memory 264732 kb
Host smart-8802e4d9-8117-4a45-86f1-5fc6fbd497b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057020261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.4057020261
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.1974274907
Short name T850
Test name
Test status
Simulation time 1554065400 ps
CPU time 513.1 seconds
Started Mar 10 12:37:27 PM PDT 24
Finished Mar 10 12:46:01 PM PDT 24
Peak memory 281020 kb
Host smart-443ae39f-153f-40cc-aa85-b03b0c0f941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974274907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.1974274907
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.450551479
Short name T187
Test name
Test status
Simulation time 515487400 ps
CPU time 39.17 seconds
Started Mar 10 12:37:30 PM PDT 24
Finished Mar 10 12:38:09 PM PDT 24
Peak memory 272944 kb
Host smart-5624e3fc-5bfa-4c59-aa71-0da0e788fb85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450551479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_re_evict.450551479
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.1321994714
Short name T595
Test name
Test status
Simulation time 2380603500 ps
CPU time 106.59 seconds
Started Mar 10 12:37:26 PM PDT 24
Finished Mar 10 12:39:14 PM PDT 24
Peak memory 281008 kb
Host smart-e22e3e19-de35-473f-9b37-b2c9b43835db
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321994714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_ro.1321994714
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.3478695858
Short name T478
Test name
Test status
Simulation time 4491867000 ps
CPU time 484.64 seconds
Started Mar 10 12:37:35 PM PDT 24
Finished Mar 10 12:45:40 PM PDT 24
Peak memory 313828 kb
Host smart-3ece6904-c193-4e80-a167-a4b2a26f9f3e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478695858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw.3478695858
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.2234326163
Short name T1023
Test name
Test status
Simulation time 168723100 ps
CPU time 32.81 seconds
Started Mar 10 12:37:26 PM PDT 24
Finished Mar 10 12:38:00 PM PDT 24
Peak memory 273192 kb
Host smart-4721dd59-2844-4289-b73d-d72646c6d1df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234326163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.2234326163
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.2153883645
Short name T909
Test name
Test status
Simulation time 88063600 ps
CPU time 30.99 seconds
Started Mar 10 12:37:30 PM PDT 24
Finished Mar 10 12:38:01 PM PDT 24
Peak memory 272988 kb
Host smart-94d5b8cf-16eb-49ed-a69c-ed8fc73ea056
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153883645 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.2153883645
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.1309437782
Short name T343
Test name
Test status
Simulation time 664667000 ps
CPU time 65.57 seconds
Started Mar 10 12:37:33 PM PDT 24
Finished Mar 10 12:38:38 PM PDT 24
Peak memory 262312 kb
Host smart-37b508fb-9295-43d5-9765-5913714cd6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309437782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1309437782
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.861039996
Short name T790
Test name
Test status
Simulation time 92564200 ps
CPU time 75.01 seconds
Started Mar 10 12:37:27 PM PDT 24
Finished Mar 10 12:38:42 PM PDT 24
Peak memory 274244 kb
Host smart-889d708f-2287-412e-9ea5-61cbab8e2073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861039996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.861039996
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.2907198850
Short name T448
Test name
Test status
Simulation time 4166009500 ps
CPU time 177.44 seconds
Started Mar 10 12:37:26 PM PDT 24
Finished Mar 10 12:40:23 PM PDT 24
Peak memory 264712 kb
Host smart-1a5036bc-14df-49f2-af4d-c016e48bdc35
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907198850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.flash_ctrl_wo.2907198850
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.1360693288
Short name T477
Test name
Test status
Simulation time 35427300 ps
CPU time 13.74 seconds
Started Mar 10 12:37:41 PM PDT 24
Finished Mar 10 12:37:55 PM PDT 24
Peak memory 264344 kb
Host smart-8aac8a81-b199-4955-a011-ba895a1d30a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360693288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
1360693288
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.2808659488
Short name T602
Test name
Test status
Simulation time 27876700 ps
CPU time 13.23 seconds
Started Mar 10 12:37:40 PM PDT 24
Finished Mar 10 12:37:54 PM PDT 24
Peak memory 273852 kb
Host smart-5f847b25-3152-42ce-871c-b3894cb318e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808659488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.2808659488
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2375272778
Short name T283
Test name
Test status
Simulation time 10019889000 ps
CPU time 82.01 seconds
Started Mar 10 12:37:36 PM PDT 24
Finished Mar 10 12:38:59 PM PDT 24
Peak memory 319800 kb
Host smart-2957107a-6c8f-4ea3-a275-992baae4056f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375272778 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2375272778
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.4187032505
Short name T922
Test name
Test status
Simulation time 24923100 ps
CPU time 13.85 seconds
Started Mar 10 12:37:36 PM PDT 24
Finished Mar 10 12:37:50 PM PDT 24
Peak memory 264792 kb
Host smart-b8ab399b-949c-41fa-9849-5b7d5177620e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187032505 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.4187032505
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.1736941344
Short name T139
Test name
Test status
Simulation time 140169070000 ps
CPU time 707.64 seconds
Started Mar 10 12:37:30 PM PDT 24
Finished Mar 10 12:49:18 PM PDT 24
Peak memory 262612 kb
Host smart-a6a03da2-2669-4d80-a5d4-28547c338aab
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736941344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.1736941344
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3121080748
Short name T620
Test name
Test status
Simulation time 36050141100 ps
CPU time 99.03 seconds
Started Mar 10 12:37:31 PM PDT 24
Finished Mar 10 12:39:11 PM PDT 24
Peak memory 258408 kb
Host smart-afe60c99-bdac-4812-8bf2-92576be9090d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121080748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.3121080748
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.3695212602
Short name T656
Test name
Test status
Simulation time 1914772800 ps
CPU time 148.19 seconds
Started Mar 10 12:37:34 PM PDT 24
Finished Mar 10 12:40:03 PM PDT 24
Peak memory 294004 kb
Host smart-6ee181cf-c1cf-40c0-909e-29f523fa5185
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695212602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.3695212602
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.896698327
Short name T676
Test name
Test status
Simulation time 17315039000 ps
CPU time 198.23 seconds
Started Mar 10 12:37:35 PM PDT 24
Finished Mar 10 12:40:53 PM PDT 24
Peak memory 284220 kb
Host smart-e2f165b8-6603-41cf-b072-ea3cb4064748
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896698327 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.896698327
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.2116844334
Short name T719
Test name
Test status
Simulation time 975489500 ps
CPU time 74.34 seconds
Started Mar 10 12:37:31 PM PDT 24
Finished Mar 10 12:38:45 PM PDT 24
Peak memory 262260 kb
Host smart-ff2dbec0-6a83-4056-b3c0-19675e6a3a19
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116844334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2
116844334
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.3299597059
Short name T957
Test name
Test status
Simulation time 31702700 ps
CPU time 13.3 seconds
Started Mar 10 12:37:45 PM PDT 24
Finished Mar 10 12:37:59 PM PDT 24
Peak memory 264600 kb
Host smart-4f9fe82e-b3b0-4353-bc7a-a374a3dfd0d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299597059 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.3299597059
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.2309566034
Short name T75
Test name
Test status
Simulation time 69280626700 ps
CPU time 286.66 seconds
Started Mar 10 12:37:28 PM PDT 24
Finished Mar 10 12:42:16 PM PDT 24
Peak memory 272980 kb
Host smart-d55ad2d7-d216-46e7-ac66-cc9916016086
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309566034 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.2309566034
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.544913874
Short name T151
Test name
Test status
Simulation time 400208100 ps
CPU time 134.59 seconds
Started Mar 10 12:37:32 PM PDT 24
Finished Mar 10 12:39:47 PM PDT 24
Peak memory 260164 kb
Host smart-bed12d7d-5ad2-48d9-8450-a57088f2b757
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544913874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ot
p_reset.544913874
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.4272656424
Short name T1048
Test name
Test status
Simulation time 700290100 ps
CPU time 293.68 seconds
Started Mar 10 12:37:30 PM PDT 24
Finished Mar 10 12:42:24 PM PDT 24
Peak memory 264592 kb
Host smart-db490d07-f0a0-4b3d-b013-aadea09cafc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272656424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.4272656424
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.3357531055
Short name T464
Test name
Test status
Simulation time 74294200 ps
CPU time 16.03 seconds
Started Mar 10 12:37:33 PM PDT 24
Finished Mar 10 12:37:49 PM PDT 24
Peak memory 264712 kb
Host smart-152a8844-8e62-466d-b9ec-3671e24b64df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357531055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.3357531055
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.1680722872
Short name T828
Test name
Test status
Simulation time 198518500 ps
CPU time 300.79 seconds
Started Mar 10 12:37:38 PM PDT 24
Finished Mar 10 12:42:39 PM PDT 24
Peak memory 279736 kb
Host smart-90270f7b-40de-4968-934a-6d23cf4c520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680722872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.1680722872
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.2325184952
Short name T471
Test name
Test status
Simulation time 405821200 ps
CPU time 99.11 seconds
Started Mar 10 12:37:32 PM PDT 24
Finished Mar 10 12:39:12 PM PDT 24
Peak memory 280300 kb
Host smart-d5e54a2b-96fe-4ccd-a70f-805fefbdc3d0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325184952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_ro.2325184952
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.601955471
Short name T1084
Test name
Test status
Simulation time 8171731100 ps
CPU time 515.61 seconds
Started Mar 10 12:37:38 PM PDT 24
Finished Mar 10 12:46:14 PM PDT 24
Peak memory 313248 kb
Host smart-1833f25f-601e-4fb6-97e1-ee879e193db7
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601955471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ct
rl_rw.601955471
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.2881311875
Short name T711
Test name
Test status
Simulation time 30323100 ps
CPU time 31.03 seconds
Started Mar 10 12:37:30 PM PDT 24
Finished Mar 10 12:38:02 PM PDT 24
Peak memory 273104 kb
Host smart-28e2d290-496a-475a-b65d-954be7ac7805
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881311875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.2881311875
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.1276232060
Short name T956
Test name
Test status
Simulation time 55682200 ps
CPU time 31.58 seconds
Started Mar 10 12:37:36 PM PDT 24
Finished Mar 10 12:38:08 PM PDT 24
Peak memory 275380 kb
Host smart-c68f3cbc-3b3a-471b-97a0-d11c2ddbafe4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276232060 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.1276232060
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.3396772702
Short name T373
Test name
Test status
Simulation time 4272493600 ps
CPU time 69.21 seconds
Started Mar 10 12:37:34 PM PDT 24
Finished Mar 10 12:38:44 PM PDT 24
Peak memory 263704 kb
Host smart-abb6f7b5-7005-4ea5-a9dc-7a9a21eb3bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396772702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3396772702
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.212514523
Short name T236
Test name
Test status
Simulation time 45211300 ps
CPU time 76.85 seconds
Started Mar 10 12:37:31 PM PDT 24
Finished Mar 10 12:38:48 PM PDT 24
Peak memory 275236 kb
Host smart-1b13db9a-1989-4cd8-b6fe-18777f64ac79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212514523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.212514523
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.1615911273
Short name T82
Test name
Test status
Simulation time 2141070800 ps
CPU time 145.65 seconds
Started Mar 10 12:37:34 PM PDT 24
Finished Mar 10 12:40:00 PM PDT 24
Peak memory 264748 kb
Host smart-d4b8fbc9-458c-410a-b02a-fffb2770acff
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615911273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.flash_ctrl_wo.1615911273
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.571710447
Short name T171
Test name
Test status
Simulation time 47469900 ps
CPU time 13.56 seconds
Started Mar 10 12:37:39 PM PDT 24
Finished Mar 10 12:37:53 PM PDT 24
Peak memory 263772 kb
Host smart-c0b23bcc-c219-4a50-9c96-21ef37290cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571710447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.571710447
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.283401572
Short name T423
Test name
Test status
Simulation time 201545800 ps
CPU time 16.03 seconds
Started Mar 10 12:37:40 PM PDT 24
Finished Mar 10 12:37:57 PM PDT 24
Peak memory 273856 kb
Host smart-3e28df7f-ddf0-4de4-8925-0b31b5f0d2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283401572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.283401572
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.4293500569
Short name T174
Test name
Test status
Simulation time 20053200 ps
CPU time 21.51 seconds
Started Mar 10 12:37:39 PM PDT 24
Finished Mar 10 12:38:01 PM PDT 24
Peak memory 273024 kb
Host smart-bd28bcff-4692-4512-b151-31698c3f50dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293500569 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.4293500569
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3080544178
Short name T162
Test name
Test status
Simulation time 10012047500 ps
CPU time 147.69 seconds
Started Mar 10 12:37:40 PM PDT 24
Finished Mar 10 12:40:08 PM PDT 24
Peak memory 375648 kb
Host smart-d653297b-ea45-47c2-b148-2b4956cc7af9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080544178 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3080544178
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.2988544170
Short name T735
Test name
Test status
Simulation time 26650500 ps
CPU time 13.49 seconds
Started Mar 10 12:37:40 PM PDT 24
Finished Mar 10 12:37:54 PM PDT 24
Peak memory 264756 kb
Host smart-54053142-60dd-4c6e-8b2e-2ade3fdfc8e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988544170 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.2988544170
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.2560342782
Short name T862
Test name
Test status
Simulation time 8151310100 ps
CPU time 74.98 seconds
Started Mar 10 12:37:34 PM PDT 24
Finished Mar 10 12:38:49 PM PDT 24
Peak memory 261404 kb
Host smart-bfe8df04-6a48-4080-98db-3fe92fc7dea0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560342782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.2560342782
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.1131857813
Short name T890
Test name
Test status
Simulation time 1395613900 ps
CPU time 160.11 seconds
Started Mar 10 12:37:36 PM PDT 24
Finished Mar 10 12:40:16 PM PDT 24
Peak memory 289392 kb
Host smart-0bb691db-7aa8-4ad2-a269-b4dc5e72e743
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131857813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.1131857813
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.537889614
Short name T328
Test name
Test status
Simulation time 36696362800 ps
CPU time 256.87 seconds
Started Mar 10 12:37:35 PM PDT 24
Finished Mar 10 12:41:52 PM PDT 24
Peak memory 293484 kb
Host smart-acc5aca8-4cdc-4700-8cca-3acf3e2373b4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537889614 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.537889614
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.3114377816
Short name T896
Test name
Test status
Simulation time 4026657300 ps
CPU time 71.08 seconds
Started Mar 10 12:37:36 PM PDT 24
Finished Mar 10 12:38:47 PM PDT 24
Peak memory 258984 kb
Host smart-bd549fd1-c2f3-4760-825c-45e43287dcaf
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114377816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3
114377816
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.2194718562
Short name T460
Test name
Test status
Simulation time 14943000 ps
CPU time 13.84 seconds
Started Mar 10 12:37:38 PM PDT 24
Finished Mar 10 12:37:52 PM PDT 24
Peak memory 264712 kb
Host smart-c4045103-8941-4fd3-bf9d-abafbcdf1586
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194718562 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.2194718562
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.740229281
Short name T690
Test name
Test status
Simulation time 218544300 ps
CPU time 132.3 seconds
Started Mar 10 12:37:41 PM PDT 24
Finished Mar 10 12:39:53 PM PDT 24
Peak memory 259164 kb
Host smart-3cd30e2e-8b2f-4909-8ac7-8982f8093f5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740229281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ot
p_reset.740229281
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.9841438
Short name T853
Test name
Test status
Simulation time 2830930800 ps
CPU time 364.31 seconds
Started Mar 10 12:37:34 PM PDT 24
Finished Mar 10 12:43:39 PM PDT 24
Peak memory 261700 kb
Host smart-2c33abeb-601b-4e01-a28b-445feb5e49d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9841438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.9841438
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.1448737178
Short name T447
Test name
Test status
Simulation time 159435800 ps
CPU time 24.31 seconds
Started Mar 10 12:37:36 PM PDT 24
Finished Mar 10 12:38:00 PM PDT 24
Peak memory 264804 kb
Host smart-43621c18-8168-4e4b-9a76-03db14ff550e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448737178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.1448737178
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.3774516879
Short name T860
Test name
Test status
Simulation time 8797832200 ps
CPU time 1453.58 seconds
Started Mar 10 12:37:35 PM PDT 24
Finished Mar 10 01:01:49 PM PDT 24
Peak memory 287300 kb
Host smart-1355d085-da33-43ba-8957-6c6a73e42891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774516879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.3774516879
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.2459640690
Short name T382
Test name
Test status
Simulation time 108423300 ps
CPU time 34.89 seconds
Started Mar 10 12:37:40 PM PDT 24
Finished Mar 10 12:38:15 PM PDT 24
Peak memory 273092 kb
Host smart-1d901e29-a279-42e7-b727-0b0c5cad6b8b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459640690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.2459640690
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.1986533235
Short name T1111
Test name
Test status
Simulation time 838891000 ps
CPU time 91.1 seconds
Started Mar 10 12:37:36 PM PDT 24
Finished Mar 10 12:39:07 PM PDT 24
Peak memory 288616 kb
Host smart-d949215a-b8d7-4263-ade6-cd180ea43dcf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986533235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_ro.1986533235
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.898102927
Short name T795
Test name
Test status
Simulation time 2893430900 ps
CPU time 436.16 seconds
Started Mar 10 12:37:37 PM PDT 24
Finished Mar 10 12:44:53 PM PDT 24
Peak memory 313856 kb
Host smart-c0898b20-85fb-4314-a088-f553f6106ccc
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898102927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ct
rl_rw.898102927
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.1510950383
Short name T878
Test name
Test status
Simulation time 33321300 ps
CPU time 31.67 seconds
Started Mar 10 12:37:40 PM PDT 24
Finished Mar 10 12:38:12 PM PDT 24
Peak memory 271944 kb
Host smart-13a72a8d-6e88-41c2-ab2c-f435b4c75446
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510950383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.1510950383
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.3021675293
Short name T394
Test name
Test status
Simulation time 51453800 ps
CPU time 31.05 seconds
Started Mar 10 12:37:36 PM PDT 24
Finished Mar 10 12:38:07 PM PDT 24
Peak memory 273156 kb
Host smart-546050a8-f000-425e-9e6f-4f58dd944868
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021675293 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.3021675293
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.4252731333
Short name T166
Test name
Test status
Simulation time 6256641500 ps
CPU time 77.83 seconds
Started Mar 10 12:37:47 PM PDT 24
Finished Mar 10 12:39:06 PM PDT 24
Peak memory 263524 kb
Host smart-04bfd8d0-4cc7-4f46-8b9b-5d36c8758b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252731333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.4252731333
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.265518005
Short name T972
Test name
Test status
Simulation time 82075800 ps
CPU time 119.41 seconds
Started Mar 10 12:37:36 PM PDT 24
Finished Mar 10 12:39:36 PM PDT 24
Peak memory 277040 kb
Host smart-68cc9507-a0db-4ccd-9cf3-8f58f087fe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265518005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.265518005
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.2673218151
Short name T508
Test name
Test status
Simulation time 4506141200 ps
CPU time 176.06 seconds
Started Mar 10 12:37:44 PM PDT 24
Finished Mar 10 12:40:41 PM PDT 24
Peak memory 264676 kb
Host smart-9e48cc1b-d2a1-484e-bdee-b3022fa7d644
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673218151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.flash_ctrl_wo.2673218151
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.3767882645
Short name T848
Test name
Test status
Simulation time 32665500 ps
CPU time 13.41 seconds
Started Mar 10 12:37:45 PM PDT 24
Finished Mar 10 12:37:59 PM PDT 24
Peak memory 264284 kb
Host smart-877915d8-2d9d-46da-9774-b086c8f6df95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767882645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
3767882645
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.1474746012
Short name T998
Test name
Test status
Simulation time 26110000 ps
CPU time 15.83 seconds
Started Mar 10 12:37:44 PM PDT 24
Finished Mar 10 12:38:00 PM PDT 24
Peak memory 273836 kb
Host smart-79328571-05e2-4d57-a511-e2593ac0ff3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474746012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.1474746012
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.835793933
Short name T1105
Test name
Test status
Simulation time 10019388900 ps
CPU time 163.36 seconds
Started Mar 10 12:37:45 PM PDT 24
Finished Mar 10 12:40:29 PM PDT 24
Peak memory 280416 kb
Host smart-aa2bd1c3-4e62-4370-85d4-4ee38378c311
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835793933 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.835793933
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.4284468213
Short name T271
Test name
Test status
Simulation time 38945200 ps
CPU time 13.59 seconds
Started Mar 10 12:37:44 PM PDT 24
Finished Mar 10 12:37:58 PM PDT 24
Peak memory 264796 kb
Host smart-b1f3f61d-ddea-47d5-b6a2-f9ccf2faca02
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284468213 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.4284468213
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.2720093340
Short name T155
Test name
Test status
Simulation time 320275865400 ps
CPU time 1099.68 seconds
Started Mar 10 12:37:47 PM PDT 24
Finished Mar 10 12:56:08 PM PDT 24
Peak memory 258440 kb
Host smart-cac5f2ba-803b-48b2-9800-2fea2d057b42
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720093340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.2720093340
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2053126047
Short name T396
Test name
Test status
Simulation time 6336382000 ps
CPU time 88.98 seconds
Started Mar 10 12:37:39 PM PDT 24
Finished Mar 10 12:39:08 PM PDT 24
Peak memory 258384 kb
Host smart-36955f52-68cd-4468-ad64-75ddd5aac242
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053126047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.2053126047
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.1886473851
Short name T654
Test name
Test status
Simulation time 1032215300 ps
CPU time 145.87 seconds
Started Mar 10 12:37:41 PM PDT 24
Finished Mar 10 12:40:07 PM PDT 24
Peak memory 294268 kb
Host smart-feb8ce76-e5c2-4624-87e5-4f2c64afb1dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886473851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.1886473851
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1760970598
Short name T597
Test name
Test status
Simulation time 32359686200 ps
CPU time 218.05 seconds
Started Mar 10 12:37:43 PM PDT 24
Finished Mar 10 12:41:21 PM PDT 24
Peak memory 284356 kb
Host smart-85cb8ba7-edd0-4338-bbbc-3e0058da073a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760970598 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.1760970598
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.4125647790
Short name T43
Test name
Test status
Simulation time 23385907700 ps
CPU time 68 seconds
Started Mar 10 12:37:48 PM PDT 24
Finished Mar 10 12:38:57 PM PDT 24
Peak memory 259748 kb
Host smart-9345cb69-cb67-40a9-83fb-f94c9b233637
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125647790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.4
125647790
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.3110033781
Short name T133
Test name
Test status
Simulation time 25233900 ps
CPU time 13.6 seconds
Started Mar 10 12:37:44 PM PDT 24
Finished Mar 10 12:37:58 PM PDT 24
Peak memory 264760 kb
Host smart-375debea-196f-4228-81d8-eaeea66cf5c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110033781 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.3110033781
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.4176249352
Short name T817
Test name
Test status
Simulation time 3217082500 ps
CPU time 129.83 seconds
Started Mar 10 12:37:41 PM PDT 24
Finished Mar 10 12:39:51 PM PDT 24
Peak memory 264640 kb
Host smart-c77121bb-a82f-4e1e-b001-ce10dea8e79d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176249352 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.4176249352
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.2234549282
Short name T1017
Test name
Test status
Simulation time 36431200 ps
CPU time 130.2 seconds
Started Mar 10 12:37:48 PM PDT 24
Finished Mar 10 12:39:58 PM PDT 24
Peak memory 258984 kb
Host smart-6b28ee75-1ba5-49dd-9330-09bf42cf7fa6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234549282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.2234549282
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.2005692407
Short name T65
Test name
Test status
Simulation time 41899000 ps
CPU time 159.04 seconds
Started Mar 10 12:37:42 PM PDT 24
Finished Mar 10 12:40:21 PM PDT 24
Peak memory 260676 kb
Host smart-8e4113e2-ae95-4de2-80fe-dc5b10967559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005692407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2005692407
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.1397241038
Short name T734
Test name
Test status
Simulation time 29427800 ps
CPU time 13.6 seconds
Started Mar 10 12:37:42 PM PDT 24
Finished Mar 10 12:37:56 PM PDT 24
Peak memory 264852 kb
Host smart-ee9282a3-e7d8-43bf-aa5f-faa81b1dd652
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397241038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.1397241038
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.2180566864
Short name T563
Test name
Test status
Simulation time 164669700 ps
CPU time 856.66 seconds
Started Mar 10 12:37:39 PM PDT 24
Finished Mar 10 12:51:56 PM PDT 24
Peak memory 282204 kb
Host smart-73d99452-9038-4b3c-8f52-89ffc0bc0db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180566864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.2180566864
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.226469231
Short name T95
Test name
Test status
Simulation time 218939700 ps
CPU time 36.8 seconds
Started Mar 10 12:37:49 PM PDT 24
Finished Mar 10 12:38:26 PM PDT 24
Peak memory 273884 kb
Host smart-83e945ac-b95c-4d66-9ff4-eb00d4356940
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226469231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_re_evict.226469231
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.2588870296
Short name T435
Test name
Test status
Simulation time 1990708600 ps
CPU time 106.62 seconds
Started Mar 10 12:37:48 PM PDT 24
Finished Mar 10 12:39:35 PM PDT 24
Peak memory 280160 kb
Host smart-995cd739-88a4-415a-9ca4-8c256dcf7ccd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588870296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_ro.2588870296
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.3793398507
Short name T638
Test name
Test status
Simulation time 14215807300 ps
CPU time 515.4 seconds
Started Mar 10 12:37:48 PM PDT 24
Finished Mar 10 12:46:24 PM PDT 24
Peak memory 313692 kb
Host smart-8261dafe-c46d-45bd-b825-97c1daf96694
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793398507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw.3793398507
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.193957293
Short name T387
Test name
Test status
Simulation time 103193000 ps
CPU time 35.05 seconds
Started Mar 10 12:37:49 PM PDT 24
Finished Mar 10 12:38:24 PM PDT 24
Peak memory 272884 kb
Host smart-2cb3d6d3-2433-4afb-853b-1438e03ce378
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193957293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_rw_evict.193957293
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.4174381958
Short name T895
Test name
Test status
Simulation time 53011400 ps
CPU time 33.57 seconds
Started Mar 10 12:37:48 PM PDT 24
Finished Mar 10 12:38:23 PM PDT 24
Peak memory 273036 kb
Host smart-9d66bc60-f2fe-4fb8-8af5-a2aad6bd92fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174381958 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.4174381958
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.3869453468
Short name T1080
Test name
Test status
Simulation time 3073417900 ps
CPU time 61.96 seconds
Started Mar 10 12:37:54 PM PDT 24
Finished Mar 10 12:38:56 PM PDT 24
Peak memory 258880 kb
Host smart-ae435227-65de-4050-bb34-0723d88f6216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869453468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3869453468
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.671114305
Short name T731
Test name
Test status
Simulation time 52714900 ps
CPU time 167.18 seconds
Started Mar 10 12:37:41 PM PDT 24
Finished Mar 10 12:40:28 PM PDT 24
Peak memory 276116 kb
Host smart-18157c8f-5ca8-4bd7-acc4-4698da585ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671114305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.671114305
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.38480847
Short name T988
Test name
Test status
Simulation time 2630911000 ps
CPU time 173.41 seconds
Started Mar 10 12:37:39 PM PDT 24
Finished Mar 10 12:40:32 PM PDT 24
Peak memory 264596 kb
Host smart-a7e19875-805c-403c-8f3d-f9031874e78f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38480847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.flash_ctrl_wo.38480847
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.326275423
Short name T1100
Test name
Test status
Simulation time 68649000 ps
CPU time 13.83 seconds
Started Mar 10 12:37:53 PM PDT 24
Finished Mar 10 12:38:07 PM PDT 24
Peak memory 263788 kb
Host smart-e12a314b-7e6b-4479-b387-f66990c0845b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326275423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.326275423
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.2005432206
Short name T834
Test name
Test status
Simulation time 22268600 ps
CPU time 16.19 seconds
Started Mar 10 12:37:52 PM PDT 24
Finished Mar 10 12:38:08 PM PDT 24
Peak memory 274324 kb
Host smart-bb33710f-bbc8-4919-8c8c-0dd6ad035435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005432206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.2005432206
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.1255020240
Short name T1102
Test name
Test status
Simulation time 82586100 ps
CPU time 20.26 seconds
Started Mar 10 12:37:58 PM PDT 24
Finished Mar 10 12:38:18 PM PDT 24
Peak memory 264740 kb
Host smart-1f11cc95-20b0-4021-8d0d-0097afc14f28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255020240 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.1255020240
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1086420154
Short name T925
Test name
Test status
Simulation time 10015720800 ps
CPU time 101.69 seconds
Started Mar 10 12:37:53 PM PDT 24
Finished Mar 10 12:39:35 PM PDT 24
Peak memory 341308 kb
Host smart-91140f12-346f-477b-9a93-062467d7e750
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086420154 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1086420154
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.3840841899
Short name T1022
Test name
Test status
Simulation time 15166900 ps
CPU time 13.49 seconds
Started Mar 10 12:37:53 PM PDT 24
Finished Mar 10 12:38:07 PM PDT 24
Peak memory 264828 kb
Host smart-d879d6fa-2acd-4613-a9b8-782e709ff57a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840841899 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.3840841899
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.3579772187
Short name T141
Test name
Test status
Simulation time 90154312700 ps
CPU time 734.76 seconds
Started Mar 10 12:37:52 PM PDT 24
Finished Mar 10 12:50:07 PM PDT 24
Peak memory 262460 kb
Host smart-3c3e791e-205b-424d-9a2b-61535c141974
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579772187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.3579772187
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.3929140801
Short name T615
Test name
Test status
Simulation time 3880939700 ps
CPU time 123.61 seconds
Started Mar 10 12:37:44 PM PDT 24
Finished Mar 10 12:39:48 PM PDT 24
Peak memory 261304 kb
Host smart-824498c6-6dcb-4c4c-8669-429d1481b48d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929140801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.3929140801
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.3414822918
Short name T207
Test name
Test status
Simulation time 5343332700 ps
CPU time 173.7 seconds
Started Mar 10 12:37:49 PM PDT 24
Finished Mar 10 12:40:43 PM PDT 24
Peak memory 292860 kb
Host smart-a4199edf-e5be-41da-a89d-cdf2116a7ef9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414822918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.3414822918
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.2607791642
Short name T438
Test name
Test status
Simulation time 17916521200 ps
CPU time 182.21 seconds
Started Mar 10 12:37:53 PM PDT 24
Finished Mar 10 12:40:56 PM PDT 24
Peak memory 289300 kb
Host smart-510578c7-bef2-4ca2-8bcf-bebaca9439f2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607791642 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.2607791642
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.1954170050
Short name T1013
Test name
Test status
Simulation time 3866680100 ps
CPU time 83.79 seconds
Started Mar 10 12:37:51 PM PDT 24
Finished Mar 10 12:39:15 PM PDT 24
Peak memory 258940 kb
Host smart-fb89673d-82a8-4608-8fba-9af68c91aec3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954170050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.1
954170050
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.4160494368
Short name T134
Test name
Test status
Simulation time 16401800 ps
CPU time 13.65 seconds
Started Mar 10 12:37:53 PM PDT 24
Finished Mar 10 12:38:07 PM PDT 24
Peak memory 264820 kb
Host smart-43362617-8273-4e15-9ade-d8fde1f0708f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160494368 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.4160494368
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.1990064776
Short name T855
Test name
Test status
Simulation time 4709733900 ps
CPU time 87.19 seconds
Started Mar 10 12:37:44 PM PDT 24
Finished Mar 10 12:39:11 PM PDT 24
Peak memory 260580 kb
Host smart-bb485c19-b524-47da-82d6-2bc1fd43c544
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990064776 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.1990064776
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.1080480029
Short name T732
Test name
Test status
Simulation time 146375000 ps
CPU time 136.04 seconds
Started Mar 10 12:37:46 PM PDT 24
Finished Mar 10 12:40:03 PM PDT 24
Peak memory 262588 kb
Host smart-565d84b7-5ce5-41fa-a34e-895b57e41e5d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080480029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.1080480029
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.2094298085
Short name T576
Test name
Test status
Simulation time 178212900 ps
CPU time 456.1 seconds
Started Mar 10 12:37:48 PM PDT 24
Finished Mar 10 12:45:25 PM PDT 24
Peak memory 260724 kb
Host smart-f40398c9-5435-4971-bb87-60bb0f49b56d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2094298085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.2094298085
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.1588980186
Short name T407
Test name
Test status
Simulation time 21609000 ps
CPU time 13.38 seconds
Started Mar 10 12:37:51 PM PDT 24
Finished Mar 10 12:38:05 PM PDT 24
Peak memory 264664 kb
Host smart-ce431497-1897-415b-bb31-3a7f8540bf85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588980186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.1588980186
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.719301937
Short name T1060
Test name
Test status
Simulation time 69704100 ps
CPU time 473.39 seconds
Started Mar 10 12:37:54 PM PDT 24
Finished Mar 10 12:45:47 PM PDT 24
Peak memory 282116 kb
Host smart-678ed8bd-3b10-42d6-91bd-fa91016ce6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719301937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.719301937
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.2537941784
Short name T649
Test name
Test status
Simulation time 189704200 ps
CPU time 37.08 seconds
Started Mar 10 12:37:53 PM PDT 24
Finished Mar 10 12:38:30 PM PDT 24
Peak memory 273156 kb
Host smart-83cdc5e8-5f24-49e9-b45c-e6eb6c663e08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537941784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.2537941784
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.993401914
Short name T1062
Test name
Test status
Simulation time 522847100 ps
CPU time 96.23 seconds
Started Mar 10 12:37:46 PM PDT 24
Finished Mar 10 12:39:23 PM PDT 24
Peak memory 281196 kb
Host smart-0d21daa8-e5fe-41c6-ad49-facbae956eaa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993401914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.flash_ctrl_ro.993401914
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.2186202885
Short name T963
Test name
Test status
Simulation time 44647200 ps
CPU time 31.63 seconds
Started Mar 10 12:37:56 PM PDT 24
Finished Mar 10 12:38:28 PM PDT 24
Peak memory 271920 kb
Host smart-9d0b9cce-e3bc-4e58-9114-efd12c48ab66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186202885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.2186202885
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.3181000907
Short name T751
Test name
Test status
Simulation time 97886200 ps
CPU time 30.97 seconds
Started Mar 10 12:37:49 PM PDT 24
Finished Mar 10 12:38:20 PM PDT 24
Peak memory 273064 kb
Host smart-da22d8c1-957e-4022-afee-9e86049a9ad0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181000907 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.3181000907
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.761403779
Short name T1038
Test name
Test status
Simulation time 2080923900 ps
CPU time 70.42 seconds
Started Mar 10 12:37:53 PM PDT 24
Finished Mar 10 12:39:03 PM PDT 24
Peak memory 258964 kb
Host smart-749ee5c1-9a76-42d0-9ee1-abf0d110dacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761403779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.761403779
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.67490351
Short name T879
Test name
Test status
Simulation time 99382000 ps
CPU time 171.61 seconds
Started Mar 10 12:37:45 PM PDT 24
Finished Mar 10 12:40:37 PM PDT 24
Peak memory 279112 kb
Host smart-d2cc7a13-8f61-4dd9-a798-325f74369e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67490351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.67490351
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.1945240854
Short name T1121
Test name
Test status
Simulation time 5661228800 ps
CPU time 184.94 seconds
Started Mar 10 12:37:43 PM PDT 24
Finished Mar 10 12:40:49 PM PDT 24
Peak memory 264644 kb
Host smart-5d1dec4b-4f0d-441a-a212-780aa89b6229
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945240854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.flash_ctrl_wo.1945240854
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.3923961589
Short name T44
Test name
Test status
Simulation time 49266200 ps
CPU time 13.73 seconds
Started Mar 10 12:35:38 PM PDT 24
Finished Mar 10 12:35:54 PM PDT 24
Peak memory 264824 kb
Host smart-bcb7e2b1-e68e-42bf-9b69-5193ed091100
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923961589 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.3923961589
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.2825361083
Short name T953
Test name
Test status
Simulation time 155242800 ps
CPU time 13.69 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:35:44 PM PDT 24
Peak memory 264384 kb
Host smart-ae03da2a-9a10-415e-8046-037142ad58c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825361083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2
825361083
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.3736445340
Short name T254
Test name
Test status
Simulation time 22387800 ps
CPU time 13.81 seconds
Started Mar 10 12:35:31 PM PDT 24
Finished Mar 10 12:35:45 PM PDT 24
Peak memory 264704 kb
Host smart-ea483ffe-a33b-4dcb-a129-9623818f8cef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736445340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.3736445340
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.1578493129
Short name T810
Test name
Test status
Simulation time 42516000 ps
CPU time 13.45 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:35:40 PM PDT 24
Peak memory 274008 kb
Host smart-911b4cd1-fceb-4cc0-a6ae-552117bcacc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578493129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.1578493129
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.2369957657
Short name T874
Test name
Test status
Simulation time 370806400 ps
CPU time 101.74 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:37:12 PM PDT 24
Peak memory 280548 kb
Host smart-cd79494d-0e00-4366-ac0a-55fdc83a9662
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369957657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.2369957657
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.3380961155
Short name T218
Test name
Test status
Simulation time 11249100 ps
CPU time 20.45 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:35:51 PM PDT 24
Peak memory 272968 kb
Host smart-2657a62f-b246-4316-bafb-09e6750c4abd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380961155 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.3380961155
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.2812488710
Short name T914
Test name
Test status
Simulation time 1396860000 ps
CPU time 356.39 seconds
Started Mar 10 12:35:24 PM PDT 24
Finished Mar 10 12:41:20 PM PDT 24
Peak memory 260712 kb
Host smart-ec394c87-0725-478d-89e6-54d99fb534d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812488710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.2812488710
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.2177495584
Short name T287
Test name
Test status
Simulation time 17412804500 ps
CPU time 2457.06 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 01:16:20 PM PDT 24
Peak memory 263868 kb
Host smart-f4d6753b-1232-4e69-beb4-13be83b644f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177495584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.2177495584
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.4029695911
Short name T163
Test name
Test status
Simulation time 1801233600 ps
CPU time 3034.23 seconds
Started Mar 10 12:35:34 PM PDT 24
Finished Mar 10 01:26:09 PM PDT 24
Peak memory 264612 kb
Host smart-e74d6d0c-a5e0-4918-bea7-3081ce826e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029695911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.4029695911
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.1096985432
Short name T821
Test name
Test status
Simulation time 684676600 ps
CPU time 905.26 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:50:35 PM PDT 24
Peak memory 273364 kb
Host smart-12ec30bc-185e-4d4a-a390-41996f863b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096985432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1096985432
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.365469868
Short name T55
Test name
Test status
Simulation time 972591000 ps
CPU time 22.55 seconds
Started Mar 10 12:35:23 PM PDT 24
Finished Mar 10 12:35:46 PM PDT 24
Peak memory 264656 kb
Host smart-84ffe250-b5cf-4cb3-8b18-915e78fc1502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365469868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.365469868
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.727555105
Short name T730
Test name
Test status
Simulation time 320981800 ps
CPU time 34.2 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:36:04 PM PDT 24
Peak memory 264812 kb
Host smart-935306c1-561f-4a04-86c9-dc5e083444f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727555105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_fs_sup.727555105
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.3749169278
Short name T84
Test name
Test status
Simulation time 193762401800 ps
CPU time 2649.39 seconds
Started Mar 10 12:35:20 PM PDT 24
Finished Mar 10 01:19:30 PM PDT 24
Peak memory 259796 kb
Host smart-79a5f6d0-a6e9-4a02-b9cd-d93165a5def2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749169278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.3749169278
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.3278399783
Short name T944
Test name
Test status
Simulation time 58499600 ps
CPU time 70.17 seconds
Started Mar 10 12:35:17 PM PDT 24
Finished Mar 10 12:36:29 PM PDT 24
Peak memory 264688 kb
Host smart-144d07fc-d680-49b6-98b8-34243ac071fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3278399783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3278399783
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3945795556
Short name T867
Test name
Test status
Simulation time 10034111900 ps
CPU time 50.13 seconds
Started Mar 10 12:35:39 PM PDT 24
Finished Mar 10 12:36:30 PM PDT 24
Peak memory 267488 kb
Host smart-93ae4199-72d7-4368-8ab4-ec47c310c7d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945795556 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3945795556
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.3719999700
Short name T280
Test name
Test status
Simulation time 46425500 ps
CPU time 13.57 seconds
Started Mar 10 12:35:25 PM PDT 24
Finished Mar 10 12:35:39 PM PDT 24
Peak memory 264752 kb
Host smart-357057d5-7f31-45a8-a3fd-f9223acab93b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719999700 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.3719999700
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.3543998700
Short name T829
Test name
Test status
Simulation time 117771445100 ps
CPU time 1903.94 seconds
Started Mar 10 12:35:20 PM PDT 24
Finished Mar 10 01:07:05 PM PDT 24
Peak memory 258428 kb
Host smart-51b21ab9-aa6b-4138-a9b1-bf30420e2a80
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543998700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.3543998700
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.3282664112
Short name T70
Test name
Test status
Simulation time 40122335900 ps
CPU time 685.37 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:46:53 PM PDT 24
Peak memory 262680 kb
Host smart-1b7876f5-84ba-4901-8437-7eb93dd3209a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282664112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.3282664112
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2032668260
Short name T546
Test name
Test status
Simulation time 30275187400 ps
CPU time 276.17 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:39:58 PM PDT 24
Peak memory 261728 kb
Host smart-77d88d1b-9180-4448-9658-5483d7cc9e88
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032668260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.2032668260
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.117688813
Short name T249
Test name
Test status
Simulation time 15167594300 ps
CPU time 477.09 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:43:27 PM PDT 24
Peak memory 317172 kb
Host smart-1b01a943-aeaa-466b-9add-26be1465c13a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117688813 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.flash_ctrl_integrity.117688813
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.1494817455
Short name T554
Test name
Test status
Simulation time 5125869300 ps
CPU time 153.97 seconds
Started Mar 10 12:35:32 PM PDT 24
Finished Mar 10 12:38:06 PM PDT 24
Peak memory 290420 kb
Host smart-cad8b0fc-9c53-4dcc-a505-f68039c30f80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494817455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.1494817455
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3846993258
Short name T665
Test name
Test status
Simulation time 30264693000 ps
CPU time 206.25 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:38:56 PM PDT 24
Peak memory 289296 kb
Host smart-411112b3-31d0-4b40-a294-8bc8df3f5407
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846993258 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.3846993258
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.1879377623
Short name T708
Test name
Test status
Simulation time 4338830300 ps
CPU time 87.66 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:36:55 PM PDT 24
Peak memory 264740 kb
Host smart-277bd94a-2fed-4d9f-bc5a-ebaa7fdbad8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879377623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.1879377623
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.288269573
Short name T492
Test name
Test status
Simulation time 59006898500 ps
CPU time 345.62 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:41:13 PM PDT 24
Peak memory 264692 kb
Host smart-9b03b8d7-823b-40f4-abf3-536175da7493
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288
269573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.288269573
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.746852824
Short name T440
Test name
Test status
Simulation time 3294097100 ps
CPU time 65.48 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:36:35 PM PDT 24
Peak memory 259072 kb
Host smart-55b1c50d-628c-4387-a656-91f672e84623
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746852824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.746852824
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1576168192
Short name T1002
Test name
Test status
Simulation time 222246700 ps
CPU time 13.44 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:35:44 PM PDT 24
Peak memory 264812 kb
Host smart-186d45c6-6e3f-408b-b89d-113c44e62487
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576168192 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.1576168192
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.4172204767
Short name T100
Test name
Test status
Simulation time 20587430100 ps
CPU time 821.91 seconds
Started Mar 10 12:35:23 PM PDT 24
Finished Mar 10 12:49:05 PM PDT 24
Peak memory 273368 kb
Host smart-bed1980d-680d-4acb-9192-e42dae932b35
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172204767 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.4172204767
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.502500410
Short name T459
Test name
Test status
Simulation time 75633900 ps
CPU time 131.8 seconds
Started Mar 10 12:35:20 PM PDT 24
Finished Mar 10 12:37:32 PM PDT 24
Peak memory 259836 kb
Host smart-44955781-5238-46e7-961e-43a3a0c79a1f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502500410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp
_reset.502500410
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.4261800270
Short name T816
Test name
Test status
Simulation time 1737844800 ps
CPU time 139.11 seconds
Started Mar 10 12:35:20 PM PDT 24
Finished Mar 10 12:37:40 PM PDT 24
Peak memory 293636 kb
Host smart-f3188848-e248-45d0-97fc-5657594d7c55
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261800270 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.4261800270
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.3866118989
Short name T227
Test name
Test status
Simulation time 19741178400 ps
CPU time 546.77 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:44:35 PM PDT 24
Peak memory 264640 kb
Host smart-6b5d11d9-0369-4c42-8a9e-db623cc232eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866118989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3866118989
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.3625631304
Short name T128
Test name
Test status
Simulation time 725100700 ps
CPU time 24.75 seconds
Started Mar 10 12:35:26 PM PDT 24
Finished Mar 10 12:35:51 PM PDT 24
Peak memory 264852 kb
Host smart-23266ebc-2ada-44b4-8fa0-2416ff088135
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625631304 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.3625631304
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.3337732142
Short name T1122
Test name
Test status
Simulation time 31886300 ps
CPU time 13.45 seconds
Started Mar 10 12:35:32 PM PDT 24
Finished Mar 10 12:35:46 PM PDT 24
Peak memory 264700 kb
Host smart-3e5f8fae-c4a0-4838-bcfa-da14499bb0ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337732142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.3337732142
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.2339987175
Short name T98
Test name
Test status
Simulation time 73948800 ps
CPU time 149.22 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:37:58 PM PDT 24
Peak memory 268028 kb
Host smart-bc3f84bc-6bae-4c23-8ece-6c54f6d014eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339987175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2339987175
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.1694582539
Short name T782
Test name
Test status
Simulation time 2279619500 ps
CPU time 127.17 seconds
Started Mar 10 12:35:21 PM PDT 24
Finished Mar 10 12:37:29 PM PDT 24
Peak memory 264096 kb
Host smart-3b8bb148-d7fc-4bc3-9ce6-eec8914503d3
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1694582539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1694582539
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1735105528
Short name T761
Test name
Test status
Simulation time 18788200 ps
CPU time 20.91 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:35:44 PM PDT 24
Peak memory 264824 kb
Host smart-8574ca27-8348-4263-80fc-f89d477ad6f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735105528 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.1735105528
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.1974634929
Short name T402
Test name
Test status
Simulation time 24619500 ps
CPU time 22.45 seconds
Started Mar 10 12:35:24 PM PDT 24
Finished Mar 10 12:35:47 PM PDT 24
Peak memory 264788 kb
Host smart-7b22ee15-51b1-4b72-8426-4b8e3abb3981
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974634929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.1974634929
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.3546198718
Short name T612
Test name
Test status
Simulation time 387740200 ps
CPU time 85.53 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:36:54 PM PDT 24
Peak memory 280360 kb
Host smart-ea56fc8a-c792-413c-81c1-9feff2e5b885
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546198718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_ro.3546198718
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.503940665
Short name T251
Test name
Test status
Simulation time 667016600 ps
CPU time 141.33 seconds
Started Mar 10 12:35:20 PM PDT 24
Finished Mar 10 12:37:42 PM PDT 24
Peak memory 281144 kb
Host smart-3606990d-ba6f-455e-bb43-d020a75b5df0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
503940665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.503940665
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.1168276508
Short name T605
Test name
Test status
Simulation time 14494548100 ps
CPU time 531.52 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:44:14 PM PDT 24
Peak memory 313156 kb
Host smart-34497bdb-ab08-4ae8-ae1b-330ba16b3a52
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168276508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_rw.1168276508
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.1328318988
Short name T248
Test name
Test status
Simulation time 6771886200 ps
CPU time 586.67 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:45:14 PM PDT 24
Peak memory 320604 kb
Host smart-822ec694-2c29-4cd5-92de-fc1a554682b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328318988 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.1328318988
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.2926150879
Short name T201
Test name
Test status
Simulation time 93988200 ps
CPU time 32.76 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:36:01 PM PDT 24
Peak memory 277272 kb
Host smart-32ec9e90-62cc-48ae-9590-9d0555fd4981
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926150879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.2926150879
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2994018016
Short name T906
Test name
Test status
Simulation time 39705500 ps
CPU time 30.71 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:35:58 PM PDT 24
Peak memory 274172 kb
Host smart-dd03b672-eba0-4272-900f-8d2c9b57c492
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994018016 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2994018016
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.29201217
Short name T476
Test name
Test status
Simulation time 60745731000 ps
CPU time 592.59 seconds
Started Mar 10 12:35:36 PM PDT 24
Finished Mar 10 12:45:29 PM PDT 24
Peak memory 311276 kb
Host smart-75be2d14-a912-415f-a97d-7b5a80fea63e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29201217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash
_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_ser
r.29201217
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.149815387
Short name T370
Test name
Test status
Simulation time 1812614000 ps
CPU time 64.67 seconds
Started Mar 10 12:35:18 PM PDT 24
Finished Mar 10 12:36:23 PM PDT 24
Peak memory 263548 kb
Host smart-e70115df-ae7a-46b4-a260-c40f406afc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149815387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.149815387
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.3023054666
Short name T898
Test name
Test status
Simulation time 2873105100 ps
CPU time 70.32 seconds
Started Mar 10 12:35:31 PM PDT 24
Finished Mar 10 12:36:42 PM PDT 24
Peak memory 264888 kb
Host smart-3427787a-b086-4316-bc99-7b13d7d05206
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023054666 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.3023054666
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.3487244327
Short name T589
Test name
Test status
Simulation time 1118536800 ps
CPU time 59.29 seconds
Started Mar 10 12:35:23 PM PDT 24
Finished Mar 10 12:36:23 PM PDT 24
Peak memory 264816 kb
Host smart-876a2136-9d05-492c-975d-1824867bbad9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487244327 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.3487244327
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.3739386389
Short name T876
Test name
Test status
Simulation time 19075900 ps
CPU time 74.81 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:36:43 PM PDT 24
Peak memory 274088 kb
Host smart-5212eb83-af55-46c0-a25c-6455a0040097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739386389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3739386389
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.938561645
Short name T414
Test name
Test status
Simulation time 28347200 ps
CPU time 26.36 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:35:56 PM PDT 24
Peak memory 258436 kb
Host smart-a0b21a00-56ea-4574-8eb5-30b54c6bdd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938561645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.938561645
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.2518732239
Short name T824
Test name
Test status
Simulation time 230373400 ps
CPU time 212.9 seconds
Started Mar 10 12:35:26 PM PDT 24
Finished Mar 10 12:38:59 PM PDT 24
Peak memory 279336 kb
Host smart-fc1d2536-080f-4bd5-806f-28c021e861a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518732239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.2518732239
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.866548606
Short name T778
Test name
Test status
Simulation time 99209700 ps
CPU time 26.22 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:35:55 PM PDT 24
Peak memory 258760 kb
Host smart-6acf8ef2-d9f9-45f6-b78c-37d93210e0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866548606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.866548606
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.2690228508
Short name T877
Test name
Test status
Simulation time 3779384900 ps
CPU time 155.87 seconds
Started Mar 10 12:35:20 PM PDT 24
Finished Mar 10 12:37:57 PM PDT 24
Peak memory 264756 kb
Host smart-520e59c9-3fa6-40d7-a96b-a07ca761ff8b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690228508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_wo.2690228508
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.2690685954
Short name T456
Test name
Test status
Simulation time 56616900 ps
CPU time 13.64 seconds
Started Mar 10 12:37:57 PM PDT 24
Finished Mar 10 12:38:11 PM PDT 24
Peak memory 263688 kb
Host smart-d6e70f62-658a-4d6f-9c8e-7a3bc948e23e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690685954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
2690685954
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.1677801183
Short name T630
Test name
Test status
Simulation time 47896100 ps
CPU time 13.29 seconds
Started Mar 10 12:37:57 PM PDT 24
Finished Mar 10 12:38:11 PM PDT 24
Peak memory 273948 kb
Host smart-067c7755-cdab-4b05-8dd5-8b6b47d8981c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677801183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.1677801183
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.625263657
Short name T1078
Test name
Test status
Simulation time 21039300 ps
CPU time 22.25 seconds
Started Mar 10 12:37:54 PM PDT 24
Finished Mar 10 12:38:17 PM PDT 24
Peak memory 279520 kb
Host smart-887dbbb9-3e83-4567-9034-5c64432610c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625263657 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.625263657
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.1543481180
Short name T564
Test name
Test status
Simulation time 13797324200 ps
CPU time 47.16 seconds
Started Mar 10 12:37:49 PM PDT 24
Finished Mar 10 12:38:36 PM PDT 24
Peak memory 258496 kb
Host smart-c89bfd9c-592d-421c-b335-b939da418f79
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543481180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.1543481180
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.1979972307
Short name T1096
Test name
Test status
Simulation time 2254093400 ps
CPU time 153.13 seconds
Started Mar 10 12:37:59 PM PDT 24
Finished Mar 10 12:40:33 PM PDT 24
Peak memory 289372 kb
Host smart-60867bae-29ef-4ed5-8eee-08772fbb8488
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979972307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.1979972307
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3286106574
Short name T1052
Test name
Test status
Simulation time 9092760300 ps
CPU time 288.91 seconds
Started Mar 10 12:37:59 PM PDT 24
Finished Mar 10 12:42:48 PM PDT 24
Peak memory 290472 kb
Host smart-b9bc66f2-1794-4842-a844-b4e4a7335f6d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286106574 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.3286106574
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.3748844887
Short name T146
Test name
Test status
Simulation time 158873000 ps
CPU time 131.25 seconds
Started Mar 10 12:37:51 PM PDT 24
Finished Mar 10 12:40:02 PM PDT 24
Peak memory 259172 kb
Host smart-2d64a15e-cc19-47c8-a4a4-dd25a9ba1e83
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748844887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.3748844887
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.775448969
Short name T918
Test name
Test status
Simulation time 18252600 ps
CPU time 13.32 seconds
Started Mar 10 12:37:53 PM PDT 24
Finished Mar 10 12:38:06 PM PDT 24
Peak memory 263916 kb
Host smart-23cad92d-9829-4ef2-9f93-162e82142bdb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775448969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_res
et.775448969
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.404000871
Short name T919
Test name
Test status
Simulation time 101708700 ps
CPU time 31.32 seconds
Started Mar 10 12:37:58 PM PDT 24
Finished Mar 10 12:38:30 PM PDT 24
Peak memory 273020 kb
Host smart-9f68bc1e-7940-4c21-a267-b58b3c1d2cdd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404000871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_rw_evict.404000871
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.211420644
Short name T755
Test name
Test status
Simulation time 29062500 ps
CPU time 28.68 seconds
Started Mar 10 12:37:57 PM PDT 24
Finished Mar 10 12:38:26 PM PDT 24
Peak memory 273152 kb
Host smart-a9927814-0ad5-4d75-9906-f5347da76538
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211420644 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.211420644
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.2710427409
Short name T624
Test name
Test status
Simulation time 3528302800 ps
CPU time 65.49 seconds
Started Mar 10 12:37:58 PM PDT 24
Finished Mar 10 12:39:04 PM PDT 24
Peak memory 262300 kb
Host smart-fd39f8d7-194c-4ce8-a6f6-80b8e7fde49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710427409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.2710427409
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.1964981608
Short name T748
Test name
Test status
Simulation time 399360100 ps
CPU time 119.15 seconds
Started Mar 10 12:37:48 PM PDT 24
Finished Mar 10 12:39:48 PM PDT 24
Peak memory 274900 kb
Host smart-7a01a8fc-395e-4e69-86bb-0a5699486bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964981608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.1964981608
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.980636905
Short name T893
Test name
Test status
Simulation time 188400000 ps
CPU time 14.92 seconds
Started Mar 10 12:38:00 PM PDT 24
Finished Mar 10 12:38:18 PM PDT 24
Peak memory 264764 kb
Host smart-40d95837-4c82-43a2-89cd-6304acd999df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980636905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.980636905
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.3427676774
Short name T633
Test name
Test status
Simulation time 47801800 ps
CPU time 15.9 seconds
Started Mar 10 12:38:01 PM PDT 24
Finished Mar 10 12:38:19 PM PDT 24
Peak memory 273980 kb
Host smart-75119f2a-acf8-41a1-88c7-5821dd093221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427676774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.3427676774
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.3569521438
Short name T1101
Test name
Test status
Simulation time 11018100 ps
CPU time 22.14 seconds
Started Mar 10 12:37:58 PM PDT 24
Finished Mar 10 12:38:20 PM PDT 24
Peak memory 280008 kb
Host smart-e8ec1a10-d40f-4a36-a76c-e9e1c301be65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569521438 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.3569521438
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2353774683
Short name T306
Test name
Test status
Simulation time 22265766100 ps
CPU time 71.67 seconds
Started Mar 10 12:37:54 PM PDT 24
Finished Mar 10 12:39:06 PM PDT 24
Peak memory 258588 kb
Host smart-644e32be-64ee-4246-a29e-4b6f7b811114
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353774683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.2353774683
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.1514178044
Short name T738
Test name
Test status
Simulation time 2116916700 ps
CPU time 142.2 seconds
Started Mar 10 12:37:54 PM PDT 24
Finished Mar 10 12:40:16 PM PDT 24
Peak memory 291848 kb
Host smart-64f22bc7-37d9-4d7c-81e9-b993671c8365
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514178044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.1514178044
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1200555027
Short name T531
Test name
Test status
Simulation time 8277385900 ps
CPU time 208.93 seconds
Started Mar 10 12:37:55 PM PDT 24
Finished Mar 10 12:41:24 PM PDT 24
Peak memory 292376 kb
Host smart-bb8f7e22-7978-497e-9127-c9fd433d9782
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200555027 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.1200555027
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.3406850568
Short name T808
Test name
Test status
Simulation time 80620300 ps
CPU time 108.76 seconds
Started Mar 10 12:37:56 PM PDT 24
Finished Mar 10 12:39:45 PM PDT 24
Peak memory 260148 kb
Host smart-799adcb4-4624-42c4-b4c3-c83b19d81aa5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406850568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.3406850568
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.946321213
Short name T881
Test name
Test status
Simulation time 56637500 ps
CPU time 13.43 seconds
Started Mar 10 12:37:55 PM PDT 24
Finished Mar 10 12:38:09 PM PDT 24
Peak memory 264724 kb
Host smart-639ae159-a401-4d42-902c-75bebbef20ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946321213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_res
et.946321213
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.2828873845
Short name T646
Test name
Test status
Simulation time 29546800 ps
CPU time 30.79 seconds
Started Mar 10 12:37:58 PM PDT 24
Finished Mar 10 12:38:28 PM PDT 24
Peak memory 273140 kb
Host smart-75185aef-4246-48cb-922d-8d30d0f66f5f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828873845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.2828873845
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.649724480
Short name T661
Test name
Test status
Simulation time 28209600 ps
CPU time 28.17 seconds
Started Mar 10 12:38:01 PM PDT 24
Finished Mar 10 12:38:31 PM PDT 24
Peak memory 273104 kb
Host smart-a4dec95b-9b51-4049-ab3c-c3c7a2eaad8a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649724480 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.649724480
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.4077810075
Short name T497
Test name
Test status
Simulation time 911765900 ps
CPU time 52.24 seconds
Started Mar 10 12:38:02 PM PDT 24
Finished Mar 10 12:38:55 PM PDT 24
Peak memory 261988 kb
Host smart-3d0fd23b-40af-48b9-a458-78e96d590ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077810075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.4077810075
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.2020594662
Short name T1033
Test name
Test status
Simulation time 248198600 ps
CPU time 97.76 seconds
Started Mar 10 12:37:53 PM PDT 24
Finished Mar 10 12:39:32 PM PDT 24
Peak memory 274584 kb
Host smart-61b2d3be-495a-46d3-b2ae-654eeb2228ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020594662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2020594662
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.82451143
Short name T875
Test name
Test status
Simulation time 88757900 ps
CPU time 13.51 seconds
Started Mar 10 12:38:06 PM PDT 24
Finished Mar 10 12:38:20 PM PDT 24
Peak memory 264372 kb
Host smart-f703c007-1b40-476a-a0d7-0f7e09703746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82451143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.82451143
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.3859493493
Short name T994
Test name
Test status
Simulation time 41999600 ps
CPU time 16.03 seconds
Started Mar 10 12:38:05 PM PDT 24
Finished Mar 10 12:38:21 PM PDT 24
Peak memory 273928 kb
Host smart-c4890813-a8fe-4515-bea5-4b3c97ae9d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859493493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3859493493
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.890592923
Short name T967
Test name
Test status
Simulation time 15516900 ps
CPU time 22.19 seconds
Started Mar 10 12:38:04 PM PDT 24
Finished Mar 10 12:38:27 PM PDT 24
Peak memory 273016 kb
Host smart-0feb2753-8403-4baa-a91e-684a89666c54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890592923 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.890592923
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.1565185633
Short name T888
Test name
Test status
Simulation time 7361863700 ps
CPU time 82.79 seconds
Started Mar 10 12:38:07 PM PDT 24
Finished Mar 10 12:39:30 PM PDT 24
Peak memory 258408 kb
Host smart-512ae3a0-56cd-4f53-b22d-b175ee581aa3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565185633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.1565185633
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.1715124534
Short name T613
Test name
Test status
Simulation time 1750545900 ps
CPU time 135.33 seconds
Started Mar 10 12:38:00 PM PDT 24
Finished Mar 10 12:40:15 PM PDT 24
Peak memory 293504 kb
Host smart-89e8cb9f-3e5f-46a6-ac53-9dec0b4de5f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715124534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.1715124534
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.4206256657
Short name T535
Test name
Test status
Simulation time 15586624200 ps
CPU time 164.04 seconds
Started Mar 10 12:38:02 PM PDT 24
Finished Mar 10 12:40:47 PM PDT 24
Peak memory 289348 kb
Host smart-6540e450-7a86-4b78-b8a1-9149e2d2f822
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206256657 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.4206256657
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.2034349920
Short name T933
Test name
Test status
Simulation time 145286600 ps
CPU time 109.7 seconds
Started Mar 10 12:38:01 PM PDT 24
Finished Mar 10 12:39:53 PM PDT 24
Peak memory 258972 kb
Host smart-0dd68995-e813-4b78-8e66-1c49cb286cfc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034349920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.2034349920
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.2059838182
Short name T509
Test name
Test status
Simulation time 29284900 ps
CPU time 13.52 seconds
Started Mar 10 12:38:01 PM PDT 24
Finished Mar 10 12:38:16 PM PDT 24
Peak memory 263992 kb
Host smart-7252a401-6468-4564-b38b-b35fac67e862
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059838182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.2059838182
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.1176199114
Short name T995
Test name
Test status
Simulation time 174032600 ps
CPU time 32.53 seconds
Started Mar 10 12:38:01 PM PDT 24
Finished Mar 10 12:38:35 PM PDT 24
Peak memory 273040 kb
Host smart-afffc86c-1268-4550-b382-f67191224f54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176199114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.1176199114
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.382353768
Short name T1030
Test name
Test status
Simulation time 41531800 ps
CPU time 30.11 seconds
Started Mar 10 12:37:59 PM PDT 24
Finished Mar 10 12:38:29 PM PDT 24
Peak memory 274180 kb
Host smart-58e5a394-4349-4bcb-8e9d-abadce0d3b35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382353768 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.382353768
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.860053558
Short name T571
Test name
Test status
Simulation time 4564581500 ps
CPU time 80.22 seconds
Started Mar 10 12:38:07 PM PDT 24
Finished Mar 10 12:39:28 PM PDT 24
Peak memory 263504 kb
Host smart-9dd6c4e2-39f1-4264-8d47-d2bbc53faf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860053558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.860053558
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.267704658
Short name T728
Test name
Test status
Simulation time 41787400 ps
CPU time 75.82 seconds
Started Mar 10 12:38:01 PM PDT 24
Finished Mar 10 12:39:19 PM PDT 24
Peak memory 274072 kb
Host smart-62cf6308-9864-4abf-a712-10b3ede8479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267704658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.267704658
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.2477704680
Short name T672
Test name
Test status
Simulation time 33617700 ps
CPU time 13.6 seconds
Started Mar 10 12:38:07 PM PDT 24
Finished Mar 10 12:38:20 PM PDT 24
Peak memory 264284 kb
Host smart-5e4ff4d6-233f-47ec-98ca-3fa0c14f3b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477704680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
2477704680
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.2248270919
Short name T616
Test name
Test status
Simulation time 25679100 ps
CPU time 13.37 seconds
Started Mar 10 12:38:08 PM PDT 24
Finished Mar 10 12:38:21 PM PDT 24
Peak memory 283172 kb
Host smart-8d3b4f2a-6196-452f-9435-54d645dc5a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248270919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2248270919
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.658226104
Short name T157
Test name
Test status
Simulation time 104886000 ps
CPU time 21.48 seconds
Started Mar 10 12:38:04 PM PDT 24
Finished Mar 10 12:38:26 PM PDT 24
Peak memory 264720 kb
Host smart-29fcde61-0d8e-40ea-8533-8777d6db9c98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658226104 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.658226104
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.2713510063
Short name T632
Test name
Test status
Simulation time 7627816700 ps
CPU time 80.79 seconds
Started Mar 10 12:38:09 PM PDT 24
Finished Mar 10 12:39:30 PM PDT 24
Peak memory 261264 kb
Host smart-57e57aeb-f9a0-4c53-9726-14ca94d5bbc7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713510063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.2713510063
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.734529671
Short name T968
Test name
Test status
Simulation time 2359985300 ps
CPU time 170.13 seconds
Started Mar 10 12:38:09 PM PDT 24
Finished Mar 10 12:41:00 PM PDT 24
Peak memory 289304 kb
Host smart-2815a9bc-ac7a-4477-a8a3-16623c529bf3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734529671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flas
h_ctrl_intr_rd.734529671
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2337738598
Short name T426
Test name
Test status
Simulation time 28644458400 ps
CPU time 213.77 seconds
Started Mar 10 12:38:09 PM PDT 24
Finished Mar 10 12:41:43 PM PDT 24
Peak memory 283780 kb
Host smart-7aedf038-909b-4287-a566-cc516d5dea29
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337738598 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2337738598
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.2324150950
Short name T962
Test name
Test status
Simulation time 39702500 ps
CPU time 114.8 seconds
Started Mar 10 12:38:06 PM PDT 24
Finished Mar 10 12:40:01 PM PDT 24
Peak memory 263352 kb
Host smart-aec2e6d1-6b12-45ce-8687-6ea03372bf82
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324150950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.2324150950
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.3760020052
Short name T505
Test name
Test status
Simulation time 34313500 ps
CPU time 13.69 seconds
Started Mar 10 12:38:07 PM PDT 24
Finished Mar 10 12:38:21 PM PDT 24
Peak memory 264768 kb
Host smart-70cb62a8-d325-401a-9f17-2913b2b4e49e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760020052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.3760020052
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.1535975351
Short name T729
Test name
Test status
Simulation time 163878600 ps
CPU time 33.04 seconds
Started Mar 10 12:38:09 PM PDT 24
Finished Mar 10 12:38:42 PM PDT 24
Peak memory 271968 kb
Host smart-933d20cb-e03b-4ef1-9fde-197a880f55e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535975351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.1535975351
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.3950849284
Short name T432
Test name
Test status
Simulation time 34686100 ps
CPU time 30.93 seconds
Started Mar 10 12:38:05 PM PDT 24
Finished Mar 10 12:38:36 PM PDT 24
Peak memory 264940 kb
Host smart-c82d9c23-4cb6-4458-95f5-8f217f7a8194
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950849284 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.3950849284
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.1260318534
Short name T869
Test name
Test status
Simulation time 3818484500 ps
CPU time 56.12 seconds
Started Mar 10 12:38:06 PM PDT 24
Finished Mar 10 12:39:03 PM PDT 24
Peak memory 262368 kb
Host smart-7a6527a9-9a35-4f63-8a19-ae524f166f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260318534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1260318534
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.3528546600
Short name T643
Test name
Test status
Simulation time 67773600 ps
CPU time 120.21 seconds
Started Mar 10 12:38:07 PM PDT 24
Finished Mar 10 12:40:07 PM PDT 24
Peak memory 277152 kb
Host smart-3b8de6aa-152a-4684-b137-2f94df20deaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528546600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3528546600
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.2031024208
Short name T444
Test name
Test status
Simulation time 116486100 ps
CPU time 13.82 seconds
Started Mar 10 12:38:11 PM PDT 24
Finished Mar 10 12:38:25 PM PDT 24
Peak memory 263744 kb
Host smart-27808ef9-06dc-4eb3-bfcf-b02dd2ba8751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031024208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
2031024208
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.2233087487
Short name T753
Test name
Test status
Simulation time 32885300 ps
CPU time 15.71 seconds
Started Mar 10 12:38:13 PM PDT 24
Finished Mar 10 12:38:29 PM PDT 24
Peak memory 273772 kb
Host smart-8f31c6c4-6519-4f8c-97c6-5b13b5cd4207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233087487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2233087487
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.2208934019
Short name T815
Test name
Test status
Simulation time 26671600 ps
CPU time 20.27 seconds
Started Mar 10 12:38:11 PM PDT 24
Finished Mar 10 12:38:31 PM PDT 24
Peak memory 273044 kb
Host smart-acd72f56-0f74-4f8e-bd52-29eee56a14e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208934019 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.2208934019
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.771067699
Short name T315
Test name
Test status
Simulation time 13361993600 ps
CPU time 228.42 seconds
Started Mar 10 12:38:05 PM PDT 24
Finished Mar 10 12:41:54 PM PDT 24
Peak memory 261804 kb
Host smart-cb3f2b17-7a33-49eb-af2b-31a5788645e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771067699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_h
w_sec_otp.771067699
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.2291753058
Short name T329
Test name
Test status
Simulation time 5161144400 ps
CPU time 158.45 seconds
Started Mar 10 12:38:11 PM PDT 24
Finished Mar 10 12:40:49 PM PDT 24
Peak memory 289404 kb
Host smart-ae703e5c-dbae-4bd8-b4b6-17ae7b6670f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291753058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.2291753058
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2858438185
Short name T34
Test name
Test status
Simulation time 18309188600 ps
CPU time 270.11 seconds
Started Mar 10 12:38:10 PM PDT 24
Finished Mar 10 12:42:41 PM PDT 24
Peak memory 292132 kb
Host smart-dee57f32-9d24-43a1-8c6e-23b1d003e43b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858438185 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.2858438185
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.938371586
Short name T482
Test name
Test status
Simulation time 41324000 ps
CPU time 130.79 seconds
Started Mar 10 12:38:09 PM PDT 24
Finished Mar 10 12:40:20 PM PDT 24
Peak memory 259184 kb
Host smart-0d21788a-2035-4fde-a3bc-fd6161964fb5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938371586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ot
p_reset.938371586
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.3292517473
Short name T4
Test name
Test status
Simulation time 45336400 ps
CPU time 14.05 seconds
Started Mar 10 12:38:10 PM PDT 24
Finished Mar 10 12:38:24 PM PDT 24
Peak memory 264652 kb
Host smart-414b43dd-a04d-48e1-9d03-29175cee6ccc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292517473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.3292517473
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.2730999579
Short name T1057
Test name
Test status
Simulation time 31104000 ps
CPU time 31.05 seconds
Started Mar 10 12:38:13 PM PDT 24
Finished Mar 10 12:38:44 PM PDT 24
Peak memory 274096 kb
Host smart-dcae40f7-dcc6-4ecb-bf51-9ba49c3f16e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730999579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.2730999579
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.2984169577
Short name T652
Test name
Test status
Simulation time 353152600 ps
CPU time 32.05 seconds
Started Mar 10 12:38:11 PM PDT 24
Finished Mar 10 12:38:44 PM PDT 24
Peak memory 273164 kb
Host smart-14dc2d22-dfd4-436d-b5eb-97c384b9af7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984169577 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.2984169577
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.1073336292
Short name T1015
Test name
Test status
Simulation time 33916005800 ps
CPU time 75.05 seconds
Started Mar 10 12:38:10 PM PDT 24
Finished Mar 10 12:39:26 PM PDT 24
Peak memory 263420 kb
Host smart-272cc3d5-c579-4bb2-b1a5-cd055de350ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073336292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.1073336292
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.979708954
Short name T838
Test name
Test status
Simulation time 21379200 ps
CPU time 74.51 seconds
Started Mar 10 12:38:06 PM PDT 24
Finished Mar 10 12:39:21 PM PDT 24
Peak memory 275232 kb
Host smart-288e81a8-5584-4429-b478-19e942c5b618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979708954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.979708954
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.3701813005
Short name T470
Test name
Test status
Simulation time 50444600 ps
CPU time 13.83 seconds
Started Mar 10 12:38:14 PM PDT 24
Finished Mar 10 12:38:27 PM PDT 24
Peak memory 264364 kb
Host smart-2d1c2a8c-08e2-469b-aa21-8bf0b9599caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701813005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
3701813005
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.1691083610
Short name T1056
Test name
Test status
Simulation time 28180800 ps
CPU time 15.37 seconds
Started Mar 10 12:38:21 PM PDT 24
Finished Mar 10 12:38:37 PM PDT 24
Peak memory 274260 kb
Host smart-9e4e0abb-1e2d-4aca-ac44-c49afae67b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691083610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1691083610
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.2541446043
Short name T347
Test name
Test status
Simulation time 10921700 ps
CPU time 21.74 seconds
Started Mar 10 12:38:17 PM PDT 24
Finished Mar 10 12:38:39 PM PDT 24
Peak memory 273004 kb
Host smart-08484f1e-2609-46a0-9270-f14082579dda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541446043 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.2541446043
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.1145465812
Short name T412
Test name
Test status
Simulation time 9787695800 ps
CPU time 162.26 seconds
Started Mar 10 12:38:11 PM PDT 24
Finished Mar 10 12:40:54 PM PDT 24
Peak memory 258400 kb
Host smart-506bfa93-6971-4c45-bdad-36a6dc31841a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145465812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.1145465812
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.1159754092
Short name T330
Test name
Test status
Simulation time 2453320300 ps
CPU time 141.25 seconds
Started Mar 10 12:38:09 PM PDT 24
Finished Mar 10 12:40:31 PM PDT 24
Peak memory 291956 kb
Host smart-39779a5c-fa62-4430-8cc3-55e468676a5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159754092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_intr_rd.1159754092
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.875296208
Short name T549
Test name
Test status
Simulation time 9014437500 ps
CPU time 196.64 seconds
Started Mar 10 12:38:11 PM PDT 24
Finished Mar 10 12:41:28 PM PDT 24
Peak memory 289372 kb
Host smart-cdfcf625-3328-44e3-820e-3ff25ec18f13
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875296208 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.875296208
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.1630345576
Short name T897
Test name
Test status
Simulation time 35418600 ps
CPU time 130.92 seconds
Started Mar 10 12:38:13 PM PDT 24
Finished Mar 10 12:40:24 PM PDT 24
Peak memory 263804 kb
Host smart-945538c3-46e7-49a3-bba0-466722d7dbeb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630345576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.1630345576
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.3679489517
Short name T842
Test name
Test status
Simulation time 206633800 ps
CPU time 13.75 seconds
Started Mar 10 12:38:13 PM PDT 24
Finished Mar 10 12:38:27 PM PDT 24
Peak memory 264756 kb
Host smart-0efbd1d2-3430-4c2b-8980-9b4d814ce6e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679489517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.3679489517
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.3237622215
Short name T903
Test name
Test status
Simulation time 82671300 ps
CPU time 31.28 seconds
Started Mar 10 12:38:13 PM PDT 24
Finished Mar 10 12:38:45 PM PDT 24
Peak memory 273008 kb
Host smart-fc152cfa-66e7-465e-9751-50df374a2ff1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237622215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.3237622215
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.970429117
Short name T868
Test name
Test status
Simulation time 51228400 ps
CPU time 28.17 seconds
Started Mar 10 12:38:11 PM PDT 24
Finished Mar 10 12:38:40 PM PDT 24
Peak memory 274052 kb
Host smart-dddbbb10-a447-4764-92d1-40d02732c211
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970429117 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.970429117
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.645537371
Short name T305
Test name
Test status
Simulation time 1257409800 ps
CPU time 51.76 seconds
Started Mar 10 12:38:14 PM PDT 24
Finished Mar 10 12:39:06 PM PDT 24
Peak memory 262000 kb
Host smart-e26794a8-0d21-40f5-8ff0-61c88e86f8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645537371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.645537371
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.1884895162
Short name T351
Test name
Test status
Simulation time 19653000 ps
CPU time 49.54 seconds
Started Mar 10 12:38:11 PM PDT 24
Finished Mar 10 12:39:01 PM PDT 24
Peak memory 269788 kb
Host smart-b6bc4997-0315-4560-acb3-c7a0b0807158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884895162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.1884895162
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.2880884965
Short name T483
Test name
Test status
Simulation time 54560900 ps
CPU time 13.6 seconds
Started Mar 10 12:38:17 PM PDT 24
Finished Mar 10 12:38:31 PM PDT 24
Peak memory 264340 kb
Host smart-c4f907c6-47ce-4107-affb-b2b0ebe17a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880884965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
2880884965
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.83885561
Short name T924
Test name
Test status
Simulation time 14880600 ps
CPU time 13.31 seconds
Started Mar 10 12:38:16 PM PDT 24
Finished Mar 10 12:38:29 PM PDT 24
Peak memory 273860 kb
Host smart-cd2ca50f-b5df-4c9b-962f-4e70d6585e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83885561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.83885561
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.3675934921
Short name T796
Test name
Test status
Simulation time 20311700 ps
CPU time 21.86 seconds
Started Mar 10 12:38:17 PM PDT 24
Finished Mar 10 12:38:39 PM PDT 24
Peak memory 264800 kb
Host smart-acf6ba4d-3bab-4fd4-8086-9926a4cf26e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675934921 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.3675934921
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.4072305654
Short name T899
Test name
Test status
Simulation time 6923609300 ps
CPU time 57.51 seconds
Started Mar 10 12:38:18 PM PDT 24
Finished Mar 10 12:39:17 PM PDT 24
Peak memory 258528 kb
Host smart-4fac86be-4977-47a1-a4ca-97e87d34bd8c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072305654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.4072305654
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.4169158612
Short name T603
Test name
Test status
Simulation time 5879124000 ps
CPU time 184.62 seconds
Started Mar 10 12:38:17 PM PDT 24
Finished Mar 10 12:41:22 PM PDT 24
Peak memory 292672 kb
Host smart-2a87f99e-fd4a-4f60-9749-f274d87b7eb6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169158612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.4169158612
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.406161556
Short name T886
Test name
Test status
Simulation time 18470063200 ps
CPU time 244.23 seconds
Started Mar 10 12:38:17 PM PDT 24
Finished Mar 10 12:42:22 PM PDT 24
Peak memory 283976 kb
Host smart-e456e349-6b85-4467-815d-96cf660a35b6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406161556 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.406161556
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.3711869207
Short name T147
Test name
Test status
Simulation time 67683600 ps
CPU time 132.6 seconds
Started Mar 10 12:38:21 PM PDT 24
Finished Mar 10 12:40:35 PM PDT 24
Peak memory 259012 kb
Host smart-067f2684-cfb3-437e-a3a0-06358e6e0579
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711869207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.3711869207
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.2670945208
Short name T1070
Test name
Test status
Simulation time 206554500 ps
CPU time 13.32 seconds
Started Mar 10 12:38:13 PM PDT 24
Finished Mar 10 12:38:26 PM PDT 24
Peak memory 263888 kb
Host smart-51de075a-6f70-401e-999a-11e6e4ed9024
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670945208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.2670945208
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.3547328289
Short name T418
Test name
Test status
Simulation time 55198500 ps
CPU time 32.47 seconds
Started Mar 10 12:38:16 PM PDT 24
Finished Mar 10 12:38:49 PM PDT 24
Peak memory 273060 kb
Host smart-31856d1a-0df2-4765-b869-fad1c7925dfc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547328289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.3547328289
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3789923254
Short name T202
Test name
Test status
Simulation time 27861200 ps
CPU time 30.7 seconds
Started Mar 10 12:38:18 PM PDT 24
Finished Mar 10 12:38:50 PM PDT 24
Peak memory 275144 kb
Host smart-3a00916f-b93d-400a-a004-28aa633be8a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789923254 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.3789923254
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.3776600633
Short name T726
Test name
Test status
Simulation time 34959100 ps
CPU time 122.11 seconds
Started Mar 10 12:38:15 PM PDT 24
Finished Mar 10 12:40:17 PM PDT 24
Peak memory 274720 kb
Host smart-ae77f5d9-1deb-4086-af88-cc34750ffbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776600633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3776600633
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.1879299521
Short name T707
Test name
Test status
Simulation time 69162600 ps
CPU time 13.84 seconds
Started Mar 10 12:38:19 PM PDT 24
Finished Mar 10 12:38:33 PM PDT 24
Peak memory 264416 kb
Host smart-f43f9fb7-5f53-48f9-8a68-5cb3f59046af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879299521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
1879299521
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.3507015963
Short name T481
Test name
Test status
Simulation time 49114600 ps
CPU time 15.93 seconds
Started Mar 10 12:38:24 PM PDT 24
Finished Mar 10 12:38:41 PM PDT 24
Peak memory 283348 kb
Host smart-747f0fd7-99fb-4926-87dc-015957be0003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507015963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3507015963
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.1123443451
Short name T501
Test name
Test status
Simulation time 16147500 ps
CPU time 22.15 seconds
Started Mar 10 12:38:21 PM PDT 24
Finished Mar 10 12:38:44 PM PDT 24
Peak memory 279772 kb
Host smart-1e186aea-44ec-410e-bd59-651354403fe3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123443451 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.1123443451
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.731213615
Short name T573
Test name
Test status
Simulation time 1108949600 ps
CPU time 89.12 seconds
Started Mar 10 12:38:20 PM PDT 24
Finished Mar 10 12:39:49 PM PDT 24
Peak memory 258504 kb
Host smart-5bf0db41-e897-4896-8f0e-f634b2a9f653
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731213615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_h
w_sec_otp.731213615
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.1895293202
Short name T1088
Test name
Test status
Simulation time 15299989900 ps
CPU time 193.75 seconds
Started Mar 10 12:38:22 PM PDT 24
Finished Mar 10 12:41:36 PM PDT 24
Peak memory 292552 kb
Host smart-3b8936ca-0465-4ae9-b43e-c7638ad75a11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895293202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.1895293202
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1789053354
Short name T840
Test name
Test status
Simulation time 30692448500 ps
CPU time 187.64 seconds
Started Mar 10 12:38:20 PM PDT 24
Finished Mar 10 12:41:28 PM PDT 24
Peak memory 290448 kb
Host smart-fdda507e-0fdc-4d63-9d41-f5bc2a11b7c1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789053354 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1789053354
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.1977936652
Short name T657
Test name
Test status
Simulation time 100797100 ps
CPU time 13.52 seconds
Started Mar 10 12:38:19 PM PDT 24
Finished Mar 10 12:38:33 PM PDT 24
Peak memory 263936 kb
Host smart-4299d457-acb4-4235-afdf-482dadaecce9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977936652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.1977936652
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.3420184375
Short name T940
Test name
Test status
Simulation time 28879700 ps
CPU time 30.19 seconds
Started Mar 10 12:38:23 PM PDT 24
Finished Mar 10 12:38:54 PM PDT 24
Peak memory 273032 kb
Host smart-7fd2c031-ace6-4c6c-a73b-9e5a327fac53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420184375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl
ash_ctrl_rw_evict.3420184375
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1227558849
Short name T1118
Test name
Test status
Simulation time 79948800 ps
CPU time 31.69 seconds
Started Mar 10 12:38:21 PM PDT 24
Finished Mar 10 12:38:54 PM PDT 24
Peak memory 276552 kb
Host smart-e39ee275-69ed-4ed0-867a-ab8a11296d9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227558849 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.1227558849
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.1104199597
Short name T376
Test name
Test status
Simulation time 1994314700 ps
CPU time 61.36 seconds
Started Mar 10 12:38:21 PM PDT 24
Finished Mar 10 12:39:23 PM PDT 24
Peak memory 262304 kb
Host smart-db2a2e3c-ff37-4daf-8757-1a888358a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104199597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.1104199597
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.3238864268
Short name T1086
Test name
Test status
Simulation time 139416600 ps
CPU time 97.9 seconds
Started Mar 10 12:38:15 PM PDT 24
Finished Mar 10 12:39:53 PM PDT 24
Peak memory 274864 kb
Host smart-354b1ea3-0c8f-4faa-9a63-9d1480abd54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238864268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.3238864268
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.1861077626
Short name T453
Test name
Test status
Simulation time 26583000 ps
CPU time 13.23 seconds
Started Mar 10 12:38:31 PM PDT 24
Finished Mar 10 12:38:45 PM PDT 24
Peak memory 264520 kb
Host smart-86bfd90d-2178-45e2-94d4-a5240456bb52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861077626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
1861077626
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.2127025568
Short name T496
Test name
Test status
Simulation time 25894700 ps
CPU time 15.97 seconds
Started Mar 10 12:38:28 PM PDT 24
Finished Mar 10 12:38:44 PM PDT 24
Peak memory 273936 kb
Host smart-48e27f03-7b7e-43d0-a0e4-2d837f7b4ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127025568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.2127025568
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.2572676669
Short name T93
Test name
Test status
Simulation time 17173000 ps
CPU time 20.52 seconds
Started Mar 10 12:38:26 PM PDT 24
Finished Mar 10 12:38:47 PM PDT 24
Peak memory 273008 kb
Host smart-234c5482-f462-4fb5-8214-096767b72b3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572676669 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.2572676669
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.3964714100
Short name T847
Test name
Test status
Simulation time 11475226300 ps
CPU time 102.69 seconds
Started Mar 10 12:38:31 PM PDT 24
Finished Mar 10 12:40:14 PM PDT 24
Peak memory 261644 kb
Host smart-d875fc90-6a3c-4ae8-8000-a31522f971f9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964714100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.3964714100
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.3382945856
Short name T499
Test name
Test status
Simulation time 1144258100 ps
CPU time 155.61 seconds
Started Mar 10 12:38:26 PM PDT 24
Finished Mar 10 12:41:02 PM PDT 24
Peak memory 284312 kb
Host smart-30fb5696-0b5b-460d-86b4-e3aaf8755284
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382945856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.3382945856
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3188449405
Short name T451
Test name
Test status
Simulation time 33000443600 ps
CPU time 190.52 seconds
Started Mar 10 12:38:26 PM PDT 24
Finished Mar 10 12:41:37 PM PDT 24
Peak memory 284104 kb
Host smart-ed4b8ea0-cfb3-4b9f-a264-26b6fc3f7f68
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188449405 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3188449405
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.2890219569
Short name T882
Test name
Test status
Simulation time 72229600 ps
CPU time 131.08 seconds
Started Mar 10 12:38:27 PM PDT 24
Finished Mar 10 12:40:38 PM PDT 24
Peak memory 259196 kb
Host smart-74a207d2-91bf-4e7e-8b99-51398e4f4dbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890219569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.2890219569
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.2366749555
Short name T1061
Test name
Test status
Simulation time 314414700 ps
CPU time 18.73 seconds
Started Mar 10 12:38:26 PM PDT 24
Finished Mar 10 12:38:45 PM PDT 24
Peak memory 264784 kb
Host smart-cea23cfa-65c6-4503-9f21-3d39dd535e0b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366749555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.2366749555
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.651761526
Short name T99
Test name
Test status
Simulation time 27513500 ps
CPU time 28.02 seconds
Started Mar 10 12:38:31 PM PDT 24
Finished Mar 10 12:39:00 PM PDT 24
Peak memory 265852 kb
Host smart-66497adc-6da5-48a1-be65-7f93967029cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651761526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_rw_evict.651761526
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.2769107813
Short name T27
Test name
Test status
Simulation time 108334700 ps
CPU time 28.65 seconds
Started Mar 10 12:38:29 PM PDT 24
Finished Mar 10 12:38:58 PM PDT 24
Peak memory 273156 kb
Host smart-e56c455a-4c2a-404d-be9b-43da4d34f17a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769107813 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.2769107813
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.1682971236
Short name T445
Test name
Test status
Simulation time 54371400 ps
CPU time 168.48 seconds
Started Mar 10 12:38:28 PM PDT 24
Finished Mar 10 12:41:17 PM PDT 24
Peak memory 277892 kb
Host smart-399afe5f-a2ff-4588-9bf1-aaa2cb3e2ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682971236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.1682971236
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.799167476
Short name T434
Test name
Test status
Simulation time 158709200 ps
CPU time 13.84 seconds
Started Mar 10 12:38:31 PM PDT 24
Finished Mar 10 12:38:45 PM PDT 24
Peak memory 264384 kb
Host smart-5041ce5c-8f54-40cf-8d33-a07ed4c687ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799167476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.799167476
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.4108795110
Short name T1075
Test name
Test status
Simulation time 21649800 ps
CPU time 13.51 seconds
Started Mar 10 12:38:37 PM PDT 24
Finished Mar 10 12:38:50 PM PDT 24
Peak memory 274064 kb
Host smart-662b9ad5-ecac-4b1d-a08c-c9caeecfcd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108795110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.4108795110
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.187911055
Short name T221
Test name
Test status
Simulation time 27398900 ps
CPU time 21.77 seconds
Started Mar 10 12:38:31 PM PDT 24
Finished Mar 10 12:38:53 PM PDT 24
Peak memory 279660 kb
Host smart-221f0c4a-a8b7-4553-9b71-d973ec47ba66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187911055 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.187911055
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.1108716009
Short name T81
Test name
Test status
Simulation time 1636212800 ps
CPU time 114.64 seconds
Started Mar 10 12:38:28 PM PDT 24
Finished Mar 10 12:40:23 PM PDT 24
Peak memory 261816 kb
Host smart-3536350c-88f1-49a7-9efb-c1c34bbc5e4c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108716009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.1108716009
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.2166081956
Short name T196
Test name
Test status
Simulation time 1040439900 ps
CPU time 153.25 seconds
Started Mar 10 12:38:24 PM PDT 24
Finished Mar 10 12:40:58 PM PDT 24
Peak memory 293568 kb
Host smart-f047d8b4-6c9e-442a-bb44-2576f0e01826
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166081956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.2166081956
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.2966315480
Short name T149
Test name
Test status
Simulation time 92006800 ps
CPU time 110.72 seconds
Started Mar 10 12:38:26 PM PDT 24
Finished Mar 10 12:40:16 PM PDT 24
Peak memory 258856 kb
Host smart-f6e0d2f6-60b6-4182-8f6f-e6d61ebf106a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966315480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.2966315480
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.2873229652
Short name T705
Test name
Test status
Simulation time 22825800 ps
CPU time 13.68 seconds
Started Mar 10 12:38:24 PM PDT 24
Finished Mar 10 12:38:38 PM PDT 24
Peak memory 264712 kb
Host smart-a787195c-fca3-43f9-9dbb-a2f7136fe9fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873229652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.2873229652
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.2232258500
Short name T936
Test name
Test status
Simulation time 70106100 ps
CPU time 30.22 seconds
Started Mar 10 12:38:31 PM PDT 24
Finished Mar 10 12:39:02 PM PDT 24
Peak memory 265820 kb
Host smart-797ea4f7-fd96-487a-8a1b-22a06745a972
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232258500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.2232258500
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.3363338229
Short name T987
Test name
Test status
Simulation time 29860400 ps
CPU time 30.73 seconds
Started Mar 10 12:38:30 PM PDT 24
Finished Mar 10 12:39:01 PM PDT 24
Peak memory 273136 kb
Host smart-046077a1-47b8-4ebc-8f2c-28f7839acb49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363338229 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.3363338229
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.2510253793
Short name T366
Test name
Test status
Simulation time 6131140900 ps
CPU time 68.17 seconds
Started Mar 10 12:38:30 PM PDT 24
Finished Mar 10 12:39:39 PM PDT 24
Peak memory 263600 kb
Host smart-363e530f-1681-486f-8d0a-8eedb5946b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510253793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.2510253793
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.666984539
Short name T832
Test name
Test status
Simulation time 22607800 ps
CPU time 75.08 seconds
Started Mar 10 12:38:25 PM PDT 24
Finished Mar 10 12:39:40 PM PDT 24
Peak memory 274068 kb
Host smart-dfad8b4a-0603-4b2f-9979-1a2c42172931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666984539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.666984539
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.365314746
Short name T533
Test name
Test status
Simulation time 94045900 ps
CPU time 13.31 seconds
Started Mar 10 12:35:44 PM PDT 24
Finished Mar 10 12:35:57 PM PDT 24
Peak memory 264148 kb
Host smart-618cce31-caac-4762-92d3-8cd097bf2aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365314746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.365314746
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.2802265396
Short name T175
Test name
Test status
Simulation time 19425600 ps
CPU time 13.66 seconds
Started Mar 10 12:35:39 PM PDT 24
Finished Mar 10 12:35:54 PM PDT 24
Peak memory 264668 kb
Host smart-70910d0b-2bff-468c-b87d-8bd79d5e400f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802265396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.2802265396
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.3042230889
Short name T246
Test name
Test status
Simulation time 38767900 ps
CPU time 13.18 seconds
Started Mar 10 12:35:36 PM PDT 24
Finished Mar 10 12:35:50 PM PDT 24
Peak memory 274028 kb
Host smart-e0cd14ae-7f86-4ce7-ac5a-ca9be08878da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042230889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.3042230889
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.3972077690
Short name T331
Test name
Test status
Simulation time 308509200 ps
CPU time 102.75 seconds
Started Mar 10 12:35:31 PM PDT 24
Finished Mar 10 12:37:14 PM PDT 24
Peak memory 280448 kb
Host smart-1974d96c-a648-470c-9680-38f38cd95ad9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972077690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.3972077690
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.471864025
Short name T345
Test name
Test status
Simulation time 15409000 ps
CPU time 21.41 seconds
Started Mar 10 12:35:36 PM PDT 24
Finished Mar 10 12:35:58 PM PDT 24
Peak memory 264832 kb
Host smart-a889b5d5-7d81-4af8-989d-4da19d514840
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471864025 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.471864025
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.643870746
Short name T121
Test name
Test status
Simulation time 29210351300 ps
CPU time 434.27 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:42:37 PM PDT 24
Peak memory 262236 kb
Host smart-d5d48638-edfa-4b8c-b115-aa5eb7159d5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643870746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.643870746
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.3381640864
Short name T1026
Test name
Test status
Simulation time 29794450100 ps
CPU time 2245.35 seconds
Started Mar 10 12:35:33 PM PDT 24
Finished Mar 10 01:12:59 PM PDT 24
Peak memory 263956 kb
Host smart-d63db83c-e0f9-4340-9335-876b5cb48789
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381640864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.3381640864
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.2462630742
Short name T765
Test name
Test status
Simulation time 2992607900 ps
CPU time 2606.16 seconds
Started Mar 10 12:35:33 PM PDT 24
Finished Mar 10 01:18:59 PM PDT 24
Peak memory 264380 kb
Host smart-6c953812-4361-43a3-aa07-cc3fc95b9ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462630742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.2462630742
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.297358750
Short name T289
Test name
Test status
Simulation time 1393773600 ps
CPU time 927.48 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:50:58 PM PDT 24
Peak memory 272944 kb
Host smart-8e125a6b-ba50-48b2-aabd-d530f8752a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297358750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.297358750
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.1990359039
Short name T510
Test name
Test status
Simulation time 849586300 ps
CPU time 20.84 seconds
Started Mar 10 12:35:31 PM PDT 24
Finished Mar 10 12:35:53 PM PDT 24
Peak memory 264600 kb
Host smart-ae026cf4-2166-4914-86ac-2cef7b96240d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990359039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.1990359039
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.2033886836
Short name T90
Test name
Test status
Simulation time 91870418500 ps
CPU time 2423.64 seconds
Started Mar 10 12:35:43 PM PDT 24
Finished Mar 10 01:16:08 PM PDT 24
Peak memory 261248 kb
Host smart-bdbe1137-dd73-406f-b3f1-c8202fe6e51d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033886836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.2033886836
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.2704128830
Short name T920
Test name
Test status
Simulation time 132066000 ps
CPU time 56.03 seconds
Started Mar 10 12:35:23 PM PDT 24
Finished Mar 10 12:36:20 PM PDT 24
Peak memory 264368 kb
Host smart-e306269b-9cfd-4697-aa35-33e91b322bf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2704128830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2704128830
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1865965469
Short name T74
Test name
Test status
Simulation time 10106452500 ps
CPU time 40.22 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:36:11 PM PDT 24
Peak memory 264820 kb
Host smart-ac31a462-c8fc-4a2c-bdb0-873f4ab15b5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865965469 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1865965469
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.2762504283
Short name T473
Test name
Test status
Simulation time 49317800 ps
CPU time 13.51 seconds
Started Mar 10 12:35:40 PM PDT 24
Finished Mar 10 12:35:54 PM PDT 24
Peak memory 264900 kb
Host smart-3e3b6589-2fa7-4eeb-b4b4-e44519cb046e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762504283 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.2762504283
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.671539759
Short name T354
Test name
Test status
Simulation time 40122392800 ps
CPU time 733.09 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:47:41 PM PDT 24
Peak memory 262528 kb
Host smart-e0d9ab9a-4bf5-4362-99a7-30e0f421dc30
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671539759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_hw_rma_reset.671539759
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.3801758017
Short name T526
Test name
Test status
Simulation time 2421734000 ps
CPU time 92.19 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:37:00 PM PDT 24
Peak memory 261360 kb
Host smart-be935278-529f-46c4-a1c7-2094c09ea6f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801758017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.3801758017
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.2658957904
Short name T252
Test name
Test status
Simulation time 22952604700 ps
CPU time 503.38 seconds
Started Mar 10 12:35:34 PM PDT 24
Finished Mar 10 12:43:57 PM PDT 24
Peak memory 332896 kb
Host smart-f2fab388-74b9-4d2d-ac6e-6b0241372efa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658957904 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_integrity.2658957904
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.2609681242
Short name T884
Test name
Test status
Simulation time 9931707900 ps
CPU time 143.02 seconds
Started Mar 10 12:35:33 PM PDT 24
Finished Mar 10 12:37:57 PM PDT 24
Peak memory 293052 kb
Host smart-8041dda2-c098-4872-bb54-f08260531645
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609681242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.2609681242
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3478398842
Short name T814
Test name
Test status
Simulation time 34746390300 ps
CPU time 203.14 seconds
Started Mar 10 12:35:38 PM PDT 24
Finished Mar 10 12:39:03 PM PDT 24
Peak memory 284004 kb
Host smart-7f6540d1-b6af-4d56-86a0-792538616ccc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478398842 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.3478398842
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.4084079104
Short name T514
Test name
Test status
Simulation time 23506950900 ps
CPU time 117.32 seconds
Started Mar 10 12:35:33 PM PDT 24
Finished Mar 10 12:37:30 PM PDT 24
Peak memory 264672 kb
Host smart-65160e2a-f85f-4157-a59c-9d2fa081da56
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084079104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.4084079104
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.624384539
Short name T845
Test name
Test status
Simulation time 54362507100 ps
CPU time 425.79 seconds
Started Mar 10 12:35:38 PM PDT 24
Finished Mar 10 12:42:46 PM PDT 24
Peak memory 264768 kb
Host smart-4b43db82-3855-4ca4-82eb-be458c6508dc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624
384539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.624384539
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.2117157988
Short name T381
Test name
Test status
Simulation time 3400639500 ps
CPU time 65.26 seconds
Started Mar 10 12:35:31 PM PDT 24
Finished Mar 10 12:36:36 PM PDT 24
Peak memory 259024 kb
Host smart-d91de852-c49b-4719-a417-96a4ae6c8b8b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117157988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2117157988
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.2222355297
Short name T528
Test name
Test status
Simulation time 15559400 ps
CPU time 13.31 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:35:44 PM PDT 24
Peak memory 264816 kb
Host smart-166a3b22-3064-4ad3-bb26-b2e05cd8cba9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222355297 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.2222355297
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.3966411248
Short name T912
Test name
Test status
Simulation time 3740476100 ps
CPU time 70.78 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:36:41 PM PDT 24
Peak memory 260032 kb
Host smart-4e9776b5-1c75-4135-a640-eb568f6e0c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966411248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.3966411248
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.4000337346
Short name T1104
Test name
Test status
Simulation time 29051668700 ps
CPU time 402.96 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:42:13 PM PDT 24
Peak memory 272940 kb
Host smart-511d14c3-4351-4740-9394-3b3aa3eb3fd3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000337346 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.4000337346
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.4166417122
Short name T570
Test name
Test status
Simulation time 2228210300 ps
CPU time 146.63 seconds
Started Mar 10 12:35:45 PM PDT 24
Finished Mar 10 12:38:11 PM PDT 24
Peak memory 281208 kb
Host smart-6c83aed2-0952-47fc-957e-8fef5b582186
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166417122 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.4166417122
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.4177764482
Short name T112
Test name
Test status
Simulation time 15457700 ps
CPU time 13.77 seconds
Started Mar 10 12:35:37 PM PDT 24
Finished Mar 10 12:35:54 PM PDT 24
Peak memory 278716 kb
Host smart-d0f1b910-a412-4895-8ccf-38f3981f0fcb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4177764482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.4177764482
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.2079671905
Short name T1024
Test name
Test status
Simulation time 723018100 ps
CPU time 385.55 seconds
Started Mar 10 12:35:25 PM PDT 24
Finished Mar 10 12:41:50 PM PDT 24
Peak memory 264520 kb
Host smart-5fa3bc2c-0d45-441d-9fa1-0451f72e4ca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2079671905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.2079671905
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.689295617
Short name T1003
Test name
Test status
Simulation time 689927500 ps
CPU time 22.53 seconds
Started Mar 10 12:35:42 PM PDT 24
Finished Mar 10 12:36:04 PM PDT 24
Peak memory 264908 kb
Host smart-fd3f3c60-8fbf-4b64-acd1-40c8c2db0bdd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689295617 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.689295617
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3479710602
Short name T277
Test name
Test status
Simulation time 15039300 ps
CPU time 13.97 seconds
Started Mar 10 12:35:35 PM PDT 24
Finished Mar 10 12:35:49 PM PDT 24
Peak memory 264904 kb
Host smart-783da358-f7da-4deb-a5c8-bac5e3d734c6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479710602 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3479710602
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.1054776573
Short name T442
Test name
Test status
Simulation time 33722400 ps
CPU time 13.29 seconds
Started Mar 10 12:35:32 PM PDT 24
Finished Mar 10 12:35:46 PM PDT 24
Peak memory 264672 kb
Host smart-c8886f25-a849-45e4-8f0e-3f8c60b6c876
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054776573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.1054776573
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.2383337658
Short name T562
Test name
Test status
Simulation time 1631355000 ps
CPU time 289.23 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:40:17 PM PDT 24
Peak memory 281020 kb
Host smart-1b0b3886-a1ed-4dbe-adaf-328d4ad501b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383337658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.2383337658
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.135363207
Short name T110
Test name
Test status
Simulation time 160065600 ps
CPU time 100.67 seconds
Started Mar 10 12:35:22 PM PDT 24
Finished Mar 10 12:37:04 PM PDT 24
Peak memory 264704 kb
Host smart-0aa52ddb-f236-4f47-8aea-affc0ecf338b
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=135363207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.135363207
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.1580096627
Short name T480
Test name
Test status
Simulation time 228672200 ps
CPU time 33.84 seconds
Started Mar 10 12:35:35 PM PDT 24
Finished Mar 10 12:36:09 PM PDT 24
Peak memory 277536 kb
Host smart-de6fd59d-5267-4ebe-9bd5-e00e4b425ebe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580096627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.1580096627
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.3922554039
Short name T960
Test name
Test status
Simulation time 24783500 ps
CPU time 22.67 seconds
Started Mar 10 12:35:38 PM PDT 24
Finished Mar 10 12:36:03 PM PDT 24
Peak memory 264952 kb
Host smart-d580092f-ef74-446a-afc7-77878eae7fe1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922554039 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.3922554039
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.2103233455
Short name T1113
Test name
Test status
Simulation time 24414900 ps
CPU time 22.41 seconds
Started Mar 10 12:35:39 PM PDT 24
Finished Mar 10 12:36:03 PM PDT 24
Peak memory 264820 kb
Host smart-459c533c-0e1c-4530-b3ee-b96dc4ded340
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103233455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.2103233455
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.2348646193
Short name T858
Test name
Test status
Simulation time 452491200 ps
CPU time 84.86 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:36:55 PM PDT 24
Peak memory 280420 kb
Host smart-190487bd-95e0-49f3-9c98-ca4432b68dd9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348646193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_ro.2348646193
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.3004677856
Short name T1077
Test name
Test status
Simulation time 821673000 ps
CPU time 101.08 seconds
Started Mar 10 12:35:28 PM PDT 24
Finished Mar 10 12:37:09 PM PDT 24
Peak memory 281232 kb
Host smart-9778e10b-f741-48b8-a52e-ef9e7a2f974a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3004677856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.3004677856
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.1094954636
Short name T993
Test name
Test status
Simulation time 1289378900 ps
CPU time 110.96 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:37:20 PM PDT 24
Peak memory 293596 kb
Host smart-bb961525-3f62-4c86-9a53-c107f005a06f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094954636 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.1094954636
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.2637195884
Short name T1029
Test name
Test status
Simulation time 6745535500 ps
CPU time 527.43 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:44:18 PM PDT 24
Peak memory 313872 kb
Host smart-705f579d-473f-4d27-8a2d-aa7e91d2d48c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637195884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_rw.2637195884
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.3294327099
Short name T1041
Test name
Test status
Simulation time 2880319200 ps
CPU time 623.18 seconds
Started Mar 10 12:35:34 PM PDT 24
Finished Mar 10 12:45:57 PM PDT 24
Peak memory 322652 kb
Host smart-a561c4f1-1eec-4748-9bb6-0f2f05bf7a36
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294327099 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_rw_derr.3294327099
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.1974877622
Short name T395
Test name
Test status
Simulation time 48878100 ps
CPU time 28.12 seconds
Started Mar 10 12:35:27 PM PDT 24
Finished Mar 10 12:35:56 PM PDT 24
Peak memory 265856 kb
Host smart-4a7d838f-5a0b-4187-b5f6-c76be2cb2bc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974877622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.1974877622
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.2623044956
Short name T625
Test name
Test status
Simulation time 43632600 ps
CPU time 30.81 seconds
Started Mar 10 12:35:32 PM PDT 24
Finished Mar 10 12:36:04 PM PDT 24
Peak memory 273044 kb
Host smart-f36f010e-aca9-42c8-a87c-ff3c436142e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623044956 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.2623044956
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.3944705019
Short name T673
Test name
Test status
Simulation time 3730686600 ps
CPU time 527.08 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:44:18 PM PDT 24
Peak memory 311252 kb
Host smart-f13b45f7-ff72-41e5-aebd-34e209d98822
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944705019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s
err.3944705019
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.466360299
Short name T415
Test name
Test status
Simulation time 9896621500 ps
CPU time 80.51 seconds
Started Mar 10 12:35:43 PM PDT 24
Finished Mar 10 12:37:04 PM PDT 24
Peak memory 264756 kb
Host smart-c57d8bd8-1cb5-4f8f-a200-c15099aa5fea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466360299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_serr_address.466360299
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.1984665288
Short name T35
Test name
Test status
Simulation time 1857388300 ps
CPU time 51.89 seconds
Started Mar 10 12:35:32 PM PDT 24
Finished Mar 10 12:36:24 PM PDT 24
Peak memory 264756 kb
Host smart-45c476d6-3be5-4d71-b546-1183247cc18e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984665288 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.1984665288
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.1430029818
Short name T618
Test name
Test status
Simulation time 20247900 ps
CPU time 75.31 seconds
Started Mar 10 12:35:35 PM PDT 24
Finished Mar 10 12:36:51 PM PDT 24
Peak memory 274024 kb
Host smart-67d53d4a-d541-457b-885f-e3a9d3030b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430029818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1430029818
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.2626503863
Short name T5
Test name
Test status
Simulation time 18291000 ps
CPU time 26.02 seconds
Started Mar 10 12:35:25 PM PDT 24
Finished Mar 10 12:35:51 PM PDT 24
Peak memory 258340 kb
Host smart-1e55e177-06e9-4af4-a5bb-7d1bfd9685ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626503863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.2626503863
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.400270223
Short name T978
Test name
Test status
Simulation time 3724803800 ps
CPU time 1690.28 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 01:03:41 PM PDT 24
Peak memory 288360 kb
Host smart-98f8afc2-68a9-4770-9a42-9a9840db03ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400270223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress
_all.400270223
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.2549265503
Short name T984
Test name
Test status
Simulation time 20530200 ps
CPU time 24.11 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:35:54 PM PDT 24
Peak memory 258356 kb
Host smart-44462cb9-d2cd-4808-a840-91d1ad6ff680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549265503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.2549265503
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.1867186642
Short name T513
Test name
Test status
Simulation time 12559656400 ps
CPU time 176.47 seconds
Started Mar 10 12:35:41 PM PDT 24
Finished Mar 10 12:38:38 PM PDT 24
Peak memory 264700 kb
Host smart-b404d6bd-cd2f-4732-be48-3c80fd9d4171
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867186642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.flash_ctrl_wo.1867186642
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.1778856546
Short name T999
Test name
Test status
Simulation time 269565300 ps
CPU time 13.61 seconds
Started Mar 10 12:38:32 PM PDT 24
Finished Mar 10 12:38:45 PM PDT 24
Peak memory 264328 kb
Host smart-6315c703-b545-498e-9f27-06a525ceedae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778856546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
1778856546
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.430441284
Short name T424
Test name
Test status
Simulation time 29387900 ps
CPU time 15.73 seconds
Started Mar 10 12:38:32 PM PDT 24
Finished Mar 10 12:38:48 PM PDT 24
Peak memory 273848 kb
Host smart-ba7cb4ea-ab8b-4c9f-b6ce-0f71ea27e869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430441284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.430441284
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.2180041063
Short name T835
Test name
Test status
Simulation time 65090400 ps
CPU time 21.03 seconds
Started Mar 10 12:38:30 PM PDT 24
Finished Mar 10 12:38:52 PM PDT 24
Peak memory 273112 kb
Host smart-fbb2b294-0727-4a8b-9e11-cbffa11a39af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180041063 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.2180041063
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.48009334
Short name T1006
Test name
Test status
Simulation time 20899739900 ps
CPU time 132.27 seconds
Started Mar 10 12:38:29 PM PDT 24
Finished Mar 10 12:40:42 PM PDT 24
Peak memory 258576 kb
Host smart-31094c0f-e6ed-407f-b68f-27ef28bc41c3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48009334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw
_sec_otp.48009334
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.178121082
Short name T278
Test name
Test status
Simulation time 1145653400 ps
CPU time 165.16 seconds
Started Mar 10 12:38:37 PM PDT 24
Finished Mar 10 12:41:22 PM PDT 24
Peak memory 293524 kb
Host smart-f498309a-b276-446e-9877-867d817afca9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178121082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flas
h_ctrl_intr_rd.178121082
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3879064861
Short name T606
Test name
Test status
Simulation time 19064087900 ps
CPU time 208.56 seconds
Started Mar 10 12:38:34 PM PDT 24
Finished Mar 10 12:42:03 PM PDT 24
Peak memory 284304 kb
Host smart-2c51c4c8-63b5-46b4-8b60-d11b64f42fa7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879064861 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.3879064861
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.3265697761
Short name T555
Test name
Test status
Simulation time 41095000 ps
CPU time 111.68 seconds
Started Mar 10 12:38:34 PM PDT 24
Finished Mar 10 12:40:25 PM PDT 24
Peak memory 259172 kb
Host smart-082ac6b6-6fcf-4f65-bc95-fcd55461be97
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265697761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.3265697761
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.3837678713
Short name T274
Test name
Test status
Simulation time 41514700 ps
CPU time 31.08 seconds
Started Mar 10 12:38:31 PM PDT 24
Finished Mar 10 12:39:02 PM PDT 24
Peak memory 265948 kb
Host smart-e7df1ba9-045a-4244-9312-8ddbbba5d7ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837678713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.3837678713
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.2532812909
Short name T760
Test name
Test status
Simulation time 31830800 ps
CPU time 31.27 seconds
Started Mar 10 12:38:31 PM PDT 24
Finished Mar 10 12:39:02 PM PDT 24
Peak memory 275456 kb
Host smart-4879d162-6616-47d6-92b5-db6b71b2eb9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532812909 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.2532812909
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.946681947
Short name T235
Test name
Test status
Simulation time 2792536400 ps
CPU time 63.49 seconds
Started Mar 10 12:38:33 PM PDT 24
Finished Mar 10 12:39:37 PM PDT 24
Peak memory 258888 kb
Host smart-de0a600e-4993-49d1-a000-db860bb318a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946681947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.946681947
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.3062269036
Short name T806
Test name
Test status
Simulation time 38434800 ps
CPU time 120.4 seconds
Started Mar 10 12:38:30 PM PDT 24
Finished Mar 10 12:40:31 PM PDT 24
Peak memory 274972 kb
Host smart-88fc25a0-9eba-4e8f-9537-cd9c89438cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062269036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3062269036
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.2093488670
Short name T945
Test name
Test status
Simulation time 54008900 ps
CPU time 13.78 seconds
Started Mar 10 12:38:36 PM PDT 24
Finished Mar 10 12:38:50 PM PDT 24
Peak memory 264132 kb
Host smart-9db102a8-be37-4f8b-aa18-dcf618d5e233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093488670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
2093488670
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.433485585
Short name T1082
Test name
Test status
Simulation time 14370900 ps
CPU time 15.78 seconds
Started Mar 10 12:38:35 PM PDT 24
Finished Mar 10 12:38:51 PM PDT 24
Peak memory 274760 kb
Host smart-3c6bc6c7-03c9-4c23-b783-afb5f6f8a2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433485585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.433485585
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.4293930299
Short name T344
Test name
Test status
Simulation time 23534000 ps
CPU time 21.73 seconds
Started Mar 10 12:38:37 PM PDT 24
Finished Mar 10 12:38:59 PM PDT 24
Peak memory 273004 kb
Host smart-f07dac26-5447-43a9-bc86-8d406e0797c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293930299 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.4293930299
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.2486223523
Short name T1114
Test name
Test status
Simulation time 19456064500 ps
CPU time 191.4 seconds
Started Mar 10 12:38:31 PM PDT 24
Finished Mar 10 12:41:43 PM PDT 24
Peak memory 258400 kb
Host smart-11b704e4-0f4f-47a7-8a6f-179c0b566711
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486223523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.2486223523
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.3251637752
Short name T979
Test name
Test status
Simulation time 7084656600 ps
CPU time 169.99 seconds
Started Mar 10 12:38:37 PM PDT 24
Finished Mar 10 12:41:28 PM PDT 24
Peak memory 293048 kb
Host smart-3bf4db28-5ad1-4379-befb-ab47124bfc32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251637752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.3251637752
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3411347851
Short name T1040
Test name
Test status
Simulation time 8835548500 ps
CPU time 194.86 seconds
Started Mar 10 12:38:31 PM PDT 24
Finished Mar 10 12:41:46 PM PDT 24
Peak memory 283964 kb
Host smart-1a82e36c-155a-492c-bb8f-53eea078f4b3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411347851 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.3411347851
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.3188549341
Short name T849
Test name
Test status
Simulation time 46259900 ps
CPU time 132.95 seconds
Started Mar 10 12:38:37 PM PDT 24
Finished Mar 10 12:40:50 PM PDT 24
Peak memory 259244 kb
Host smart-5e684344-79a2-4c0d-885a-c87adb106b50
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188549341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.3188549341
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.596799229
Short name T688
Test name
Test status
Simulation time 29955200 ps
CPU time 31.41 seconds
Started Mar 10 12:38:34 PM PDT 24
Finished Mar 10 12:39:06 PM PDT 24
Peak memory 273140 kb
Host smart-4282bbf0-6b11-47e0-afb3-8745e4ca046d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596799229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_rw_evict.596799229
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.429158474
Short name T900
Test name
Test status
Simulation time 31275800 ps
CPU time 31.21 seconds
Started Mar 10 12:38:30 PM PDT 24
Finished Mar 10 12:39:01 PM PDT 24
Peak memory 273116 kb
Host smart-b9768ccb-32f3-4b1b-b90e-41fc20300bb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429158474 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.429158474
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.2123141294
Short name T901
Test name
Test status
Simulation time 700797700 ps
CPU time 64.46 seconds
Started Mar 10 12:38:36 PM PDT 24
Finished Mar 10 12:39:40 PM PDT 24
Peak memory 262280 kb
Host smart-0619b2ac-3512-44d3-81f5-2cae9bfb3580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123141294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2123141294
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.1823539667
Short name T404
Test name
Test status
Simulation time 23902000 ps
CPU time 53.22 seconds
Started Mar 10 12:38:31 PM PDT 24
Finished Mar 10 12:39:25 PM PDT 24
Peak memory 269732 kb
Host smart-b3692916-46a9-4346-824b-87943d8e3ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823539667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1823539667
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.3059660681
Short name T299
Test name
Test status
Simulation time 304676600 ps
CPU time 13.95 seconds
Started Mar 10 12:38:41 PM PDT 24
Finished Mar 10 12:38:55 PM PDT 24
Peak memory 264360 kb
Host smart-6c1cbf50-239a-4755-af5a-c76912eaf6da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059660681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
3059660681
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.3105610746
Short name T833
Test name
Test status
Simulation time 46486600 ps
CPU time 15.65 seconds
Started Mar 10 12:38:36 PM PDT 24
Finished Mar 10 12:38:52 PM PDT 24
Peak memory 274092 kb
Host smart-f925aa99-7d49-438f-8140-fbe5cb40823e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105610746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.3105610746
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.3716933626
Short name T357
Test name
Test status
Simulation time 13062200 ps
CPU time 21.83 seconds
Started Mar 10 12:38:36 PM PDT 24
Finished Mar 10 12:38:58 PM PDT 24
Peak memory 272956 kb
Host smart-5cf364cd-3657-4513-904b-5cda29524066
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716933626 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.3716933626
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.1633321851
Short name T416
Test name
Test status
Simulation time 18535332400 ps
CPU time 120.45 seconds
Started Mar 10 12:38:35 PM PDT 24
Finished Mar 10 12:40:35 PM PDT 24
Peak memory 258492 kb
Host smart-bb4d11f5-1f9b-4731-92c6-daf74b471d0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633321851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.1633321851
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.4273410940
Short name T275
Test name
Test status
Simulation time 8147417900 ps
CPU time 169.25 seconds
Started Mar 10 12:38:38 PM PDT 24
Finished Mar 10 12:41:27 PM PDT 24
Peak memory 293156 kb
Host smart-dd56fc53-eed8-4af4-b11e-03ae3e4e7e11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273410940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.4273410940
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1807942667
Short name T491
Test name
Test status
Simulation time 8715926800 ps
CPU time 177.12 seconds
Started Mar 10 12:38:35 PM PDT 24
Finished Mar 10 12:41:32 PM PDT 24
Peak memory 283944 kb
Host smart-36216d69-21bd-491d-8c1f-f2fe69d954e2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807942667 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.1807942667
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.4047010391
Short name T538
Test name
Test status
Simulation time 39974500 ps
CPU time 130.4 seconds
Started Mar 10 12:38:36 PM PDT 24
Finished Mar 10 12:40:46 PM PDT 24
Peak memory 260248 kb
Host smart-d529c905-8834-4b67-8a7b-4b436d37ec5e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047010391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.4047010391
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.3127759159
Short name T389
Test name
Test status
Simulation time 70927800 ps
CPU time 30.73 seconds
Started Mar 10 12:38:36 PM PDT 24
Finished Mar 10 12:39:07 PM PDT 24
Peak memory 274176 kb
Host smart-8a9d698f-c28b-4129-a33c-d8aeb376aad2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127759159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.3127759159
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.45408849
Short name T926
Test name
Test status
Simulation time 71248600 ps
CPU time 31.07 seconds
Started Mar 10 12:38:35 PM PDT 24
Finished Mar 10 12:39:06 PM PDT 24
Peak memory 265908 kb
Host smart-419a3bb8-beec-4762-b7fe-4cc8d313c2b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45408849 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.45408849
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.3555104563
Short name T371
Test name
Test status
Simulation time 532718700 ps
CPU time 69.22 seconds
Started Mar 10 12:38:37 PM PDT 24
Finished Mar 10 12:39:46 PM PDT 24
Peak memory 262360 kb
Host smart-25713be7-f0e2-43d3-a76c-a64570e18ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555104563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3555104563
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.2005866360
Short name T454
Test name
Test status
Simulation time 67940000 ps
CPU time 98.47 seconds
Started Mar 10 12:38:35 PM PDT 24
Finished Mar 10 12:40:14 PM PDT 24
Peak memory 274768 kb
Host smart-e9e7d99f-6e91-4362-872a-f8e4193ea9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005866360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.2005866360
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.1329787638
Short name T537
Test name
Test status
Simulation time 36518600 ps
CPU time 13.53 seconds
Started Mar 10 12:38:42 PM PDT 24
Finished Mar 10 12:38:55 PM PDT 24
Peak memory 263868 kb
Host smart-fbf5c69d-5486-447a-9460-2a9ab2d842d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329787638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
1329787638
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.1577026890
Short name T577
Test name
Test status
Simulation time 44692300 ps
CPU time 13.25 seconds
Started Mar 10 12:38:53 PM PDT 24
Finished Mar 10 12:39:07 PM PDT 24
Peak memory 274936 kb
Host smart-502315b0-5b5e-4d43-b362-73782bdf0431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577026890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.1577026890
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.1118856193
Short name T12
Test name
Test status
Simulation time 20002500 ps
CPU time 20.75 seconds
Started Mar 10 12:38:45 PM PDT 24
Finished Mar 10 12:39:06 PM PDT 24
Peak memory 273096 kb
Host smart-f4f0bb3f-e664-4380-8f3f-729570c37e4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118856193 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.1118856193
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.2162320702
Short name T975
Test name
Test status
Simulation time 11841987500 ps
CPU time 244.23 seconds
Started Mar 10 12:38:40 PM PDT 24
Finished Mar 10 12:42:44 PM PDT 24
Peak memory 258384 kb
Host smart-0bbc20c7-9267-498b-8794-3ad489a7f3f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162320702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.2162320702
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.1274374204
Short name T736
Test name
Test status
Simulation time 2549851100 ps
CPU time 160.66 seconds
Started Mar 10 12:38:53 PM PDT 24
Finished Mar 10 12:41:34 PM PDT 24
Peak memory 294268 kb
Host smart-f6c6b190-bae7-4bdf-8f64-6840b87ea66d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274374204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.1274374204
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.2672076958
Short name T1055
Test name
Test status
Simulation time 9051598900 ps
CPU time 235.59 seconds
Started Mar 10 12:38:41 PM PDT 24
Finished Mar 10 12:42:37 PM PDT 24
Peak memory 293116 kb
Host smart-70cf5848-5bb8-44e2-9e7e-4491b39c7043
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672076958 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.2672076958
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.1924696967
Short name T253
Test name
Test status
Simulation time 272159200 ps
CPU time 131.76 seconds
Started Mar 10 12:38:44 PM PDT 24
Finished Mar 10 12:40:57 PM PDT 24
Peak memory 259104 kb
Host smart-93600281-1767-4165-9a76-07b87eb38ecb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924696967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.1924696967
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.1176400595
Short name T386
Test name
Test status
Simulation time 686246500 ps
CPU time 39.11 seconds
Started Mar 10 12:38:40 PM PDT 24
Finished Mar 10 12:39:19 PM PDT 24
Peak memory 273092 kb
Host smart-69658ea4-e0d1-488d-8c22-20c473fd554a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176400595 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.1176400595
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.957069359
Short name T495
Test name
Test status
Simulation time 1354742800 ps
CPU time 66.99 seconds
Started Mar 10 12:38:53 PM PDT 24
Finished Mar 10 12:40:00 PM PDT 24
Peak memory 259056 kb
Host smart-9962e0b3-0086-40c5-8375-e4c34d637a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957069359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.957069359
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.3025380187
Short name T1092
Test name
Test status
Simulation time 109982100 ps
CPU time 49.17 seconds
Started Mar 10 12:38:43 PM PDT 24
Finished Mar 10 12:39:32 PM PDT 24
Peak memory 269900 kb
Host smart-fb0e215e-1796-4848-9171-be7299c4429e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025380187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3025380187
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.2308063095
Short name T1098
Test name
Test status
Simulation time 50179700 ps
CPU time 13.55 seconds
Started Mar 10 12:38:46 PM PDT 24
Finished Mar 10 12:38:59 PM PDT 24
Peak memory 264340 kb
Host smart-044b4dea-976a-41e4-84cc-565239780902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308063095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
2308063095
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.1199755125
Short name T992
Test name
Test status
Simulation time 164717300 ps
CPU time 16.1 seconds
Started Mar 10 12:38:46 PM PDT 24
Finished Mar 10 12:39:02 PM PDT 24
Peak memory 275064 kb
Host smart-84b625c4-25bf-4c90-b8d8-7fca8a92ab3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199755125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1199755125
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.2149666983
Short name T219
Test name
Test status
Simulation time 10988400 ps
CPU time 21.66 seconds
Started Mar 10 12:38:46 PM PDT 24
Finished Mar 10 12:39:08 PM PDT 24
Peak memory 264672 kb
Host smart-f15b6e71-0d39-4395-8a51-aee6672c79c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149666983 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.2149666983
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.68462944
Short name T1019
Test name
Test status
Simulation time 13066778500 ps
CPU time 123.87 seconds
Started Mar 10 12:38:43 PM PDT 24
Finished Mar 10 12:40:47 PM PDT 24
Peak memory 258524 kb
Host smart-03377248-7484-4c30-ad75-9198933aaacc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68462944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw
_sec_otp.68462944
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.2801080436
Short name T801
Test name
Test status
Simulation time 6062657600 ps
CPU time 179.34 seconds
Started Mar 10 12:38:53 PM PDT 24
Finished Mar 10 12:41:53 PM PDT 24
Peak memory 294028 kb
Host smart-279f8e00-20cc-47b1-9c45-68a2ec0f2691
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801080436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.2801080436
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.2716313035
Short name T623
Test name
Test status
Simulation time 39077668100 ps
CPU time 204.58 seconds
Started Mar 10 12:38:42 PM PDT 24
Finished Mar 10 12:42:07 PM PDT 24
Peak memory 284312 kb
Host smart-8aa0a4b8-199e-4713-ae6e-cefc1297d317
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716313035 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.2716313035
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.3208889828
Short name T1083
Test name
Test status
Simulation time 221277500 ps
CPU time 133.09 seconds
Started Mar 10 12:38:53 PM PDT 24
Finished Mar 10 12:41:06 PM PDT 24
Peak memory 260348 kb
Host smart-22ce4ae9-06af-4c5d-af4f-deec36441bcf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208889828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.3208889828
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.2567685139
Short name T1064
Test name
Test status
Simulation time 233356300 ps
CPU time 29.05 seconds
Started Mar 10 12:38:40 PM PDT 24
Finished Mar 10 12:39:09 PM PDT 24
Peak memory 273044 kb
Host smart-0c3ad02d-29c5-40b4-94e8-b406eef89c33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567685139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.2567685139
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.3753398424
Short name T388
Test name
Test status
Simulation time 30623800 ps
CPU time 31.19 seconds
Started Mar 10 12:38:42 PM PDT 24
Finished Mar 10 12:39:13 PM PDT 24
Peak memory 273192 kb
Host smart-6bc6a274-30b1-4111-a7a5-3e67983e08f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753398424 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.3753398424
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.1733906787
Short name T670
Test name
Test status
Simulation time 2547216000 ps
CPU time 63.25 seconds
Started Mar 10 12:38:48 PM PDT 24
Finished Mar 10 12:39:51 PM PDT 24
Peak memory 258960 kb
Host smart-8432c4eb-c90f-4e2e-b2f2-fc2df8846d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733906787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1733906787
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.4120603306
Short name T540
Test name
Test status
Simulation time 32726500 ps
CPU time 121.38 seconds
Started Mar 10 12:38:40 PM PDT 24
Finished Mar 10 12:40:41 PM PDT 24
Peak memory 274944 kb
Host smart-82d24a1d-edba-453e-928c-cfc17a869caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120603306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.4120603306
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.156380340
Short name T974
Test name
Test status
Simulation time 159337700 ps
CPU time 13.9 seconds
Started Mar 10 12:38:47 PM PDT 24
Finished Mar 10 12:39:01 PM PDT 24
Peak memory 264360 kb
Host smart-746127a4-7423-4fe6-9d4f-6519bbf53903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156380340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.156380340
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2393211602
Short name T717
Test name
Test status
Simulation time 46111300 ps
CPU time 13.28 seconds
Started Mar 10 12:38:45 PM PDT 24
Finished Mar 10 12:38:59 PM PDT 24
Peak memory 274016 kb
Host smart-d027a3b9-f52d-4abe-93ff-0017d8cdc3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393211602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2393211602
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.787269500
Short name T714
Test name
Test status
Simulation time 10347800 ps
CPU time 22.01 seconds
Started Mar 10 12:38:47 PM PDT 24
Finished Mar 10 12:39:09 PM PDT 24
Peak memory 264764 kb
Host smart-ab0e7b3f-30e6-41cb-bec4-ec78f4e8fac1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787269500 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.787269500
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.977471467
Short name T313
Test name
Test status
Simulation time 4331031100 ps
CPU time 140.76 seconds
Started Mar 10 12:38:47 PM PDT 24
Finished Mar 10 12:41:08 PM PDT 24
Peak memory 258624 kb
Host smart-f8eba9cf-1cbd-4d05-8c43-bac98a3c02fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977471467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_h
w_sec_otp.977471467
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.2658338022
Short name T1028
Test name
Test status
Simulation time 927794000 ps
CPU time 143.26 seconds
Started Mar 10 12:38:47 PM PDT 24
Finished Mar 10 12:41:10 PM PDT 24
Peak memory 294316 kb
Host smart-63fb3597-97cb-44d5-b0d4-15688b43f3aa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658338022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.2658338022
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.2419656277
Short name T593
Test name
Test status
Simulation time 8976505700 ps
CPU time 204.91 seconds
Started Mar 10 12:38:48 PM PDT 24
Finished Mar 10 12:42:14 PM PDT 24
Peak memory 293348 kb
Host smart-5b01662c-f323-4954-a484-55d38fca0311
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419656277 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.2419656277
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.4181727116
Short name T152
Test name
Test status
Simulation time 37658000 ps
CPU time 131.78 seconds
Started Mar 10 12:38:46 PM PDT 24
Finished Mar 10 12:40:57 PM PDT 24
Peak memory 259168 kb
Host smart-e60a3ce8-38b0-4d9a-8955-1c7f43cf8edf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181727116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.4181727116
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.1361385681
Short name T889
Test name
Test status
Simulation time 108388500 ps
CPU time 28.21 seconds
Started Mar 10 12:38:45 PM PDT 24
Finished Mar 10 12:39:13 PM PDT 24
Peak memory 273112 kb
Host smart-6b7f805c-3200-490c-9bf9-ff795ec16a8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361385681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.1361385681
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.2954698504
Short name T185
Test name
Test status
Simulation time 29988700 ps
CPU time 28.84 seconds
Started Mar 10 12:38:45 PM PDT 24
Finished Mar 10 12:39:14 PM PDT 24
Peak memory 273044 kb
Host smart-ccfbf202-84b7-4792-9b6f-bdb937406701
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954698504 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.2954698504
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.1395552166
Short name T600
Test name
Test status
Simulation time 4236364400 ps
CPU time 65.12 seconds
Started Mar 10 12:38:52 PM PDT 24
Finished Mar 10 12:39:57 PM PDT 24
Peak memory 261580 kb
Host smart-a8e5f49e-bd20-467a-9fbc-fc411f9f672d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395552166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.1395552166
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.1936845253
Short name T977
Test name
Test status
Simulation time 33006300 ps
CPU time 145.73 seconds
Started Mar 10 12:38:48 PM PDT 24
Finished Mar 10 12:41:14 PM PDT 24
Peak memory 275472 kb
Host smart-115f9539-6289-40ba-8c50-bff8aeddabda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936845253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1936845253
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.815424105
Short name T608
Test name
Test status
Simulation time 66627400 ps
CPU time 13.39 seconds
Started Mar 10 12:38:51 PM PDT 24
Finished Mar 10 12:39:04 PM PDT 24
Peak memory 263804 kb
Host smart-20a9d61f-6894-402c-85af-252051df2b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815424105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.815424105
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.3055320415
Short name T637
Test name
Test status
Simulation time 52390900 ps
CPU time 15.85 seconds
Started Mar 10 12:38:53 PM PDT 24
Finished Mar 10 12:39:09 PM PDT 24
Peak memory 273928 kb
Host smart-e2ea12d1-fe51-4a45-9804-9a41722d77f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055320415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3055320415
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.3105897011
Short name T355
Test name
Test status
Simulation time 13154000 ps
CPU time 21.74 seconds
Started Mar 10 12:38:55 PM PDT 24
Finished Mar 10 12:39:16 PM PDT 24
Peak memory 265012 kb
Host smart-c1b86941-db44-480b-a169-e2bf680e0b5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105897011 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.3105897011
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.2966466843
Short name T543
Test name
Test status
Simulation time 3538411600 ps
CPU time 66.65 seconds
Started Mar 10 12:38:49 PM PDT 24
Finished Mar 10 12:39:56 PM PDT 24
Peak memory 258560 kb
Host smart-956911c2-0664-484e-9c71-611c6b3c09ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966466843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.2966466843
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.4029649661
Short name T619
Test name
Test status
Simulation time 1220052300 ps
CPU time 150.65 seconds
Started Mar 10 12:38:51 PM PDT 24
Finished Mar 10 12:41:21 PM PDT 24
Peak memory 293488 kb
Host smart-998ddb4a-65b7-42dd-b2cb-44d27e8e1192
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029649661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.4029649661
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3175156043
Short name T969
Test name
Test status
Simulation time 9076360700 ps
CPU time 349.39 seconds
Started Mar 10 12:38:56 PM PDT 24
Finished Mar 10 12:44:46 PM PDT 24
Peak memory 284168 kb
Host smart-ecce9490-a24b-4a48-a586-1270359e899a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175156043 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.3175156043
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2269878688
Short name T592
Test name
Test status
Simulation time 30225300 ps
CPU time 30.92 seconds
Started Mar 10 12:38:52 PM PDT 24
Finished Mar 10 12:39:23 PM PDT 24
Peak memory 265900 kb
Host smart-afdf4886-c85d-4d5d-966b-e56dc454a332
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269878688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2269878688
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.2695743977
Short name T678
Test name
Test status
Simulation time 29652000 ps
CPU time 31.32 seconds
Started Mar 10 12:38:50 PM PDT 24
Finished Mar 10 12:39:22 PM PDT 24
Peak memory 273128 kb
Host smart-2cc420c5-5684-428f-ac7c-8156d8d79574
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695743977 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.2695743977
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.2230555433
Short name T398
Test name
Test status
Simulation time 78450900 ps
CPU time 96.19 seconds
Started Mar 10 12:38:51 PM PDT 24
Finished Mar 10 12:40:27 PM PDT 24
Peak memory 275688 kb
Host smart-64a5a6a6-2057-455d-88e3-3ea53ba232c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230555433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2230555433
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.3774772501
Short name T609
Test name
Test status
Simulation time 102372500 ps
CPU time 13.65 seconds
Started Mar 10 12:38:59 PM PDT 24
Finished Mar 10 12:39:12 PM PDT 24
Peak memory 264288 kb
Host smart-71afd0ba-c47a-482e-8110-34ec27637e56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774772501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
3774772501
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.1611774592
Short name T807
Test name
Test status
Simulation time 14597100 ps
CPU time 15.56 seconds
Started Mar 10 12:38:58 PM PDT 24
Finished Mar 10 12:39:13 PM PDT 24
Peak memory 274840 kb
Host smart-525ed407-d017-4af9-8c45-1803b3e3e769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611774592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1611774592
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.4272009621
Short name T353
Test name
Test status
Simulation time 34321800 ps
CPU time 20.74 seconds
Started Mar 10 12:39:00 PM PDT 24
Finished Mar 10 12:39:21 PM PDT 24
Peak memory 264712 kb
Host smart-9938684f-591f-491f-b644-4cd9e7fda6e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272009621 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.4272009621
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1003708897
Short name T439
Test name
Test status
Simulation time 788048300 ps
CPU time 31.03 seconds
Started Mar 10 12:38:54 PM PDT 24
Finished Mar 10 12:39:26 PM PDT 24
Peak memory 261672 kb
Host smart-8bb5c1f4-6337-4466-8df2-90ed0d9af59f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003708897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.1003708897
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.1692263715
Short name T1036
Test name
Test status
Simulation time 2637982300 ps
CPU time 206.31 seconds
Started Mar 10 12:38:52 PM PDT 24
Finished Mar 10 12:42:18 PM PDT 24
Peak memory 289460 kb
Host smart-ce81f91e-1c96-4d4a-ba97-628fbc3fd6b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692263715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.1692263715
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2752802149
Short name T1066
Test name
Test status
Simulation time 9149514600 ps
CPU time 196.24 seconds
Started Mar 10 12:38:49 PM PDT 24
Finished Mar 10 12:42:06 PM PDT 24
Peak memory 284216 kb
Host smart-c42c6492-5dbb-4fd3-b002-f84d9b78d2d0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752802149 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.2752802149
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.2555734595
Short name T668
Test name
Test status
Simulation time 140661100 ps
CPU time 133.6 seconds
Started Mar 10 12:38:52 PM PDT 24
Finished Mar 10 12:41:05 PM PDT 24
Peak memory 259180 kb
Host smart-72201cac-70d2-4389-a423-27fe99e18e49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555734595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.2555734595
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.2032087647
Short name T930
Test name
Test status
Simulation time 88504800 ps
CPU time 32.95 seconds
Started Mar 10 12:38:53 PM PDT 24
Finished Mar 10 12:39:26 PM PDT 24
Peak memory 265980 kb
Host smart-9ba7d375-46dc-484f-be75-726c03acc17c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032087647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.2032087647
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.1951062906
Short name T515
Test name
Test status
Simulation time 32777400 ps
CPU time 30.54 seconds
Started Mar 10 12:39:01 PM PDT 24
Finished Mar 10 12:39:32 PM PDT 24
Peak memory 273104 kb
Host smart-adce120e-22de-4838-99e5-eb8706235663
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951062906 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.1951062906
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.2860568997
Short name T937
Test name
Test status
Simulation time 2120019600 ps
CPU time 61.09 seconds
Started Mar 10 12:39:00 PM PDT 24
Finished Mar 10 12:40:02 PM PDT 24
Peak memory 261000 kb
Host smart-20637a30-839e-46b3-b047-41cf259a72cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860568997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.2860568997
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.325309369
Short name T931
Test name
Test status
Simulation time 15727800 ps
CPU time 51.29 seconds
Started Mar 10 12:38:51 PM PDT 24
Finished Mar 10 12:39:43 PM PDT 24
Peak memory 269900 kb
Host smart-05109d20-39da-47f9-bb1d-5007263b98f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325309369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.325309369
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.1952235652
Short name T452
Test name
Test status
Simulation time 153166600 ps
CPU time 13.44 seconds
Started Mar 10 12:39:02 PM PDT 24
Finished Mar 10 12:39:17 PM PDT 24
Peak memory 263516 kb
Host smart-22be618e-41a1-416a-b628-58a135651be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952235652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
1952235652
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.158926807
Short name T742
Test name
Test status
Simulation time 40298800 ps
CPU time 15.91 seconds
Started Mar 10 12:39:00 PM PDT 24
Finished Mar 10 12:39:16 PM PDT 24
Peak memory 274824 kb
Host smart-b72845c6-cbd4-4cca-a79f-776919ca252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158926807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.158926807
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.4056040452
Short name T348
Test name
Test status
Simulation time 30869300 ps
CPU time 20.87 seconds
Started Mar 10 12:39:01 PM PDT 24
Finished Mar 10 12:39:24 PM PDT 24
Peak memory 273048 kb
Host smart-daf7a755-1d6d-4da1-a3f4-307690dab360
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056040452 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.4056040452
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.4011469057
Short name T1027
Test name
Test status
Simulation time 1681412000 ps
CPU time 133.27 seconds
Started Mar 10 12:38:59 PM PDT 24
Finished Mar 10 12:41:12 PM PDT 24
Peak memory 258448 kb
Host smart-d608986c-1a6a-43e2-913b-aa4735e0e3d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011469057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.4011469057
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.1194820604
Short name T915
Test name
Test status
Simulation time 2736368400 ps
CPU time 205.66 seconds
Started Mar 10 12:39:01 PM PDT 24
Finished Mar 10 12:42:27 PM PDT 24
Peak memory 293104 kb
Host smart-9c373571-792d-4c2e-b6f1-3471b287ba42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194820604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.1194820604
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.2985550281
Short name T119
Test name
Test status
Simulation time 8680277200 ps
CPU time 193.97 seconds
Started Mar 10 12:39:02 PM PDT 24
Finished Mar 10 12:42:17 PM PDT 24
Peak memory 290180 kb
Host smart-4c461d90-9897-4a6e-9651-dc8d08381fe1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985550281 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.2985550281
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.665210441
Short name T647
Test name
Test status
Simulation time 33622900 ps
CPU time 132.46 seconds
Started Mar 10 12:39:05 PM PDT 24
Finished Mar 10 12:41:18 PM PDT 24
Peak memory 263688 kb
Host smart-f716de31-a078-4608-9769-f0a6af811e6e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665210441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ot
p_reset.665210441
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.2248102192
Short name T836
Test name
Test status
Simulation time 50751800 ps
CPU time 31.28 seconds
Started Mar 10 12:38:58 PM PDT 24
Finished Mar 10 12:39:30 PM PDT 24
Peak memory 274084 kb
Host smart-cfcc6fa5-bc88-4a71-8b1c-059973833ba4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248102192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.2248102192
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.2181681756
Short name T725
Test name
Test status
Simulation time 222786600 ps
CPU time 31.63 seconds
Started Mar 10 12:39:01 PM PDT 24
Finished Mar 10 12:39:33 PM PDT 24
Peak memory 273060 kb
Host smart-6bd0f9c2-9948-4d1b-8bf5-181ef5cc1757
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181681756 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.2181681756
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.972269982
Short name T793
Test name
Test status
Simulation time 6223520300 ps
CPU time 63.56 seconds
Started Mar 10 12:39:02 PM PDT 24
Finished Mar 10 12:40:07 PM PDT 24
Peak memory 258832 kb
Host smart-af142129-a5ba-4001-b338-c97c5d7a5d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972269982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.972269982
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.2105967031
Short name T941
Test name
Test status
Simulation time 41405800 ps
CPU time 51.84 seconds
Started Mar 10 12:38:59 PM PDT 24
Finished Mar 10 12:39:51 PM PDT 24
Peak memory 269836 kb
Host smart-65e95fd9-9b0b-43bc-8573-ca51743efaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105967031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.2105967031
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.2352692773
Short name T436
Test name
Test status
Simulation time 90899300 ps
CPU time 13.52 seconds
Started Mar 10 12:39:07 PM PDT 24
Finished Mar 10 12:39:21 PM PDT 24
Peak memory 264404 kb
Host smart-a5f15ec3-41c3-48e8-83f8-2d0b9cf5b0ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352692773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
2352692773
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.2056023999
Short name T658
Test name
Test status
Simulation time 176716100 ps
CPU time 15.87 seconds
Started Mar 10 12:39:07 PM PDT 24
Finished Mar 10 12:39:23 PM PDT 24
Peak memory 273984 kb
Host smart-c4e3c1ae-2ebc-4581-8285-2650589cc729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056023999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2056023999
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.1631425670
Short name T41
Test name
Test status
Simulation time 10825600 ps
CPU time 21.48 seconds
Started Mar 10 12:39:07 PM PDT 24
Finished Mar 10 12:39:28 PM PDT 24
Peak memory 273032 kb
Host smart-dffaabd5-f9ae-4386-86ab-a0eed728c0a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631425670 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.1631425670
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.3245036673
Short name T996
Test name
Test status
Simulation time 3314502200 ps
CPU time 72.93 seconds
Started Mar 10 12:39:00 PM PDT 24
Finished Mar 10 12:40:13 PM PDT 24
Peak memory 261444 kb
Host smart-46133068-9918-4ed2-ac91-2ef17accbb2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245036673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.3245036673
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.1192584359
Short name T420
Test name
Test status
Simulation time 1550845900 ps
CPU time 202.17 seconds
Started Mar 10 12:39:09 PM PDT 24
Finished Mar 10 12:42:31 PM PDT 24
Peak memory 293528 kb
Host smart-5ea3181f-efa6-4c62-a332-b991dae4f21c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192584359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.1192584359
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.3611447562
Short name T72
Test name
Test status
Simulation time 45043500 ps
CPU time 131.17 seconds
Started Mar 10 12:38:59 PM PDT 24
Finished Mar 10 12:41:10 PM PDT 24
Peak memory 259060 kb
Host smart-d8f180a5-2e5d-4d34-8afe-810cc5a1ea7f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611447562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.3611447562
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.1007666941
Short name T385
Test name
Test status
Simulation time 97162000 ps
CPU time 33.16 seconds
Started Mar 10 12:39:09 PM PDT 24
Finished Mar 10 12:39:42 PM PDT 24
Peak memory 274152 kb
Host smart-2b9938a6-0d9c-4964-8b8c-37919907c7f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007666941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.1007666941
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.1639167987
Short name T304
Test name
Test status
Simulation time 31845600 ps
CPU time 31.02 seconds
Started Mar 10 12:39:05 PM PDT 24
Finished Mar 10 12:39:37 PM PDT 24
Peak memory 275364 kb
Host smart-2b94d16a-1908-400b-8e12-e1a70ed3158e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639167987 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.1639167987
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.1856353641
Short name T363
Test name
Test status
Simulation time 2695068600 ps
CPU time 61.58 seconds
Started Mar 10 12:39:07 PM PDT 24
Finished Mar 10 12:40:08 PM PDT 24
Peak memory 262836 kb
Host smart-eec4ee52-4ca3-402f-a6b1-560c5e69d623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856353641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1856353641
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.1478863468
Short name T433
Test name
Test status
Simulation time 23878600 ps
CPU time 76.24 seconds
Started Mar 10 12:39:00 PM PDT 24
Finished Mar 10 12:40:17 PM PDT 24
Peak memory 274008 kb
Host smart-fa965b09-f5df-4c05-a568-d40736603289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478863468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1478863468
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.1645183039
Short name T1072
Test name
Test status
Simulation time 96629700 ps
CPU time 13.79 seconds
Started Mar 10 12:35:44 PM PDT 24
Finished Mar 10 12:35:58 PM PDT 24
Peak memory 264340 kb
Host smart-6e8e8a73-3325-4779-b3b6-b37341262a6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645183039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.1
645183039
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.1730469401
Short name T758
Test name
Test status
Simulation time 39431100 ps
CPU time 13.62 seconds
Started Mar 10 12:35:48 PM PDT 24
Finished Mar 10 12:36:02 PM PDT 24
Peak memory 264700 kb
Host smart-cb1752de-8862-423f-9591-9406ad7aa254
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730469401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.1730469401
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.3683061059
Short name T660
Test name
Test status
Simulation time 25116400 ps
CPU time 15.51 seconds
Started Mar 10 12:35:49 PM PDT 24
Finished Mar 10 12:36:05 PM PDT 24
Peak memory 274300 kb
Host smart-fdaf3628-d6cf-461f-a6ec-38028027bcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683061059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3683061059
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.74100198
Short name T1120
Test name
Test status
Simulation time 285727900 ps
CPU time 105.64 seconds
Started Mar 10 12:35:42 PM PDT 24
Finished Mar 10 12:37:28 PM PDT 24
Peak memory 280688 kb
Host smart-bf5e96f5-b68f-4dac-b95c-0446f204fc9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74100198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_derr_detect.74100198
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.3855128152
Short name T346
Test name
Test status
Simulation time 23385800 ps
CPU time 20.72 seconds
Started Mar 10 12:35:40 PM PDT 24
Finished Mar 10 12:36:01 PM PDT 24
Peak memory 272928 kb
Host smart-27e9f18c-2064-4562-8605-8f68fd6f8a24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855128152 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.3855128152
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.2874974700
Short name T1039
Test name
Test status
Simulation time 33452734200 ps
CPU time 2385.43 seconds
Started Mar 10 12:35:46 PM PDT 24
Finished Mar 10 01:15:32 PM PDT 24
Peak memory 263856 kb
Host smart-47c8a40b-f31c-4cee-bed8-0de416c2370a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874974700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.2874974700
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.322781196
Short name T169
Test name
Test status
Simulation time 862211700 ps
CPU time 2615.18 seconds
Started Mar 10 12:35:40 PM PDT 24
Finished Mar 10 01:19:16 PM PDT 24
Peak memory 264376 kb
Host smart-84cf397c-c67b-4069-8d63-878c8b280bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322781196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.322781196
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.753866702
Short name T73
Test name
Test status
Simulation time 1186177700 ps
CPU time 794.31 seconds
Started Mar 10 12:35:41 PM PDT 24
Finished Mar 10 12:48:55 PM PDT 24
Peak memory 264712 kb
Host smart-d504d9d7-e753-49a4-a23b-2058e3085a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753866702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.753866702
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.2219934389
Short name T1089
Test name
Test status
Simulation time 137631400 ps
CPU time 24.28 seconds
Started Mar 10 12:35:38 PM PDT 24
Finished Mar 10 12:36:05 PM PDT 24
Peak memory 264612 kb
Host smart-efd33114-8584-4fcb-8cc8-024c532fb266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219934389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.2219934389
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.3799374977
Short name T1012
Test name
Test status
Simulation time 525941300 ps
CPU time 33.1 seconds
Started Mar 10 12:35:44 PM PDT 24
Finished Mar 10 12:36:17 PM PDT 24
Peak memory 275540 kb
Host smart-81771644-a18a-46ad-867c-82402acafdbf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799374977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.3799374977
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.2552179479
Short name T87
Test name
Test status
Simulation time 49893728600 ps
CPU time 4512.9 seconds
Started Mar 10 12:35:39 PM PDT 24
Finished Mar 10 01:50:54 PM PDT 24
Peak memory 264472 kb
Host smart-6fa72c2f-a88c-40bf-8836-d3ce17aa8309
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552179479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.2552179479
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.3019314422
Short name T153
Test name
Test status
Simulation time 365842540200 ps
CPU time 2036.94 seconds
Started Mar 10 12:35:38 PM PDT 24
Finished Mar 10 01:09:37 PM PDT 24
Peak memory 264236 kb
Host smart-0c1174cc-b454-4257-8569-e70c8c909d5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019314422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.3019314422
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.426883580
Short name T671
Test name
Test status
Simulation time 124854200 ps
CPU time 59.49 seconds
Started Mar 10 12:35:29 PM PDT 24
Finished Mar 10 12:36:29 PM PDT 24
Peak memory 264532 kb
Host smart-fdf2feb5-a64f-4b1b-b658-ed6ebd44de0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426883580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.426883580
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.286783086
Short name T934
Test name
Test status
Simulation time 10012148300 ps
CPU time 111.9 seconds
Started Mar 10 12:35:44 PM PDT 24
Finished Mar 10 12:37:36 PM PDT 24
Peak memory 312140 kb
Host smart-2cd2ad3b-f58f-4edd-8202-768e7f77c9d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286783086 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.286783086
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.2225769869
Short name T805
Test name
Test status
Simulation time 15746400 ps
CPU time 13.26 seconds
Started Mar 10 12:35:46 PM PDT 24
Finished Mar 10 12:36:00 PM PDT 24
Peak memory 264752 kb
Host smart-25da2acd-b1f7-4dbf-96e6-b5e2b60b7165
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225769869 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.2225769869
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.3334244727
Short name T561
Test name
Test status
Simulation time 40125796500 ps
CPU time 749.87 seconds
Started Mar 10 12:35:34 PM PDT 24
Finished Mar 10 12:48:05 PM PDT 24
Peak memory 258576 kb
Host smart-0c5411c7-969b-4ef6-86a7-4b01151754a8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334244727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.3334244727
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.1680544010
Short name T798
Test name
Test status
Simulation time 924975900 ps
CPU time 38.39 seconds
Started Mar 10 12:35:41 PM PDT 24
Finished Mar 10 12:36:20 PM PDT 24
Peak memory 258508 kb
Host smart-78de4095-9dcb-4e46-a22a-8b1ed31c401c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680544010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.1680544010
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.3788014143
Short name T32
Test name
Test status
Simulation time 1317017500 ps
CPU time 152.14 seconds
Started Mar 10 12:35:47 PM PDT 24
Finished Mar 10 12:38:19 PM PDT 24
Peak memory 289440 kb
Host smart-86bc8732-5dab-48f4-9369-beaa23f672c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788014143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.3788014143
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1423500431
Short name T327
Test name
Test status
Simulation time 16127356000 ps
CPU time 301.8 seconds
Started Mar 10 12:35:45 PM PDT 24
Finished Mar 10 12:40:47 PM PDT 24
Peak memory 283880 kb
Host smart-d73cf853-d044-4116-b7f3-e8e826a8bfe6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423500431 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.1423500431
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.588588346
Short name T29
Test name
Test status
Simulation time 4616786300 ps
CPU time 94.24 seconds
Started Mar 10 12:35:40 PM PDT 24
Finished Mar 10 12:37:15 PM PDT 24
Peak memory 264756 kb
Host smart-fbe5286d-e0ee-4b78-aed6-9e2b8906b1eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588588346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_intr_wr.588588346
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3175904908
Short name T769
Test name
Test status
Simulation time 168423995600 ps
CPU time 288.94 seconds
Started Mar 10 12:35:44 PM PDT 24
Finished Mar 10 12:40:33 PM PDT 24
Peak memory 264660 kb
Host smart-504f8ed5-25df-47bb-9f3e-377d735a3dc5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317
5904908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3175904908
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.370144457
Short name T648
Test name
Test status
Simulation time 7717959400 ps
CPU time 63.88 seconds
Started Mar 10 12:35:32 PM PDT 24
Finished Mar 10 12:36:36 PM PDT 24
Peak memory 259800 kb
Host smart-16f88cce-1c8c-467a-95cb-77689be0e2c6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370144457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.370144457
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.1194618838
Short name T770
Test name
Test status
Simulation time 78300500 ps
CPU time 13.28 seconds
Started Mar 10 12:35:45 PM PDT 24
Finished Mar 10 12:35:59 PM PDT 24
Peak memory 264632 kb
Host smart-c2d10ccb-dde9-4b9d-8a92-e4fc88955065
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194618838 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.1194618838
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.3884361835
Short name T117
Test name
Test status
Simulation time 3287016100 ps
CPU time 69.27 seconds
Started Mar 10 12:35:35 PM PDT 24
Finished Mar 10 12:36:44 PM PDT 24
Peak memory 259112 kb
Host smart-1034a042-de01-48a9-b8c3-82df8ea6d165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884361835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.3884361835
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.2587754933
Short name T86
Test name
Test status
Simulation time 14342131800 ps
CPU time 268.56 seconds
Started Mar 10 12:35:33 PM PDT 24
Finished Mar 10 12:40:03 PM PDT 24
Peak memory 272768 kb
Host smart-abe96bcc-3c48-47f1-82ae-b1a6abb645e4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587754933 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.2587754933
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.2449984604
Short name T750
Test name
Test status
Simulation time 40298000 ps
CPU time 134.12 seconds
Started Mar 10 12:35:42 PM PDT 24
Finished Mar 10 12:37:56 PM PDT 24
Peak memory 259212 kb
Host smart-8dfeccc9-3b6e-4648-be3c-471f6224aee8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449984604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.2449984604
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.3841346991
Short name T530
Test name
Test status
Simulation time 1002346300 ps
CPU time 146.37 seconds
Started Mar 10 12:35:41 PM PDT 24
Finished Mar 10 12:38:07 PM PDT 24
Peak memory 281156 kb
Host smart-45598097-eb91-4f68-aa1a-121bcc6e621e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841346991 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.3841346991
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2767674283
Short name T224
Test name
Test status
Simulation time 57001600 ps
CPU time 13.6 seconds
Started Mar 10 12:35:51 PM PDT 24
Finished Mar 10 12:36:05 PM PDT 24
Peak memory 264888 kb
Host smart-cbff5dca-11d6-4ccb-9b94-7f200d6336e2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2767674283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2767674283
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.2291225832
Short name T949
Test name
Test status
Simulation time 1488546100 ps
CPU time 341.47 seconds
Started Mar 10 12:35:42 PM PDT 24
Finished Mar 10 12:41:24 PM PDT 24
Peak memory 264572 kb
Host smart-cbee6c07-46ee-4bf5-8faf-c57f4848426c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291225832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.2291225832
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.3753043235
Short name T1059
Test name
Test status
Simulation time 848047400 ps
CPU time 39.73 seconds
Started Mar 10 12:35:49 PM PDT 24
Finished Mar 10 12:36:28 PM PDT 24
Peak memory 264820 kb
Host smart-0a019882-e2bc-4cc5-88a0-4689ac3f49ed
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753043235 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.3753043235
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.3154061902
Short name T53
Test name
Test status
Simulation time 99267500 ps
CPU time 14.1 seconds
Started Mar 10 12:35:50 PM PDT 24
Finished Mar 10 12:36:04 PM PDT 24
Peak memory 264876 kb
Host smart-6a2817df-9356-44c9-9286-c60b7741da07
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154061902 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.3154061902
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.1392360352
Short name T701
Test name
Test status
Simulation time 631378600 ps
CPU time 18.93 seconds
Started Mar 10 12:35:49 PM PDT 24
Finished Mar 10 12:36:08 PM PDT 24
Peak memory 264648 kb
Host smart-ae4e621d-7410-462b-be90-bddbd8f4202b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392360352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.1392360352
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.1056119847
Short name T943
Test name
Test status
Simulation time 160234400 ps
CPU time 254.21 seconds
Started Mar 10 12:35:32 PM PDT 24
Finished Mar 10 12:39:46 PM PDT 24
Peak memory 277692 kb
Host smart-d497a433-d69d-473d-b183-54ed3849a37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056119847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.1056119847
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2134502169
Short name T1005
Test name
Test status
Simulation time 2934476400 ps
CPU time 110.94 seconds
Started Mar 10 12:35:36 PM PDT 24
Finished Mar 10 12:37:27 PM PDT 24
Peak memory 264648 kb
Host smart-e445c529-89e0-42df-9956-6ebcd729e33b
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2134502169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2134502169
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.4191814931
Short name T548
Test name
Test status
Simulation time 228737800 ps
CPU time 37.82 seconds
Started Mar 10 12:35:44 PM PDT 24
Finished Mar 10 12:36:22 PM PDT 24
Peak memory 265956 kb
Host smart-e9940209-34ab-47ea-8912-6099eb240773
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191814931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.4191814931
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.2508794498
Short name T192
Test name
Test status
Simulation time 32552500 ps
CPU time 22.48 seconds
Started Mar 10 12:35:50 PM PDT 24
Finished Mar 10 12:36:13 PM PDT 24
Peak memory 264892 kb
Host smart-d4d4dbec-90c7-4657-a7f4-06174083064e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508794498 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.2508794498
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.1132982197
Short name T243
Test name
Test status
Simulation time 47255100 ps
CPU time 22.45 seconds
Started Mar 10 12:35:39 PM PDT 24
Finished Mar 10 12:36:03 PM PDT 24
Peak memory 264712 kb
Host smart-0c1e623b-10a2-4ea1-96d6-837ee61b0c0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132982197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.1132982197
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.1717484415
Short name T210
Test name
Test status
Simulation time 1761803600 ps
CPU time 87.59 seconds
Started Mar 10 12:35:34 PM PDT 24
Finished Mar 10 12:37:02 PM PDT 24
Peak memory 281096 kb
Host smart-5c9e95ea-3051-412e-887a-b62f0f6d87f2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717484415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_ro.1717484415
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.937647918
Short name T191
Test name
Test status
Simulation time 580626500 ps
CPU time 112.45 seconds
Started Mar 10 12:35:47 PM PDT 24
Finished Mar 10 12:37:40 PM PDT 24
Peak memory 281132 kb
Host smart-76a8db1c-d16f-4009-8c04-1d2b95ad9174
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
937647918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.937647918
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.205330077
Short name T559
Test name
Test status
Simulation time 2096735700 ps
CPU time 113.57 seconds
Started Mar 10 12:35:39 PM PDT 24
Finished Mar 10 12:37:34 PM PDT 24
Peak memory 281276 kb
Host smart-8c3d8d0d-4d79-49e4-9bb4-e6cac6504cfa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205330077 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.205330077
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.910220726
Short name T1081
Test name
Test status
Simulation time 9040923900 ps
CPU time 499.74 seconds
Started Mar 10 12:35:35 PM PDT 24
Finished Mar 10 12:43:55 PM PDT 24
Peak memory 308680 kb
Host smart-e64f56ee-62a9-4bdd-b5b6-5d4281812bec
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910220726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctr
l_rw.910220726
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.3253045668
Short name T693
Test name
Test status
Simulation time 3081175300 ps
CPU time 568.87 seconds
Started Mar 10 12:35:39 PM PDT 24
Finished Mar 10 12:45:09 PM PDT 24
Peak memory 327748 kb
Host smart-62c0eb5d-6e00-44e6-942d-f03661aae61a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253045668 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_rw_derr.3253045668
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.739189964
Short name T1094
Test name
Test status
Simulation time 186442100 ps
CPU time 30.83 seconds
Started Mar 10 12:35:41 PM PDT 24
Finished Mar 10 12:36:12 PM PDT 24
Peak memory 271932 kb
Host smart-d5732568-422d-4d49-aac5-39d8288a578a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739189964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_rw_evict.739189964
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.1961569213
Short name T318
Test name
Test status
Simulation time 30356700 ps
CPU time 28.04 seconds
Started Mar 10 12:35:46 PM PDT 24
Finished Mar 10 12:36:14 PM PDT 24
Peak memory 274016 kb
Host smart-838946f1-6ef2-4c9b-afa5-b58bbb9efcc3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961569213 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.1961569213
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.380586816
Short name T948
Test name
Test status
Simulation time 2430566200 ps
CPU time 459.12 seconds
Started Mar 10 12:35:36 PM PDT 24
Finished Mar 10 12:43:15 PM PDT 24
Peak memory 311708 kb
Host smart-18f37c29-1cdd-4abe-9294-f59e5b3360e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380586816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_se
rr.380586816
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.2212016560
Short name T38
Test name
Test status
Simulation time 8633313000 ps
CPU time 4685.79 seconds
Started Mar 10 12:35:48 PM PDT 24
Finished Mar 10 01:53:54 PM PDT 24
Peak memory 285836 kb
Host smart-640bb393-2fe5-44a2-b14e-de715808c96f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212016560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.2212016560
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.894762743
Short name T372
Test name
Test status
Simulation time 1696787700 ps
CPU time 74.85 seconds
Started Mar 10 12:35:48 PM PDT 24
Finished Mar 10 12:37:03 PM PDT 24
Peak memory 263704 kb
Host smart-125c222f-6f02-4436-b048-813d4f4c5f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894762743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.894762743
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.2803794875
Short name T273
Test name
Test status
Simulation time 466284100 ps
CPU time 52.6 seconds
Started Mar 10 12:35:43 PM PDT 24
Finished Mar 10 12:36:36 PM PDT 24
Peak memory 264852 kb
Host smart-eba1da34-c5d2-484e-99a6-1f6c5b159ec1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803794875 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.2803794875
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.3694826729
Short name T772
Test name
Test status
Simulation time 1822447600 ps
CPU time 78.26 seconds
Started Mar 10 12:35:40 PM PDT 24
Finished Mar 10 12:36:59 PM PDT 24
Peak memory 264828 kb
Host smart-f36e366d-e53b-49da-8ef6-b9eb64b99921
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694826729 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.3694826729
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.2302293794
Short name T942
Test name
Test status
Simulation time 110235300 ps
CPU time 98.26 seconds
Started Mar 10 12:35:30 PM PDT 24
Finished Mar 10 12:37:09 PM PDT 24
Peak memory 274468 kb
Host smart-8a482765-7310-4c34-9b1d-98755525052a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302293794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.2302293794
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.86190062
Short name T773
Test name
Test status
Simulation time 51658600 ps
CPU time 26.01 seconds
Started Mar 10 12:35:43 PM PDT 24
Finished Mar 10 12:36:09 PM PDT 24
Peak memory 258432 kb
Host smart-e4e115d5-fd43-4616-81c8-dc80f8de2cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86190062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.86190062
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.623143907
Short name T430
Test name
Test status
Simulation time 590537500 ps
CPU time 450.57 seconds
Started Mar 10 12:35:49 PM PDT 24
Finished Mar 10 12:43:20 PM PDT 24
Peak memory 276180 kb
Host smart-07a7603b-37f1-4f66-95d6-a8d2bf055874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623143907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress
_all.623143907
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.3652116618
Short name T441
Test name
Test status
Simulation time 91257600 ps
CPU time 26.56 seconds
Started Mar 10 12:35:39 PM PDT 24
Finished Mar 10 12:36:07 PM PDT 24
Peak memory 258784 kb
Host smart-f34fb96d-fc07-49f6-8afd-c417ee68fe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652116618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.3652116618
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.543825820
Short name T419
Test name
Test status
Simulation time 2308181200 ps
CPU time 188.86 seconds
Started Mar 10 12:35:34 PM PDT 24
Finished Mar 10 12:38:44 PM PDT 24
Peak memory 264840 kb
Host smart-2645857a-29aa-49da-a982-ad098436d345
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543825820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_wo.543825820
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.1609750211
Short name T939
Test name
Test status
Simulation time 108431300 ps
CPU time 14.12 seconds
Started Mar 10 12:39:13 PM PDT 24
Finished Mar 10 12:39:28 PM PDT 24
Peak memory 264328 kb
Host smart-6eaed73a-21f0-4bf0-b9da-c66f03051b5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609750211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
1609750211
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.2947524937
Short name T951
Test name
Test status
Simulation time 27760400 ps
CPU time 15.83 seconds
Started Mar 10 12:39:08 PM PDT 24
Finished Mar 10 12:39:24 PM PDT 24
Peak memory 274068 kb
Host smart-be8c3563-1449-4e99-90bb-f82c5042e4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947524937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.2947524937
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.3442667320
Short name T356
Test name
Test status
Simulation time 10637500 ps
CPU time 21.47 seconds
Started Mar 10 12:39:09 PM PDT 24
Finished Mar 10 12:39:31 PM PDT 24
Peak memory 273128 kb
Host smart-facf1ac6-9ebb-4a00-8ad4-bc87cdacdf76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442667320 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.3442667320
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.1548958910
Short name T46
Test name
Test status
Simulation time 2707742000 ps
CPU time 82.42 seconds
Started Mar 10 12:39:05 PM PDT 24
Finished Mar 10 12:40:28 PM PDT 24
Peak memory 258556 kb
Host smart-791f9daa-30b2-44d2-b08b-078239a93533
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548958910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.1548958910
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.2016676042
Short name T148
Test name
Test status
Simulation time 42525600 ps
CPU time 112.62 seconds
Started Mar 10 12:39:09 PM PDT 24
Finished Mar 10 12:41:02 PM PDT 24
Peak memory 259124 kb
Host smart-8405a373-d2c1-4b93-8dfe-35b9686a075e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016676042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.2016676042
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.3709117014
Short name T904
Test name
Test status
Simulation time 3099124000 ps
CPU time 59.38 seconds
Started Mar 10 12:39:09 PM PDT 24
Finished Mar 10 12:40:09 PM PDT 24
Peak memory 264560 kb
Host smart-05c1dbc9-f56d-4a0e-81af-5ca1e4233c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709117014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.3709117014
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.3262127005
Short name T704
Test name
Test status
Simulation time 49662400 ps
CPU time 52.02 seconds
Started Mar 10 12:39:06 PM PDT 24
Finished Mar 10 12:39:59 PM PDT 24
Peak memory 269940 kb
Host smart-2290fdf2-15fd-43db-9df8-ea2a82f78ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262127005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.3262127005
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.2282004185
Short name T572
Test name
Test status
Simulation time 32084200 ps
CPU time 13.75 seconds
Started Mar 10 12:39:09 PM PDT 24
Finished Mar 10 12:39:23 PM PDT 24
Peak memory 264412 kb
Host smart-fcde04b4-b606-4975-8b20-8c8a443fcb71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282004185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
2282004185
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.1418776105
Short name T865
Test name
Test status
Simulation time 16742000 ps
CPU time 13.66 seconds
Started Mar 10 12:39:06 PM PDT 24
Finished Mar 10 12:39:20 PM PDT 24
Peak memory 273880 kb
Host smart-956f7d77-efbb-4ab5-9e91-dbc9229ceff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418776105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.1418776105
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.391436470
Short name T156
Test name
Test status
Simulation time 39188400 ps
CPU time 20.72 seconds
Started Mar 10 12:39:08 PM PDT 24
Finished Mar 10 12:39:29 PM PDT 24
Peak memory 264128 kb
Host smart-4b3f9b15-fcc4-451c-8a14-18f686fc8a2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391436470 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.391436470
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.372480685
Short name T866
Test name
Test status
Simulation time 6972597200 ps
CPU time 77.98 seconds
Started Mar 10 12:39:09 PM PDT 24
Finished Mar 10 12:40:27 PM PDT 24
Peak memory 258428 kb
Host smart-481ffdd5-efe3-4124-8bd2-e20b5d216f56
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372480685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_h
w_sec_otp.372480685
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.155313818
Short name T754
Test name
Test status
Simulation time 94699500 ps
CPU time 130.93 seconds
Started Mar 10 12:39:06 PM PDT 24
Finished Mar 10 12:41:18 PM PDT 24
Peak memory 259240 kb
Host smart-03472c8f-870e-4f29-a160-ae7bbb9bf42f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155313818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ot
p_reset.155313818
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.2196058000
Short name T506
Test name
Test status
Simulation time 8150242200 ps
CPU time 95.3 seconds
Started Mar 10 12:39:12 PM PDT 24
Finished Mar 10 12:40:48 PM PDT 24
Peak memory 263656 kb
Host smart-1b5a7f7e-89dd-442b-af29-a4d3b0417503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196058000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2196058000
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.654358028
Short name T990
Test name
Test status
Simulation time 28455500 ps
CPU time 191.79 seconds
Started Mar 10 12:39:07 PM PDT 24
Finished Mar 10 12:42:19 PM PDT 24
Peak memory 279884 kb
Host smart-75e01e6e-d648-435e-88ef-2fa4155d1e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654358028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.654358028
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.3363579684
Short name T399
Test name
Test status
Simulation time 128050900 ps
CPU time 13.73 seconds
Started Mar 10 12:39:07 PM PDT 24
Finished Mar 10 12:39:21 PM PDT 24
Peak memory 264336 kb
Host smart-be70d43c-bbcf-4620-a727-ea70fa081893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363579684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
3363579684
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.737249394
Short name T1107
Test name
Test status
Simulation time 29791700 ps
CPU time 13.33 seconds
Started Mar 10 12:39:06 PM PDT 24
Finished Mar 10 12:39:19 PM PDT 24
Peak memory 274004 kb
Host smart-c73d19ee-030d-40e2-aa3c-fbd343f30cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737249394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.737249394
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.1893407675
Short name T663
Test name
Test status
Simulation time 12706400 ps
CPU time 21.74 seconds
Started Mar 10 12:39:09 PM PDT 24
Finished Mar 10 12:39:31 PM PDT 24
Peak memory 273020 kb
Host smart-37e6a0d2-ea36-4ca1-8b12-c069b26673a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893407675 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.1893407675
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.1578786046
Short name T312
Test name
Test status
Simulation time 16452462000 ps
CPU time 92.21 seconds
Started Mar 10 12:39:09 PM PDT 24
Finished Mar 10 12:40:42 PM PDT 24
Peak memory 258580 kb
Host smart-38554793-0521-4346-9957-dedb4b8a57de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578786046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.1578786046
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.1306701280
Short name T745
Test name
Test status
Simulation time 59287900 ps
CPU time 110.45 seconds
Started Mar 10 12:39:08 PM PDT 24
Finished Mar 10 12:40:59 PM PDT 24
Peak memory 259228 kb
Host smart-9f0356bd-10cb-4294-97bd-04d4a14b6a4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306701280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.1306701280
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.2189990652
Short name T369
Test name
Test status
Simulation time 5903928400 ps
CPU time 66.46 seconds
Started Mar 10 12:39:05 PM PDT 24
Finished Mar 10 12:40:12 PM PDT 24
Peak memory 261720 kb
Host smart-df838f72-8069-49f0-8351-e1efc0e6a56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189990652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2189990652
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.4207561827
Short name T400
Test name
Test status
Simulation time 130803700 ps
CPU time 169.26 seconds
Started Mar 10 12:39:05 PM PDT 24
Finished Mar 10 12:41:55 PM PDT 24
Peak memory 275848 kb
Host smart-d38cf424-3a69-458f-bd21-ff94ee22f0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207561827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.4207561827
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.1645165613
Short name T410
Test name
Test status
Simulation time 35036600 ps
CPU time 13.59 seconds
Started Mar 10 12:39:13 PM PDT 24
Finished Mar 10 12:39:27 PM PDT 24
Peak memory 264096 kb
Host smart-d5a284bc-218e-47ca-9710-fdbd5d8dd5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645165613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
1645165613
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.3224539381
Short name T1099
Test name
Test status
Simulation time 53125300 ps
CPU time 13.26 seconds
Started Mar 10 12:39:14 PM PDT 24
Finished Mar 10 12:39:28 PM PDT 24
Peak memory 274036 kb
Host smart-ccf93472-2aa9-4003-96c9-4ad791571a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224539381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3224539381
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.344981990
Short name T675
Test name
Test status
Simulation time 17684900 ps
CPU time 21.77 seconds
Started Mar 10 12:39:11 PM PDT 24
Finished Mar 10 12:39:33 PM PDT 24
Peak memory 280088 kb
Host smart-cee054e4-2c26-47dc-ae07-4bb8df945fdc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344981990 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.344981990
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.1018566704
Short name T500
Test name
Test status
Simulation time 4079821200 ps
CPU time 127.81 seconds
Started Mar 10 12:39:06 PM PDT 24
Finished Mar 10 12:41:14 PM PDT 24
Peak memory 258468 kb
Host smart-59c88461-f150-4901-bf78-28cdc2ffb886
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018566704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.1018566704
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.792631187
Short name T547
Test name
Test status
Simulation time 243082700 ps
CPU time 110.39 seconds
Started Mar 10 12:39:06 PM PDT 24
Finished Mar 10 12:40:57 PM PDT 24
Peak memory 259140 kb
Host smart-55c81ad1-a943-4a97-8722-4872f186fc8b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792631187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_ot
p_reset.792631187
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.2979650932
Short name T601
Test name
Test status
Simulation time 1218837900 ps
CPU time 65.45 seconds
Started Mar 10 12:39:13 PM PDT 24
Finished Mar 10 12:40:19 PM PDT 24
Peak memory 258776 kb
Host smart-30cac26b-52b2-4467-8c49-9cb867c6c22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979650932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.2979650932
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.361371744
Short name T709
Test name
Test status
Simulation time 41720200 ps
CPU time 95.05 seconds
Started Mar 10 12:39:09 PM PDT 24
Finished Mar 10 12:40:44 PM PDT 24
Peak memory 274748 kb
Host smart-cb2dc0f5-20ae-4d35-8b0f-4406e635911c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361371744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.361371744
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.793599413
Short name T413
Test name
Test status
Simulation time 100063300 ps
CPU time 14.38 seconds
Started Mar 10 12:39:13 PM PDT 24
Finished Mar 10 12:39:28 PM PDT 24
Peak memory 264156 kb
Host smart-52c40b14-3f5d-45c9-a7b2-894e6547ad56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793599413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.793599413
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.2268698950
Short name T908
Test name
Test status
Simulation time 29327800 ps
CPU time 15.69 seconds
Started Mar 10 12:39:13 PM PDT 24
Finished Mar 10 12:39:29 PM PDT 24
Peak memory 273848 kb
Host smart-2d322da9-8a7e-4a58-a652-3cd4bd0ef37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268698950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2268698950
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.328009511
Short name T1069
Test name
Test status
Simulation time 42042400 ps
CPU time 22.01 seconds
Started Mar 10 12:39:14 PM PDT 24
Finished Mar 10 12:39:38 PM PDT 24
Peak memory 264876 kb
Host smart-644b812f-1cb9-4059-9ce6-38cf0d1e4868
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328009511 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.328009511
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.3058304902
Short name T534
Test name
Test status
Simulation time 3860189200 ps
CPU time 84.68 seconds
Started Mar 10 12:39:10 PM PDT 24
Finished Mar 10 12:40:35 PM PDT 24
Peak memory 261344 kb
Host smart-51f10a7c-166f-4958-9d5e-6d61b9a0f058
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058304902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.3058304902
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.132048090
Short name T797
Test name
Test status
Simulation time 161035900 ps
CPU time 132.04 seconds
Started Mar 10 12:39:13 PM PDT 24
Finished Mar 10 12:41:26 PM PDT 24
Peak memory 259316 kb
Host smart-525f34d4-bc84-4fe6-abe2-3069b492608d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132048090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ot
p_reset.132048090
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.251664476
Short name T1054
Test name
Test status
Simulation time 8984064700 ps
CPU time 73.47 seconds
Started Mar 10 12:39:11 PM PDT 24
Finished Mar 10 12:40:24 PM PDT 24
Peak memory 263540 kb
Host smart-f62822bb-9b2e-45d9-a2da-af2c7e2ca2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251664476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.251664476
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.1478561251
Short name T697
Test name
Test status
Simulation time 27504600 ps
CPU time 148.25 seconds
Started Mar 10 12:39:14 PM PDT 24
Finished Mar 10 12:41:42 PM PDT 24
Peak memory 277212 kb
Host smart-787255c6-d1ec-48c0-a3f0-d5a98b1caa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478561251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.1478561251
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.394019638
Short name T873
Test name
Test status
Simulation time 61760000 ps
CPU time 13.49 seconds
Started Mar 10 12:39:18 PM PDT 24
Finished Mar 10 12:39:32 PM PDT 24
Peak memory 263812 kb
Host smart-528b8fa4-c71d-4e23-b2df-c4fae35d80f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394019638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.394019638
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.3917733156
Short name T627
Test name
Test status
Simulation time 56709000 ps
CPU time 15.74 seconds
Started Mar 10 12:39:18 PM PDT 24
Finished Mar 10 12:39:34 PM PDT 24
Peak memory 274784 kb
Host smart-054ed75a-9560-4479-ae46-93d2fd446fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917733156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.3917733156
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.999916781
Short name T1046
Test name
Test status
Simulation time 16487000 ps
CPU time 21.9 seconds
Started Mar 10 12:39:13 PM PDT 24
Finished Mar 10 12:39:35 PM PDT 24
Peak memory 264944 kb
Host smart-caa012b2-1043-43f6-b29a-5abc9b8dc072
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999916781 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.999916781
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.4219416433
Short name T1076
Test name
Test status
Simulation time 1005146400 ps
CPU time 82.58 seconds
Started Mar 10 12:39:13 PM PDT 24
Finished Mar 10 12:40:36 PM PDT 24
Peak memory 261628 kb
Host smart-3c87a835-b7eb-4158-a8af-5256ad3999a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219416433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.4219416433
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.2950525268
Short name T135
Test name
Test status
Simulation time 39737400 ps
CPU time 137.57 seconds
Started Mar 10 12:39:12 PM PDT 24
Finished Mar 10 12:41:31 PM PDT 24
Peak memory 262916 kb
Host smart-faed3a21-57aa-4b82-a016-0ce19cef61b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950525268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.2950525268
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.2749263011
Short name T921
Test name
Test status
Simulation time 3404807200 ps
CPU time 70.39 seconds
Started Mar 10 12:39:14 PM PDT 24
Finished Mar 10 12:40:24 PM PDT 24
Peak memory 258884 kb
Host smart-f1cdfed8-6edf-4542-8368-885c8c7303ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749263011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.2749263011
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.65333068
Short name T409
Test name
Test status
Simulation time 23190300 ps
CPU time 51.77 seconds
Started Mar 10 12:39:11 PM PDT 24
Finished Mar 10 12:40:04 PM PDT 24
Peak memory 269848 kb
Host smart-ca688008-7dac-4b2f-8d00-2ccaef427a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65333068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.65333068
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.3184475304
Short name T1049
Test name
Test status
Simulation time 75195700 ps
CPU time 13.75 seconds
Started Mar 10 12:39:18 PM PDT 24
Finished Mar 10 12:39:32 PM PDT 24
Peak memory 264700 kb
Host smart-9c1c57a7-8cca-47d6-b9a9-be380fcaf387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184475304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
3184475304
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.1345063965
Short name T702
Test name
Test status
Simulation time 73249100 ps
CPU time 15.42 seconds
Started Mar 10 12:39:29 PM PDT 24
Finished Mar 10 12:39:48 PM PDT 24
Peak memory 274776 kb
Host smart-f4d3bb36-3bc6-49ab-8dc7-9b6c16072a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345063965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.1345063965
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.3887004306
Short name T360
Test name
Test status
Simulation time 35867500 ps
CPU time 20.39 seconds
Started Mar 10 12:39:28 PM PDT 24
Finished Mar 10 12:39:48 PM PDT 24
Peak memory 273032 kb
Host smart-fce2c055-05ef-4685-9bc6-ff1fd1f70f8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887004306 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.3887004306
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.229109641
Short name T1106
Test name
Test status
Simulation time 392677100 ps
CPU time 133.84 seconds
Started Mar 10 12:39:17 PM PDT 24
Finished Mar 10 12:41:32 PM PDT 24
Peak memory 259064 kb
Host smart-942b5136-89de-43d1-854d-49d527e1c9ff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229109641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ot
p_reset.229109641
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.2660056356
Short name T737
Test name
Test status
Simulation time 2061264100 ps
CPU time 70.26 seconds
Started Mar 10 12:39:17 PM PDT 24
Finished Mar 10 12:40:28 PM PDT 24
Peak memory 262852 kb
Host smart-37f130c0-55f2-4337-9bcb-8394e8bdfa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660056356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.2660056356
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.3782636316
Short name T1091
Test name
Test status
Simulation time 166650400 ps
CPU time 220.32 seconds
Started Mar 10 12:39:21 PM PDT 24
Finished Mar 10 12:43:02 PM PDT 24
Peak memory 279232 kb
Host smart-44ee9e39-7009-4ad5-aea9-e5187ec15f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782636316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3782636316
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.601657939
Short name T1074
Test name
Test status
Simulation time 42178700 ps
CPU time 13.52 seconds
Started Mar 10 12:39:29 PM PDT 24
Finished Mar 10 12:39:46 PM PDT 24
Peak memory 264184 kb
Host smart-73e3e430-fbca-42bb-acc3-076c6c429344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601657939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.601657939
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.4288999562
Short name T429
Test name
Test status
Simulation time 42090900 ps
CPU time 15.81 seconds
Started Mar 10 12:39:18 PM PDT 24
Finished Mar 10 12:39:34 PM PDT 24
Peak memory 274780 kb
Host smart-5aec6e8d-3b2d-4f8b-9991-14e82b77f773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288999562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.4288999562
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.1896605896
Short name T220
Test name
Test status
Simulation time 11048600 ps
CPU time 21.56 seconds
Started Mar 10 12:39:28 PM PDT 24
Finished Mar 10 12:39:49 PM PDT 24
Peak memory 273028 kb
Host smart-4af185a3-27ab-4ac1-abd1-f61bc3b1dfc0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896605896 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.1896605896
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.2564144833
Short name T809
Test name
Test status
Simulation time 7588321800 ps
CPU time 78.79 seconds
Started Mar 10 12:39:18 PM PDT 24
Finished Mar 10 12:40:38 PM PDT 24
Peak memory 261680 kb
Host smart-423df4b6-5315-41bb-8bf2-34f9f1288b3b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564144833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.2564144833
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.919155027
Short name T923
Test name
Test status
Simulation time 38230700 ps
CPU time 136.07 seconds
Started Mar 10 12:39:29 PM PDT 24
Finished Mar 10 12:41:49 PM PDT 24
Peak memory 262232 kb
Host smart-85e4d67a-8992-4173-9391-8b6b58352d38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919155027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ot
p_reset.919155027
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.3686946849
Short name T764
Test name
Test status
Simulation time 117720500 ps
CPU time 125.5 seconds
Started Mar 10 12:39:29 PM PDT 24
Finished Mar 10 12:41:38 PM PDT 24
Peak memory 274912 kb
Host smart-593ae237-05bc-403e-8e2d-572a051b9ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686946849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3686946849
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.1974128004
Short name T458
Test name
Test status
Simulation time 113305100 ps
CPU time 13.75 seconds
Started Mar 10 12:39:23 PM PDT 24
Finished Mar 10 12:39:38 PM PDT 24
Peak memory 264176 kb
Host smart-c7961bff-841d-4d80-aa19-bce736c901ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974128004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
1974128004
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.3989673080
Short name T777
Test name
Test status
Simulation time 14653200 ps
CPU time 15.76 seconds
Started Mar 10 12:39:30 PM PDT 24
Finished Mar 10 12:39:49 PM PDT 24
Peak memory 273920 kb
Host smart-ba667b29-18c2-45fc-b679-f10c2e7a0d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989673080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3989673080
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.1715915020
Short name T823
Test name
Test status
Simulation time 135034900 ps
CPU time 20.79 seconds
Started Mar 10 12:39:24 PM PDT 24
Finished Mar 10 12:39:45 PM PDT 24
Peak memory 264832 kb
Host smart-4c59d7d9-8171-4038-aebd-49aec029dbb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715915020 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.1715915020
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.106615365
Short name T917
Test name
Test status
Simulation time 7128747500 ps
CPU time 161.29 seconds
Started Mar 10 12:39:18 PM PDT 24
Finished Mar 10 12:41:59 PM PDT 24
Peak memory 261360 kb
Host smart-95dc79c4-21af-4d38-98ef-ec1310d0fd06
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106615365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_h
w_sec_otp.106615365
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.3902505246
Short name T1093
Test name
Test status
Simulation time 74410100 ps
CPU time 136.74 seconds
Started Mar 10 12:39:15 PM PDT 24
Finished Mar 10 12:41:33 PM PDT 24
Peak memory 263016 kb
Host smart-b305c7f4-f97b-4dbb-b723-d5f226c29b6e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902505246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.3902505246
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.148356186
Short name T367
Test name
Test status
Simulation time 6300976200 ps
CPU time 70.48 seconds
Started Mar 10 12:39:30 PM PDT 24
Finished Mar 10 12:40:43 PM PDT 24
Peak memory 258884 kb
Host smart-8e307a8c-fc5c-4c99-bebf-05e320f54c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148356186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.148356186
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.4137812988
Short name T636
Test name
Test status
Simulation time 20836500 ps
CPU time 121.24 seconds
Started Mar 10 12:39:16 PM PDT 24
Finished Mar 10 12:41:19 PM PDT 24
Peak memory 274896 kb
Host smart-8daeb61e-31ee-4964-bd26-a4d94be50e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137812988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.4137812988
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.3186182361
Short name T397
Test name
Test status
Simulation time 168014300 ps
CPU time 13.83 seconds
Started Mar 10 12:39:26 PM PDT 24
Finished Mar 10 12:39:40 PM PDT 24
Peak memory 264248 kb
Host smart-aac611a2-87fc-4121-b5a5-735374298cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186182361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
3186182361
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.2074816626
Short name T789
Test name
Test status
Simulation time 14211400 ps
CPU time 13.33 seconds
Started Mar 10 12:39:22 PM PDT 24
Finished Mar 10 12:39:36 PM PDT 24
Peak memory 273708 kb
Host smart-9d9267a3-ef41-4bb5-bc89-9999bd47e3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074816626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2074816626
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.559185229
Short name T892
Test name
Test status
Simulation time 11125700 ps
CPU time 21.86 seconds
Started Mar 10 12:39:26 PM PDT 24
Finished Mar 10 12:39:48 PM PDT 24
Peak memory 280036 kb
Host smart-606fd537-5661-4bcb-a63d-65963d38548b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559185229 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.559185229
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.262858086
Short name T487
Test name
Test status
Simulation time 7705613200 ps
CPU time 115.35 seconds
Started Mar 10 12:39:24 PM PDT 24
Finished Mar 10 12:41:19 PM PDT 24
Peak memory 258420 kb
Host smart-f2c6327d-3ffe-4801-865c-d422f0f7ae7b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262858086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_h
w_sec_otp.262858086
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.3885114986
Short name T1020
Test name
Test status
Simulation time 39409400 ps
CPU time 136.64 seconds
Started Mar 10 12:39:21 PM PDT 24
Finished Mar 10 12:41:38 PM PDT 24
Peak memory 263424 kb
Host smart-96d79660-dca5-4184-be11-3be2ce72dc68
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885114986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.3885114986
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.3640546109
Short name T1007
Test name
Test status
Simulation time 20241576300 ps
CPU time 76.25 seconds
Started Mar 10 12:39:25 PM PDT 24
Finished Mar 10 12:40:42 PM PDT 24
Peak memory 258988 kb
Host smart-5546a6e5-abd3-4014-96d9-d9e2bed49ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640546109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.3640546109
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.2799277517
Short name T524
Test name
Test status
Simulation time 46248300 ps
CPU time 123.2 seconds
Started Mar 10 12:39:26 PM PDT 24
Finished Mar 10 12:41:29 PM PDT 24
Peak memory 276132 kb
Host smart-cdccc5f9-754c-4166-87b3-57d1929c25b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799277517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2799277517
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.3610173023
Short name T954
Test name
Test status
Simulation time 22121000 ps
CPU time 13.41 seconds
Started Mar 10 12:35:50 PM PDT 24
Finished Mar 10 12:36:04 PM PDT 24
Peak memory 264288 kb
Host smart-5a8192c3-f5dc-4cf6-bbbe-40328b21e678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610173023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.3
610173023
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.1977576081
Short name T516
Test name
Test status
Simulation time 14920600 ps
CPU time 15.62 seconds
Started Mar 10 12:35:53 PM PDT 24
Finished Mar 10 12:36:08 PM PDT 24
Peak memory 274900 kb
Host smart-0e09f83c-ed15-4a2d-a57c-e8abb263c639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977576081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1977576081
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.1995860969
Short name T885
Test name
Test status
Simulation time 9803900 ps
CPU time 21.96 seconds
Started Mar 10 12:35:47 PM PDT 24
Finished Mar 10 12:36:09 PM PDT 24
Peak memory 279948 kb
Host smart-cb95679b-e37a-4564-b213-b4d5b413f4b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995860969 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.1995860969
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.2105747606
Short name T288
Test name
Test status
Simulation time 5880018200 ps
CPU time 2172.82 seconds
Started Mar 10 12:35:51 PM PDT 24
Finished Mar 10 01:12:04 PM PDT 24
Peak memory 264640 kb
Host smart-fe359037-ea00-4979-9ce1-ffdd35ec9ab5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105747606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.2105747606
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.1006570869
Short name T568
Test name
Test status
Simulation time 567531600 ps
CPU time 734.88 seconds
Started Mar 10 12:35:50 PM PDT 24
Finished Mar 10 12:48:05 PM PDT 24
Peak memory 264728 kb
Host smart-0cd778f8-3823-48fb-89b9-24e1fe56486c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006570869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1006570869
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1540062080
Short name T285
Test name
Test status
Simulation time 10138654100 ps
CPU time 48.91 seconds
Started Mar 10 12:35:50 PM PDT 24
Finished Mar 10 12:36:39 PM PDT 24
Peak memory 264596 kb
Host smart-0f62841c-1bff-4bf6-b5db-84f9e44b7fc8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540062080 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.1540062080
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.797770736
Short name T916
Test name
Test status
Simulation time 42145800 ps
CPU time 13.74 seconds
Started Mar 10 12:35:56 PM PDT 24
Finished Mar 10 12:36:10 PM PDT 24
Peak memory 264708 kb
Host smart-7a05d7ab-57ec-4287-a3e5-acf03ce1831a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797770736 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.797770736
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.2629004417
Short name T465
Test name
Test status
Simulation time 40121773600 ps
CPU time 700.48 seconds
Started Mar 10 12:35:49 PM PDT 24
Finished Mar 10 12:47:29 PM PDT 24
Peak memory 258404 kb
Host smart-7f7d4d9e-e52b-4e03-8533-f37d7e117335
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629004417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.2629004417
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.4204204940
Short name T527
Test name
Test status
Simulation time 43488353800 ps
CPU time 261.54 seconds
Started Mar 10 12:35:49 PM PDT 24
Finished Mar 10 12:40:11 PM PDT 24
Peak memory 261584 kb
Host smart-65eee000-b93d-47a0-9e4d-b3cd18999b2c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204204940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.4204204940
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1824760078
Short name T474
Test name
Test status
Simulation time 9040955100 ps
CPU time 216.04 seconds
Started Mar 10 12:35:44 PM PDT 24
Finished Mar 10 12:39:20 PM PDT 24
Peak memory 289296 kb
Host smart-5aae793e-9e31-4c2e-a2c4-1226ca8f38d9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824760078 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.1824760078
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.517987091
Short name T1124
Test name
Test status
Simulation time 7780560300 ps
CPU time 88.87 seconds
Started Mar 10 12:36:57 PM PDT 24
Finished Mar 10 12:38:26 PM PDT 24
Peak memory 264628 kb
Host smart-4be1e55f-b678-4208-90c4-0c00d3deb70a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517987091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.flash_ctrl_intr_wr.517987091
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.167037166
Short name T664
Test name
Test status
Simulation time 104698065200 ps
CPU time 460.69 seconds
Started Mar 10 12:35:51 PM PDT 24
Finished Mar 10 12:43:32 PM PDT 24
Peak memory 264692 kb
Host smart-97618857-98ed-4250-bf51-fc274dade92f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167
037166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.167037166
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.557925875
Short name T839
Test name
Test status
Simulation time 10218578900 ps
CPU time 67.83 seconds
Started Mar 10 12:35:56 PM PDT 24
Finished Mar 10 12:37:04 PM PDT 24
Peak memory 259116 kb
Host smart-0a4d4563-58aa-4874-ae1e-3fca1c6eef0c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557925875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.557925875
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.588855582
Short name T498
Test name
Test status
Simulation time 64844100 ps
CPU time 13.62 seconds
Started Mar 10 12:35:51 PM PDT 24
Finished Mar 10 12:36:05 PM PDT 24
Peak memory 264740 kb
Host smart-e5b2f714-9a59-4b0c-9559-66e7318327a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588855582 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.588855582
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.4219137509
Short name T103
Test name
Test status
Simulation time 12996467300 ps
CPU time 333.16 seconds
Started Mar 10 12:35:49 PM PDT 24
Finished Mar 10 12:41:23 PM PDT 24
Peak memory 272404 kb
Host smart-63951e86-3471-4970-be93-ac027bfc765d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219137509 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.4219137509
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.3913195740
Short name T667
Test name
Test status
Simulation time 265935500 ps
CPU time 132.88 seconds
Started Mar 10 12:35:46 PM PDT 24
Finished Mar 10 12:37:59 PM PDT 24
Peak memory 259260 kb
Host smart-1289bd0b-87b2-4d7e-ad25-b5a9ddab50a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913195740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.3913195740
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.2880783129
Short name T63
Test name
Test status
Simulation time 97955600 ps
CPU time 114.08 seconds
Started Mar 10 12:35:49 PM PDT 24
Finished Mar 10 12:37:44 PM PDT 24
Peak memory 261660 kb
Host smart-1d0f687f-8bdb-4718-9b6a-0f1445ed8e37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880783129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.2880783129
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.3692841814
Short name T759
Test name
Test status
Simulation time 70717700 ps
CPU time 13.53 seconds
Started Mar 10 12:35:47 PM PDT 24
Finished Mar 10 12:36:01 PM PDT 24
Peak memory 264740 kb
Host smart-8584fccb-b04a-4f1b-bab6-cd10249be63b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692841814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.3692841814
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.1822147602
Short name T536
Test name
Test status
Simulation time 487202200 ps
CPU time 306.04 seconds
Started Mar 10 12:35:49 PM PDT 24
Finished Mar 10 12:40:55 PM PDT 24
Peak memory 275260 kb
Host smart-6b44c7eb-a277-4964-b8dd-a5eae11b0ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822147602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.1822147602
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.3804270287
Short name T520
Test name
Test status
Simulation time 131695900 ps
CPU time 39.19 seconds
Started Mar 10 12:35:48 PM PDT 24
Finished Mar 10 12:36:28 PM PDT 24
Peak memory 273048 kb
Host smart-7dbaa515-5867-4e82-99ba-ca25a95a1d65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804270287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.3804270287
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.2846054453
Short name T1034
Test name
Test status
Simulation time 3011011900 ps
CPU time 96.44 seconds
Started Mar 10 12:35:46 PM PDT 24
Finished Mar 10 12:37:22 PM PDT 24
Peak memory 281092 kb
Host smart-6a59210d-f6a9-4d71-a2e7-2ed7a8361cbc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846054453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_ro.2846054453
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.1814258819
Short name T639
Test name
Test status
Simulation time 2886593700 ps
CPU time 102.53 seconds
Started Mar 10 12:35:47 PM PDT 24
Finished Mar 10 12:37:29 PM PDT 24
Peak memory 281252 kb
Host smart-51ac78d6-07b0-403b-9036-ae8462919462
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1814258819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1814258819
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.2204701096
Short name T529
Test name
Test status
Simulation time 2064394300 ps
CPU time 127.35 seconds
Started Mar 10 12:35:56 PM PDT 24
Finished Mar 10 12:38:03 PM PDT 24
Peak memory 281328 kb
Host smart-a391ea70-4acf-45df-9512-63cead725aa1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204701096 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.2204701096
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.725920436
Short name T851
Test name
Test status
Simulation time 5157886200 ps
CPU time 440.03 seconds
Started Mar 10 12:35:45 PM PDT 24
Finished Mar 10 12:43:06 PM PDT 24
Peak memory 313760 kb
Host smart-86430b42-c868-4080-b206-bba5bc89cd9c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725920436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctr
l_rw.725920436
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.619336765
Short name T208
Test name
Test status
Simulation time 2021804100 ps
CPU time 446.06 seconds
Started Mar 10 12:35:56 PM PDT 24
Finished Mar 10 12:43:23 PM PDT 24
Peak memory 316492 kb
Host smart-96b56870-c11b-4b71-b09b-84b96ea61d97
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619336765 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.flash_ctrl_rw_derr.619336765
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.2024015214
Short name T189
Test name
Test status
Simulation time 38042100 ps
CPU time 30.82 seconds
Started Mar 10 12:35:50 PM PDT 24
Finished Mar 10 12:36:21 PM PDT 24
Peak memory 273104 kb
Host smart-c71c65c9-0539-4bd4-b27f-d2ea8382be3c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024015214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.2024015214
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.3738430103
Short name T378
Test name
Test status
Simulation time 18052469300 ps
CPU time 572.64 seconds
Started Mar 10 12:35:44 PM PDT 24
Finished Mar 10 12:45:17 PM PDT 24
Peak memory 319432 kb
Host smart-108383b8-add8-4cf7-888e-8810d168771b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738430103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.3738430103
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.2545942479
Short name T799
Test name
Test status
Simulation time 1750323800 ps
CPU time 57.68 seconds
Started Mar 10 12:37:01 PM PDT 24
Finished Mar 10 12:37:59 PM PDT 24
Peak memory 262448 kb
Host smart-114dc69e-dda3-4ef3-8c60-cbdcdaaf56ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545942479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.2545942479
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.442673350
Short name T485
Test name
Test status
Simulation time 147841700 ps
CPU time 74.22 seconds
Started Mar 10 12:35:56 PM PDT 24
Finished Mar 10 12:37:10 PM PDT 24
Peak memory 278164 kb
Host smart-eff34964-f069-49f6-b549-17106b5db9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442673350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.442673350
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.1650405108
Short name T1068
Test name
Test status
Simulation time 7687240500 ps
CPU time 159.21 seconds
Started Mar 10 12:35:47 PM PDT 24
Finished Mar 10 12:38:26 PM PDT 24
Peak memory 264648 kb
Host smart-3fc83b57-0299-493c-a857-6287afc996ff
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650405108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.flash_ctrl_wo.1650405108
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.3066680945
Short name T1014
Test name
Test status
Simulation time 24068700 ps
CPU time 16.03 seconds
Started Mar 10 12:39:24 PM PDT 24
Finished Mar 10 12:39:41 PM PDT 24
Peak memory 273824 kb
Host smart-bc3b85c3-60ff-4fba-988c-b93f376b6bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066680945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3066680945
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.1568421195
Short name T955
Test name
Test status
Simulation time 111611100 ps
CPU time 131.93 seconds
Started Mar 10 12:39:25 PM PDT 24
Finished Mar 10 12:41:37 PM PDT 24
Peak memory 259276 kb
Host smart-8d76e877-c056-413f-a42f-cd6a3e8c1f80
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568421195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.1568421195
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.997203225
Short name T188
Test name
Test status
Simulation time 13613900 ps
CPU time 13.3 seconds
Started Mar 10 12:39:23 PM PDT 24
Finished Mar 10 12:39:36 PM PDT 24
Peak memory 273856 kb
Host smart-0671d4e5-7676-4c87-9a92-1431f9a60b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997203225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.997203225
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.1864170008
Short name T964
Test name
Test status
Simulation time 24094500 ps
CPU time 15.93 seconds
Started Mar 10 12:39:24 PM PDT 24
Finished Mar 10 12:39:41 PM PDT 24
Peak memory 275108 kb
Host smart-f99b07da-fcb9-4dd6-9072-68680a535066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864170008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1864170008
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.1800715264
Short name T1010
Test name
Test status
Simulation time 119580400 ps
CPU time 134.48 seconds
Started Mar 10 12:39:25 PM PDT 24
Finished Mar 10 12:41:39 PM PDT 24
Peak memory 259044 kb
Host smart-100598e5-f53b-4ce9-ad1f-c6feb1724790
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800715264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.1800715264
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.1728059028
Short name T622
Test name
Test status
Simulation time 15431500 ps
CPU time 15.94 seconds
Started Mar 10 12:39:21 PM PDT 24
Finished Mar 10 12:39:38 PM PDT 24
Peak memory 274308 kb
Host smart-42c7e266-2a7d-4ab4-ad75-b7fe66994ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728059028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1728059028
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.2218885077
Short name T766
Test name
Test status
Simulation time 43284600 ps
CPU time 129.71 seconds
Started Mar 10 12:39:24 PM PDT 24
Finished Mar 10 12:41:34 PM PDT 24
Peak memory 259116 kb
Host smart-f493dfc7-ea7c-4821-b992-f26993ec36f9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218885077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.2218885077
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.917336592
Short name T560
Test name
Test status
Simulation time 24749400 ps
CPU time 13.38 seconds
Started Mar 10 12:39:30 PM PDT 24
Finished Mar 10 12:39:46 PM PDT 24
Peak memory 283180 kb
Host smart-158bf782-0ae6-41a3-957c-cb4abc0202a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917336592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.917336592
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.389701750
Short name T689
Test name
Test status
Simulation time 148423600 ps
CPU time 137.36 seconds
Started Mar 10 12:39:23 PM PDT 24
Finished Mar 10 12:41:40 PM PDT 24
Peak memory 263244 kb
Host smart-fa2fbfba-7b33-47db-a418-c972f9ac9534
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389701750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_ot
p_reset.389701750
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.388616089
Short name T771
Test name
Test status
Simulation time 52784400 ps
CPU time 15.85 seconds
Started Mar 10 12:39:32 PM PDT 24
Finished Mar 10 12:39:49 PM PDT 24
Peak memory 273864 kb
Host smart-1644d6b0-d943-49ab-80ef-8e2f88b010ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388616089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.388616089
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.856343448
Short name T846
Test name
Test status
Simulation time 90000300 ps
CPU time 135.92 seconds
Started Mar 10 12:39:27 PM PDT 24
Finished Mar 10 12:41:44 PM PDT 24
Peak memory 260288 kb
Host smart-ab4d1ab6-5f33-484d-a9b9-904c3e8cb799
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856343448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_ot
p_reset.856343448
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.3136365915
Short name T696
Test name
Test status
Simulation time 28782800 ps
CPU time 13.29 seconds
Started Mar 10 12:39:29 PM PDT 24
Finished Mar 10 12:39:46 PM PDT 24
Peak memory 274080 kb
Host smart-5fa256b2-dce7-4d6d-80fc-1a7c299970d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136365915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.3136365915
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.2097697734
Short name T687
Test name
Test status
Simulation time 177229200 ps
CPU time 135.08 seconds
Started Mar 10 12:39:30 PM PDT 24
Finished Mar 10 12:41:48 PM PDT 24
Peak memory 263924 kb
Host smart-62e28ece-167a-4a04-8437-35611968f756
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097697734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.2097697734
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.4153330102
Short name T71
Test name
Test status
Simulation time 223999800 ps
CPU time 13.57 seconds
Started Mar 10 12:39:30 PM PDT 24
Finished Mar 10 12:39:46 PM PDT 24
Peak memory 273972 kb
Host smart-931118e7-d3b0-40c0-9d9c-184686643b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153330102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.4153330102
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.398302364
Short name T1001
Test name
Test status
Simulation time 77138300 ps
CPU time 130.46 seconds
Started Mar 10 12:39:28 PM PDT 24
Finished Mar 10 12:41:38 PM PDT 24
Peak memory 258916 kb
Host smart-666a336c-b7de-4d96-ac69-b4457ebd95fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398302364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_ot
p_reset.398302364
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.1333805889
Short name T591
Test name
Test status
Simulation time 17155100 ps
CPU time 13.35 seconds
Started Mar 10 12:39:27 PM PDT 24
Finished Mar 10 12:39:41 PM PDT 24
Peak memory 273824 kb
Host smart-7e7c4972-4984-42e0-9bcb-2ffc104a8185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333805889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1333805889
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.657112522
Short name T774
Test name
Test status
Simulation time 38123700 ps
CPU time 130.33 seconds
Started Mar 10 12:39:29 PM PDT 24
Finished Mar 10 12:41:43 PM PDT 24
Peak memory 259060 kb
Host smart-82700d58-fd36-4cbb-ab7f-ba91d4362d96
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657112522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_ot
p_reset.657112522
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.3068093500
Short name T787
Test name
Test status
Simulation time 13705000 ps
CPU time 13.19 seconds
Started Mar 10 12:39:28 PM PDT 24
Finished Mar 10 12:39:41 PM PDT 24
Peak memory 274300 kb
Host smart-7801ceb5-7245-4155-a6ec-f9d12b144f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068093500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.3068093500
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.817588736
Short name T411
Test name
Test status
Simulation time 36983700 ps
CPU time 111.07 seconds
Started Mar 10 12:39:27 PM PDT 24
Finished Mar 10 12:41:18 PM PDT 24
Peak memory 259228 kb
Host smart-7327df70-380d-4561-9110-6f28ab32d892
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817588736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_ot
p_reset.817588736
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.3946702794
Short name T634
Test name
Test status
Simulation time 15405400 ps
CPU time 15.89 seconds
Started Mar 10 12:36:11 PM PDT 24
Finished Mar 10 12:36:27 PM PDT 24
Peak memory 273960 kb
Host smart-b02d0a83-a914-41e6-bf96-6d2077acd637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946702794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.3946702794
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.775128749
Short name T359
Test name
Test status
Simulation time 21411100 ps
CPU time 21.95 seconds
Started Mar 10 12:36:12 PM PDT 24
Finished Mar 10 12:36:35 PM PDT 24
Peak memory 279620 kb
Host smart-a7a18901-bea0-4b64-a28f-7570d9ecda31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775128749 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.775128749
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.3117953733
Short name T747
Test name
Test status
Simulation time 9581501300 ps
CPU time 2189.24 seconds
Started Mar 10 12:35:59 PM PDT 24
Finished Mar 10 01:12:28 PM PDT 24
Peak memory 263856 kb
Host smart-036c59ba-115d-4284-9792-0323fbcd7eb7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117953733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.3117953733
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.4241981911
Short name T587
Test name
Test status
Simulation time 766508000 ps
CPU time 944.05 seconds
Started Mar 10 12:36:01 PM PDT 24
Finished Mar 10 12:51:46 PM PDT 24
Peak memory 272820 kb
Host smart-e70eb673-05a9-475e-bacf-37d1c1d91bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241981911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.4241981911
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.188967836
Short name T813
Test name
Test status
Simulation time 849743500 ps
CPU time 25.29 seconds
Started Mar 10 12:36:01 PM PDT 24
Finished Mar 10 12:36:27 PM PDT 24
Peak memory 264768 kb
Host smart-6725e99b-2d04-4004-9b40-6113d99ee23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188967836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.188967836
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3077622234
Short name T1073
Test name
Test status
Simulation time 10011706900 ps
CPU time 139.93 seconds
Started Mar 10 12:36:10 PM PDT 24
Finished Mar 10 12:38:32 PM PDT 24
Peak memory 381164 kb
Host smart-5fea60ee-a358-45bc-8147-b74b32df54f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077622234 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3077622234
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.2084170302
Short name T125
Test name
Test status
Simulation time 15566100 ps
CPU time 13.4 seconds
Started Mar 10 12:36:12 PM PDT 24
Finished Mar 10 12:36:26 PM PDT 24
Peak memory 264660 kb
Host smart-c9bdaafe-1a28-4574-a227-fc9eedf1d356
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084170302 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.2084170302
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.3412780032
Short name T1032
Test name
Test status
Simulation time 50120985500 ps
CPU time 777.98 seconds
Started Mar 10 12:36:03 PM PDT 24
Finished Mar 10 12:49:03 PM PDT 24
Peak memory 263564 kb
Host smart-eb5035b1-f0f5-4134-b35c-def05714bcca
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412780032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.3412780032
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.1934858532
Short name T317
Test name
Test status
Simulation time 9780285700 ps
CPU time 135.27 seconds
Started Mar 10 12:35:57 PM PDT 24
Finished Mar 10 12:38:12 PM PDT 24
Peak memory 261300 kb
Host smart-77a9b0e2-6822-497b-b446-e1876b7767e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934858532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.1934858532
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.1198651922
Short name T720
Test name
Test status
Simulation time 1393815500 ps
CPU time 147.91 seconds
Started Mar 10 12:36:09 PM PDT 24
Finished Mar 10 12:38:39 PM PDT 24
Peak memory 293484 kb
Host smart-9d5216b4-9e2e-42e1-9dfa-8c12ff775563
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198651922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.1198651922
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.4179286787
Short name T1042
Test name
Test status
Simulation time 32577804300 ps
CPU time 192.49 seconds
Started Mar 10 12:36:10 PM PDT 24
Finished Mar 10 12:39:24 PM PDT 24
Peak memory 284040 kb
Host smart-d7c0b11f-701a-445f-8e61-78b7439ccf5f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179286787 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.4179286787
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.3728673914
Short name T428
Test name
Test status
Simulation time 43200910400 ps
CPU time 109.58 seconds
Started Mar 10 12:36:07 PM PDT 24
Finished Mar 10 12:37:56 PM PDT 24
Peak memory 264672 kb
Host smart-d9ee0684-5076-40fe-9871-0e0fd6602d68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728673914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.3728673914
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.328092419
Short name T733
Test name
Test status
Simulation time 106255437100 ps
CPU time 387.32 seconds
Started Mar 10 12:36:06 PM PDT 24
Finished Mar 10 12:42:33 PM PDT 24
Peak memory 264688 kb
Host smart-e4dd4536-1862-4b27-899f-2d510cac7d1b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328
092419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.328092419
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.1352486807
Short name T1125
Test name
Test status
Simulation time 1929431700 ps
CPU time 87.82 seconds
Started Mar 10 12:36:00 PM PDT 24
Finished Mar 10 12:37:28 PM PDT 24
Peak memory 259268 kb
Host smart-fbac8843-4cf5-4741-b5b9-bd322ba14006
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352486807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.1352486807
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.86303521
Short name T588
Test name
Test status
Simulation time 107527200 ps
CPU time 13.83 seconds
Started Mar 10 12:36:11 PM PDT 24
Finished Mar 10 12:36:25 PM PDT 24
Peak memory 264832 kb
Host smart-5494784f-c408-4f3b-9dfd-771f00ded90b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86303521 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.86303521
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.3653739006
Short name T83
Test name
Test status
Simulation time 19668889100 ps
CPU time 458.35 seconds
Started Mar 10 12:36:05 PM PDT 24
Finished Mar 10 12:43:44 PM PDT 24
Peak memory 273504 kb
Host smart-6e76f11f-8a52-4adb-80b9-179f810ef744
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653739006 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.3653739006
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.2309794199
Short name T666
Test name
Test status
Simulation time 68351200 ps
CPU time 113.3 seconds
Started Mar 10 12:36:01 PM PDT 24
Finished Mar 10 12:37:55 PM PDT 24
Peak memory 262512 kb
Host smart-ed7c7502-302c-4fff-9b2a-b6647eaff051
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309794199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.2309794199
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.4161415071
Short name T66
Test name
Test status
Simulation time 1585298400 ps
CPU time 162.25 seconds
Started Mar 10 12:35:55 PM PDT 24
Finished Mar 10 12:38:38 PM PDT 24
Peak memory 264636 kb
Host smart-97fc71d9-f7a4-4e10-8a44-376f6151fbe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4161415071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.4161415071
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.665954130
Short name T272
Test name
Test status
Simulation time 527666600 ps
CPU time 22.71 seconds
Started Mar 10 12:36:07 PM PDT 24
Finished Mar 10 12:36:30 PM PDT 24
Peak memory 264716 kb
Host smart-07dfab65-fc03-46cf-82ed-ca5c2e4c54cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665954130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_rese
t.665954130
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.3391058436
Short name T101
Test name
Test status
Simulation time 1597974000 ps
CPU time 850.79 seconds
Started Mar 10 12:35:57 PM PDT 24
Finished Mar 10 12:50:08 PM PDT 24
Peak memory 282756 kb
Host smart-d7bd5cbb-f311-4fab-9ec7-cc893a3f66b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391058436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.3391058436
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.2421226704
Short name T1119
Test name
Test status
Simulation time 317600000 ps
CPU time 71.78 seconds
Started Mar 10 12:36:10 PM PDT 24
Finished Mar 10 12:37:23 PM PDT 24
Peak memory 281156 kb
Host smart-1d290868-362f-4e1e-aa43-726b652e60d6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421226704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_ro.2421226704
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.707633491
Short name T617
Test name
Test status
Simulation time 592009200 ps
CPU time 131.15 seconds
Started Mar 10 12:36:06 PM PDT 24
Finished Mar 10 12:38:17 PM PDT 24
Peak memory 281244 kb
Host smart-21f1347d-5daa-4cae-81ad-45f2047eb05c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
707633491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.707633491
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.3229151524
Short name T822
Test name
Test status
Simulation time 2775852300 ps
CPU time 126.23 seconds
Started Mar 10 12:36:05 PM PDT 24
Finished Mar 10 12:38:12 PM PDT 24
Peak memory 281224 kb
Host smart-885b15e9-a73e-4389-ba1c-90c75d145b76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229151524 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.3229151524
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.3125388359
Short name T64
Test name
Test status
Simulation time 71024333100 ps
CPU time 524.17 seconds
Started Mar 10 12:36:07 PM PDT 24
Finished Mar 10 12:44:51 PM PDT 24
Peak memory 308768 kb
Host smart-40f378a0-eb73-4466-9900-8c7e62b3c342
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125388359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct
rl_rw.3125388359
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.178308913
Short name T965
Test name
Test status
Simulation time 15365118100 ps
CPU time 644.66 seconds
Started Mar 10 12:36:08 PM PDT 24
Finished Mar 10 12:46:53 PM PDT 24
Peak memory 328856 kb
Host smart-ab0d2869-05a6-4220-8861-4592df8adf70
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178308913 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_rw_derr.178308913
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.1304414027
Short name T523
Test name
Test status
Simulation time 92744500 ps
CPU time 32.36 seconds
Started Mar 10 12:36:09 PM PDT 24
Finished Mar 10 12:36:42 PM PDT 24
Peak memory 274048 kb
Host smart-901565ab-6c9a-4705-9dfa-344d93d53ea9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304414027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.1304414027
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.187137133
Short name T384
Test name
Test status
Simulation time 80843400 ps
CPU time 28.43 seconds
Started Mar 10 12:36:05 PM PDT 24
Finished Mar 10 12:36:34 PM PDT 24
Peak memory 273008 kb
Host smart-adaaadf5-e05f-47f5-82f2-2583df5781b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187137133 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.187137133
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.2778796560
Short name T585
Test name
Test status
Simulation time 6674074200 ps
CPU time 566.41 seconds
Started Mar 10 12:36:06 PM PDT 24
Finished Mar 10 12:45:33 PM PDT 24
Peak memory 312580 kb
Host smart-45fb42be-1346-4a9b-94c0-cc81274a3d5f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778796560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.2778796560
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.3571166494
Short name T40
Test name
Test status
Simulation time 25437300 ps
CPU time 123.96 seconds
Started Mar 10 12:35:58 PM PDT 24
Finished Mar 10 12:38:02 PM PDT 24
Peak memory 277800 kb
Host smart-f0cab8a0-0d1f-4cc2-a55a-829804861f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571166494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3571166494
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.3818815202
Short name T651
Test name
Test status
Simulation time 3858920600 ps
CPU time 133.38 seconds
Started Mar 10 12:36:02 PM PDT 24
Finished Mar 10 12:38:17 PM PDT 24
Peak memory 264712 kb
Host smart-729ce014-3c33-45fe-8387-a72bca978c6e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818815202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.flash_ctrl_wo.3818815202
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.3912784912
Short name T405
Test name
Test status
Simulation time 65546200 ps
CPU time 15.42 seconds
Started Mar 10 12:39:29 PM PDT 24
Finished Mar 10 12:39:48 PM PDT 24
Peak memory 273784 kb
Host smart-4b58374e-5ae7-468d-87b1-e23857ab0378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912784912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.3912784912
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.1563284908
Short name T1126
Test name
Test status
Simulation time 38963800 ps
CPU time 134.13 seconds
Started Mar 10 12:39:30 PM PDT 24
Finished Mar 10 12:41:47 PM PDT 24
Peak memory 259056 kb
Host smart-008a1a2a-7cd7-4d14-b999-6fad3eecc482
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563284908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.1563284908
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.2767709202
Short name T722
Test name
Test status
Simulation time 13969800 ps
CPU time 15.93 seconds
Started Mar 10 12:39:28 PM PDT 24
Finished Mar 10 12:39:44 PM PDT 24
Peak memory 274884 kb
Host smart-37fe2c0a-e25d-498b-a4c9-5ae7922d3552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767709202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.2767709202
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.47672567
Short name T521
Test name
Test status
Simulation time 396290200 ps
CPU time 132.78 seconds
Started Mar 10 12:39:30 PM PDT 24
Finished Mar 10 12:41:46 PM PDT 24
Peak memory 258968 kb
Host smart-6a8b03ae-e36b-4bcd-bbc2-b981ec57a78b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47672567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp
_reset.47672567
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.3975786622
Short name T302
Test name
Test status
Simulation time 42168400 ps
CPU time 15.59 seconds
Started Mar 10 12:39:33 PM PDT 24
Finished Mar 10 12:39:48 PM PDT 24
Peak memory 274024 kb
Host smart-1ee0fe3b-e4aa-4376-8579-5fc708ceb034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975786622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3975786622
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.3840550379
Short name T1051
Test name
Test status
Simulation time 119155600 ps
CPU time 131.19 seconds
Started Mar 10 12:39:32 PM PDT 24
Finished Mar 10 12:41:44 PM PDT 24
Peak memory 258908 kb
Host smart-1752577d-fd58-4d18-a599-a348b3823a70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840550379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.3840550379
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.3393784389
Short name T590
Test name
Test status
Simulation time 23783700 ps
CPU time 16.03 seconds
Started Mar 10 12:39:32 PM PDT 24
Finished Mar 10 12:39:49 PM PDT 24
Peak memory 273936 kb
Host smart-45813023-eec7-48e9-bb14-1253f8e620c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393784389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.3393784389
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.621091642
Short name T558
Test name
Test status
Simulation time 184696100 ps
CPU time 132.29 seconds
Started Mar 10 12:39:35 PM PDT 24
Finished Mar 10 12:41:47 PM PDT 24
Peak memory 259196 kb
Host smart-dd83e8ef-bb75-4bfb-99e4-ba3be10bf38f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621091642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot
p_reset.621091642
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.3003092298
Short name T182
Test name
Test status
Simulation time 45229600 ps
CPU time 15.55 seconds
Started Mar 10 12:39:39 PM PDT 24
Finished Mar 10 12:39:54 PM PDT 24
Peak memory 273880 kb
Host smart-dfd62b52-f8cd-4bbb-a609-f8eaf33485a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003092298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.3003092298
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.4031046208
Short name T997
Test name
Test status
Simulation time 143115600 ps
CPU time 132.81 seconds
Started Mar 10 12:39:34 PM PDT 24
Finished Mar 10 12:41:47 PM PDT 24
Peak memory 258984 kb
Host smart-1148029f-7c17-45ad-86d3-06fd7041dbdd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031046208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.4031046208
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2325261838
Short name T425
Test name
Test status
Simulation time 14912800 ps
CPU time 13.53 seconds
Started Mar 10 12:39:34 PM PDT 24
Finished Mar 10 12:39:48 PM PDT 24
Peak memory 275156 kb
Host smart-56ece016-a3bb-42d4-937e-1c7f1e78039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325261838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2325261838
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.129392711
Short name T966
Test name
Test status
Simulation time 45259100 ps
CPU time 131.59 seconds
Started Mar 10 12:39:38 PM PDT 24
Finished Mar 10 12:41:50 PM PDT 24
Peak memory 259188 kb
Host smart-8fba455c-9706-4a82-9b07-8f3c0722e3c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129392711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_ot
p_reset.129392711
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.2909157920
Short name T463
Test name
Test status
Simulation time 16923200 ps
CPU time 13.25 seconds
Started Mar 10 12:39:34 PM PDT 24
Finished Mar 10 12:39:47 PM PDT 24
Peak memory 274008 kb
Host smart-b7a18543-92f0-4c87-aa41-ba69d70f3f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909157920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2909157920
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.159753335
Short name T137
Test name
Test status
Simulation time 168445300 ps
CPU time 110.29 seconds
Started Mar 10 12:39:35 PM PDT 24
Finished Mar 10 12:41:25 PM PDT 24
Peak memory 259240 kb
Host smart-1be23711-e6b9-43e3-bf50-5f59291858db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159753335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_ot
p_reset.159753335
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.1766673833
Short name T1071
Test name
Test status
Simulation time 43219100 ps
CPU time 15.8 seconds
Started Mar 10 12:39:34 PM PDT 24
Finished Mar 10 12:39:50 PM PDT 24
Peak memory 274012 kb
Host smart-2be577d7-6c9d-4c7b-b452-711059fa0fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766673833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1766673833
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.3831796395
Short name T567
Test name
Test status
Simulation time 155931900 ps
CPU time 130.83 seconds
Started Mar 10 12:39:34 PM PDT 24
Finished Mar 10 12:41:45 PM PDT 24
Peak memory 258904 kb
Host smart-1bc37251-666c-4617-8317-6ec21d0f6f80
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831796395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.3831796395
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.937321160
Short name T467
Test name
Test status
Simulation time 77781200 ps
CPU time 15.63 seconds
Started Mar 10 12:39:39 PM PDT 24
Finished Mar 10 12:39:55 PM PDT 24
Peak memory 274856 kb
Host smart-277db1da-d4ff-494d-bbbc-e8cac4904d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937321160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.937321160
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.978431556
Short name T123
Test name
Test status
Simulation time 57945600 ps
CPU time 109.02 seconds
Started Mar 10 12:39:38 PM PDT 24
Finished Mar 10 12:41:27 PM PDT 24
Peak memory 259116 kb
Host smart-5abfbffd-4691-45e0-b320-3c1494ded5e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978431556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_ot
p_reset.978431556
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.2056603560
Short name T461
Test name
Test status
Simulation time 13607800 ps
CPU time 15.72 seconds
Started Mar 10 12:39:35 PM PDT 24
Finished Mar 10 12:39:51 PM PDT 24
Peak memory 274176 kb
Host smart-dda1cbcf-8d18-44f9-b31c-a3e3c784ec4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056603560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2056603560
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.1697827705
Short name T744
Test name
Test status
Simulation time 132183400 ps
CPU time 14.29 seconds
Started Mar 10 12:36:21 PM PDT 24
Finished Mar 10 12:36:36 PM PDT 24
Peak memory 263448 kb
Host smart-767ba301-2e9d-4e42-b33f-ffae29ebdb59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697827705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1
697827705
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.1546457519
Short name T443
Test name
Test status
Simulation time 137750600 ps
CPU time 15.62 seconds
Started Mar 10 12:36:22 PM PDT 24
Finished Mar 10 12:36:38 PM PDT 24
Peak memory 274792 kb
Host smart-bdb20ccc-d430-459f-aa09-69ea15c9848b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546457519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.1546457519
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.2743407707
Short name T856
Test name
Test status
Simulation time 77538200 ps
CPU time 22.03 seconds
Started Mar 10 12:36:20 PM PDT 24
Finished Mar 10 12:36:42 PM PDT 24
Peak memory 264812 kb
Host smart-2b7606e7-2318-4417-b8bc-6b657534a22e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743407707 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.2743407707
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.2960141845
Short name T812
Test name
Test status
Simulation time 7850282200 ps
CPU time 2166.29 seconds
Started Mar 10 12:36:15 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 264052 kb
Host smart-34b01329-c85e-4ce2-b37d-2290fd3bc656
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960141845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.2960141845
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.4064852170
Short name T310
Test name
Test status
Simulation time 4002245200 ps
CPU time 931.69 seconds
Started Mar 10 12:36:16 PM PDT 24
Finished Mar 10 12:51:48 PM PDT 24
Peak memory 272944 kb
Host smart-06c626e4-18a2-4afd-8eb7-f57fc73fe71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064852170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.4064852170
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.2978467137
Short name T51
Test name
Test status
Simulation time 465598500 ps
CPU time 27.69 seconds
Started Mar 10 12:36:18 PM PDT 24
Finished Mar 10 12:36:47 PM PDT 24
Peak memory 264756 kb
Host smart-0132e3ee-efc3-450f-b91a-63f9d81e154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978467137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.2978467137
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.764221351
Short name T557
Test name
Test status
Simulation time 10027238900 ps
CPU time 76.21 seconds
Started Mar 10 12:36:20 PM PDT 24
Finished Mar 10 12:37:37 PM PDT 24
Peak memory 304364 kb
Host smart-3325673f-aac1-409c-ba68-52dec850e357
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764221351 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.764221351
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.3465990459
Short name T715
Test name
Test status
Simulation time 48054600 ps
CPU time 13.63 seconds
Started Mar 10 12:36:20 PM PDT 24
Finished Mar 10 12:36:34 PM PDT 24
Peak memory 264848 kb
Host smart-77f82263-03f9-4300-9649-f05c9c7ee5c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465990459 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.3465990459
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.1662418203
Short name T827
Test name
Test status
Simulation time 270246155800 ps
CPU time 979.28 seconds
Started Mar 10 12:36:17 PM PDT 24
Finished Mar 10 12:52:37 PM PDT 24
Peak memory 258648 kb
Host smart-4c1eee7b-84f2-4bf8-b22f-bad7b1cd3ab1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662418203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.1662418203
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1525625623
Short name T308
Test name
Test status
Simulation time 3193422900 ps
CPU time 57.3 seconds
Started Mar 10 12:36:17 PM PDT 24
Finished Mar 10 12:37:14 PM PDT 24
Peak memory 258624 kb
Host smart-1c88a28e-7ebd-499a-a13c-2c8c2811be6c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525625623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.1525625623
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.2776667615
Short name T33
Test name
Test status
Simulation time 8755413600 ps
CPU time 174.37 seconds
Started Mar 10 12:36:16 PM PDT 24
Finished Mar 10 12:39:10 PM PDT 24
Peak memory 290376 kb
Host smart-f4efe099-4317-4f80-8502-02650a1b54af
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776667615 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.2776667615
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.803791979
Short name T551
Test name
Test status
Simulation time 9081007100 ps
CPU time 91.07 seconds
Started Mar 10 12:36:16 PM PDT 24
Finished Mar 10 12:37:48 PM PDT 24
Peak memory 265052 kb
Host smart-4c0423c5-7cbc-4e50-ba9b-7e4c10374b0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803791979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.flash_ctrl_intr_wr.803791979
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.4027963760
Short name T450
Test name
Test status
Simulation time 125511594300 ps
CPU time 379.97 seconds
Started Mar 10 12:37:24 PM PDT 24
Finished Mar 10 12:43:44 PM PDT 24
Peak memory 264640 kb
Host smart-89089a67-7233-4de2-875f-41a1112789d0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402
7963760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.4027963760
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.2562775281
Short name T380
Test name
Test status
Simulation time 8275708200 ps
CPU time 73.67 seconds
Started Mar 10 12:36:16 PM PDT 24
Finished Mar 10 12:37:30 PM PDT 24
Peak memory 259856 kb
Host smart-7a56e002-fb9d-4858-8c7d-a951f54ee70a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562775281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2562775281
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.1399323916
Short name T694
Test name
Test status
Simulation time 25561900 ps
CPU time 13.37 seconds
Started Mar 10 12:36:21 PM PDT 24
Finished Mar 10 12:36:35 PM PDT 24
Peak memory 264644 kb
Host smart-147e62d3-7e27-4e56-97aa-6af9bbac5468
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399323916 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.1399323916
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.3736171874
Short name T713
Test name
Test status
Simulation time 44602600 ps
CPU time 109.3 seconds
Started Mar 10 12:36:17 PM PDT 24
Finished Mar 10 12:38:07 PM PDT 24
Peak memory 260208 kb
Host smart-118a350b-ea2d-4f69-ac07-5a93e6375369
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736171874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.3736171874
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.1320975774
Short name T61
Test name
Test status
Simulation time 938313300 ps
CPU time 453.46 seconds
Started Mar 10 12:36:16 PM PDT 24
Finished Mar 10 12:43:49 PM PDT 24
Peak memory 264648 kb
Host smart-9f6532ce-9531-4f2a-ab70-59c671bcd508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320975774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1320975774
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.1744763361
Short name T679
Test name
Test status
Simulation time 30414300 ps
CPU time 13.42 seconds
Started Mar 10 12:36:30 PM PDT 24
Finished Mar 10 12:36:44 PM PDT 24
Peak memory 264700 kb
Host smart-45c3cfac-e6be-432f-8585-b418939d1083
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744763361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.1744763361
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.197844426
Short name T102
Test name
Test status
Simulation time 182167000 ps
CPU time 198.39 seconds
Started Mar 10 12:36:10 PM PDT 24
Finished Mar 10 12:39:30 PM PDT 24
Peak memory 269420 kb
Host smart-30672b43-4514-43e8-a829-dac5ffb0bab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197844426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.197844426
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.2084454092
Short name T406
Test name
Test status
Simulation time 192883200 ps
CPU time 33.87 seconds
Started Mar 10 12:36:18 PM PDT 24
Finished Mar 10 12:36:53 PM PDT 24
Peak memory 273060 kb
Host smart-c56a654f-337c-4102-ad7d-ba1edbe0a1f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084454092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.2084454092
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.2430206906
Short name T792
Test name
Test status
Simulation time 1994366200 ps
CPU time 110.03 seconds
Started Mar 10 12:36:31 PM PDT 24
Finished Mar 10 12:38:21 PM PDT 24
Peak memory 280240 kb
Host smart-2135b7ad-04a3-4e34-83d1-911e5ec2e15f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430206906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_ro.2430206906
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.1666421781
Short name T686
Test name
Test status
Simulation time 1499180800 ps
CPU time 137.99 seconds
Started Mar 10 12:36:18 PM PDT 24
Finished Mar 10 12:38:36 PM PDT 24
Peak memory 281344 kb
Host smart-e0a9d57b-7e3e-4c66-8cd5-72bf5b6a7956
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1666421781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.1666421781
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.1800742556
Short name T507
Test name
Test status
Simulation time 1306412500 ps
CPU time 121.12 seconds
Started Mar 10 12:36:16 PM PDT 24
Finished Mar 10 12:38:18 PM PDT 24
Peak memory 281224 kb
Host smart-e9c5d71a-1639-450e-8827-efa3d8fbabfa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800742556 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.1800742556
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.1339453427
Short name T490
Test name
Test status
Simulation time 6230623800 ps
CPU time 403.78 seconds
Started Mar 10 12:36:18 PM PDT 24
Finished Mar 10 12:43:03 PM PDT 24
Peak memory 313768 kb
Host smart-cd4f4246-f95a-482e-925f-437cda43a1f1
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339453427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_rw.1339453427
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.2564596278
Short name T193
Test name
Test status
Simulation time 22573878700 ps
CPU time 532.55 seconds
Started Mar 10 12:36:30 PM PDT 24
Finished Mar 10 12:45:23 PM PDT 24
Peak memory 327628 kb
Host smart-61d7e0c7-c40e-4b3c-9bfd-f6aa3dd6d6ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564596278 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_rw_derr.2564596278
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.2651350993
Short name T19
Test name
Test status
Simulation time 41909500 ps
CPU time 31.23 seconds
Started Mar 10 12:36:21 PM PDT 24
Finished Mar 10 12:36:52 PM PDT 24
Peak memory 273096 kb
Host smart-dec62602-5b3d-4f8a-9a46-d271f0777da2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651350993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.2651350993
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.3023125021
Short name T393
Test name
Test status
Simulation time 27498400 ps
CPU time 30.87 seconds
Started Mar 10 12:36:18 PM PDT 24
Finished Mar 10 12:36:49 PM PDT 24
Peak memory 274072 kb
Host smart-3bb61604-7191-421c-bb36-b350a98ae465
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023125021 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.3023125021
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.1217090437
Short name T584
Test name
Test status
Simulation time 3233294800 ps
CPU time 572.75 seconds
Started Mar 10 12:36:18 PM PDT 24
Finished Mar 10 12:45:51 PM PDT 24
Peak memory 312324 kb
Host smart-38abd28e-4ae3-4707-a955-3f1871023c85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217090437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s
err.1217090437
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.1540946750
Short name T594
Test name
Test status
Simulation time 1482513200 ps
CPU time 70.28 seconds
Started Mar 10 12:36:30 PM PDT 24
Finished Mar 10 12:37:41 PM PDT 24
Peak memory 262476 kb
Host smart-93bc7126-17f1-4c45-8615-7c35a23ef002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540946750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.1540946750
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.2465418358
Short name T786
Test name
Test status
Simulation time 27935700 ps
CPU time 97.25 seconds
Started Mar 10 12:36:14 PM PDT 24
Finished Mar 10 12:37:51 PM PDT 24
Peak memory 275788 kb
Host smart-6c8b9c17-22f0-4fe3-8011-51952977706d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465418358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2465418358
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.3835264320
Short name T484
Test name
Test status
Simulation time 11872695800 ps
CPU time 153.6 seconds
Started Mar 10 12:36:17 PM PDT 24
Finished Mar 10 12:38:51 PM PDT 24
Peak memory 264752 kb
Host smart-0100e51e-8930-4711-8030-7ff69132aedf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835264320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.flash_ctrl_wo.3835264320
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.2327665310
Short name T532
Test name
Test status
Simulation time 15426900 ps
CPU time 15.62 seconds
Started Mar 10 12:39:34 PM PDT 24
Finished Mar 10 12:39:50 PM PDT 24
Peak memory 274316 kb
Host smart-9c4a2ffe-8a28-420e-a49d-b30b2a766868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327665310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.2327665310
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.2709060255
Short name T1087
Test name
Test status
Simulation time 76358100 ps
CPU time 135.51 seconds
Started Mar 10 12:39:33 PM PDT 24
Finished Mar 10 12:41:49 PM PDT 24
Peak memory 259112 kb
Host smart-d594d887-46f0-4703-ba41-9695c17c0b0c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709060255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.2709060255
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.3870491987
Short name T1085
Test name
Test status
Simulation time 29641400 ps
CPU time 13.27 seconds
Started Mar 10 12:39:42 PM PDT 24
Finished Mar 10 12:39:56 PM PDT 24
Peak memory 274844 kb
Host smart-5086cdcf-c0db-4cef-9d81-ce217960e476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870491987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.3870491987
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.1218146272
Short name T820
Test name
Test status
Simulation time 41624000 ps
CPU time 134.78 seconds
Started Mar 10 12:39:41 PM PDT 24
Finished Mar 10 12:41:56 PM PDT 24
Peak memory 259244 kb
Host smart-a49237c3-3398-45cb-9d4d-fc5b253b3650
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218146272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.1218146272
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.1705143733
Short name T181
Test name
Test status
Simulation time 63738500 ps
CPU time 15.74 seconds
Started Mar 10 12:39:40 PM PDT 24
Finished Mar 10 12:39:56 PM PDT 24
Peak memory 274840 kb
Host smart-8e6c047a-ff8d-4ca1-ad81-31b37bff6e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705143733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1705143733
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.353549630
Short name T503
Test name
Test status
Simulation time 28022900 ps
CPU time 16.08 seconds
Started Mar 10 12:39:40 PM PDT 24
Finished Mar 10 12:39:57 PM PDT 24
Peak memory 273988 kb
Host smart-dae6b7bd-a5bd-4b03-b128-e07ffe5670c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353549630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.353549630
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.1985265719
Short name T768
Test name
Test status
Simulation time 57204400 ps
CPU time 109.84 seconds
Started Mar 10 12:39:42 PM PDT 24
Finished Mar 10 12:41:32 PM PDT 24
Peak memory 258988 kb
Host smart-49f43d18-0644-4edb-a92f-4fa74994db6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985265719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.1985265719
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.4253510833
Short name T417
Test name
Test status
Simulation time 40842000 ps
CPU time 15.95 seconds
Started Mar 10 12:39:37 PM PDT 24
Finished Mar 10 12:39:53 PM PDT 24
Peak memory 273956 kb
Host smart-6c3ea18c-4616-4bf2-85d1-b2853812011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253510833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.4253510833
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.4131748056
Short name T883
Test name
Test status
Simulation time 221583500 ps
CPU time 131.47 seconds
Started Mar 10 12:39:39 PM PDT 24
Finished Mar 10 12:41:51 PM PDT 24
Peak memory 258988 kb
Host smart-635c3bff-c991-4427-824d-960cbd991ffb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131748056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.4131748056
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.412067284
Short name T552
Test name
Test status
Simulation time 85405800 ps
CPU time 15.87 seconds
Started Mar 10 12:39:43 PM PDT 24
Finished Mar 10 12:40:00 PM PDT 24
Peak memory 273928 kb
Host smart-3d8b415e-1aec-436d-b8dc-2f809390f48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412067284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.412067284
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.3883747901
Short name T692
Test name
Test status
Simulation time 189829700 ps
CPU time 109.06 seconds
Started Mar 10 12:39:39 PM PDT 24
Finished Mar 10 12:41:28 PM PDT 24
Peak memory 259196 kb
Host smart-db8f178b-7438-4339-b23c-e6e51a352b57
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883747901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.3883747901
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.755706428
Short name T628
Test name
Test status
Simulation time 99374600 ps
CPU time 13.58 seconds
Started Mar 10 12:39:38 PM PDT 24
Finished Mar 10 12:39:51 PM PDT 24
Peak memory 273868 kb
Host smart-a782c04a-eb3c-4de5-b44b-05216201a334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755706428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.755706428
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.1031325180
Short name T703
Test name
Test status
Simulation time 72747000 ps
CPU time 133.13 seconds
Started Mar 10 12:39:40 PM PDT 24
Finished Mar 10 12:41:54 PM PDT 24
Peak memory 259256 kb
Host smart-b8dbc6da-b216-4653-8e48-abb9b5090b06
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031325180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.1031325180
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.1258038348
Short name T180
Test name
Test status
Simulation time 22598000 ps
CPU time 13.56 seconds
Started Mar 10 12:39:40 PM PDT 24
Finished Mar 10 12:39:54 PM PDT 24
Peak memory 273932 kb
Host smart-abd4231f-def8-429b-9506-7fce0d4438ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258038348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.1258038348
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.3781027628
Short name T938
Test name
Test status
Simulation time 83566500 ps
CPU time 111.23 seconds
Started Mar 10 12:39:38 PM PDT 24
Finished Mar 10 12:41:29 PM PDT 24
Peak memory 258848 kb
Host smart-e1b8b620-a406-4e79-a9d9-84bc2167e750
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781027628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.3781027628
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.636989591
Short name T525
Test name
Test status
Simulation time 16106300 ps
CPU time 16.11 seconds
Started Mar 10 12:39:38 PM PDT 24
Finished Mar 10 12:39:54 PM PDT 24
Peak memory 273976 kb
Host smart-336a4afe-66bf-4f4f-8a39-a021ef02be81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636989591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.636989591
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.2813731411
Short name T621
Test name
Test status
Simulation time 179804200 ps
CPU time 129.75 seconds
Started Mar 10 12:39:39 PM PDT 24
Finished Mar 10 12:41:49 PM PDT 24
Peak memory 259040 kb
Host smart-f60826c0-7294-4e95-8f2c-29f5f675bc26
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813731411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.2813731411
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.2900513831
Short name T401
Test name
Test status
Simulation time 13501200 ps
CPU time 15.55 seconds
Started Mar 10 12:39:37 PM PDT 24
Finished Mar 10 12:39:53 PM PDT 24
Peak memory 274008 kb
Host smart-56daa65c-80c4-477e-b61c-6028cdfe919a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900513831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2900513831
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.1467214908
Short name T1021
Test name
Test status
Simulation time 41590300 ps
CPU time 110.64 seconds
Started Mar 10 12:39:53 PM PDT 24
Finished Mar 10 12:41:43 PM PDT 24
Peak memory 262972 kb
Host smart-0526a993-d99c-459b-ac0e-5d7c597142d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467214908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.1467214908
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.597431151
Short name T677
Test name
Test status
Simulation time 115678300 ps
CPU time 13.57 seconds
Started Mar 10 12:36:30 PM PDT 24
Finished Mar 10 12:36:43 PM PDT 24
Peak memory 264348 kb
Host smart-d6115842-81f8-4bef-853f-0d304419749c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597431151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.597431151
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.1018660125
Short name T48
Test name
Test status
Simulation time 14585800 ps
CPU time 13.14 seconds
Started Mar 10 12:36:25 PM PDT 24
Finished Mar 10 12:36:38 PM PDT 24
Peak memory 274832 kb
Host smart-154c0d6c-eaf0-41a2-b3f8-fa9195859c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018660125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.1018660125
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.1696072210
Short name T971
Test name
Test status
Simulation time 10588800 ps
CPU time 22.03 seconds
Started Mar 10 12:36:28 PM PDT 24
Finished Mar 10 12:36:50 PM PDT 24
Peak memory 272812 kb
Host smart-6145d837-d503-4c85-9ed7-52875575cb50
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696072210 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.1696072210
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.271145248
Short name T818
Test name
Test status
Simulation time 35004588200 ps
CPU time 2306.22 seconds
Started Mar 10 12:36:21 PM PDT 24
Finished Mar 10 01:14:48 PM PDT 24
Peak memory 264060 kb
Host smart-2ef72c11-9afd-40d8-b0fb-9b04e517beb0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271145248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_erro
r_mp.271145248
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.464149878
Short name T574
Test name
Test status
Simulation time 528960100 ps
CPU time 1034.39 seconds
Started Mar 10 12:36:24 PM PDT 24
Finished Mar 10 12:53:39 PM PDT 24
Peak memory 272832 kb
Host smart-27ab7fc2-a135-4d1c-a288-85e137369062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464149878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.464149878
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.3917796154
Short name T50
Test name
Test status
Simulation time 369308000 ps
CPU time 24.38 seconds
Started Mar 10 12:36:24 PM PDT 24
Finished Mar 10 12:36:48 PM PDT 24
Peak memory 264632 kb
Host smart-36db7175-0155-4bc8-bd00-bd83e9b7b57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917796154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.3917796154
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.2810572196
Short name T780
Test name
Test status
Simulation time 15189000 ps
CPU time 13.2 seconds
Started Mar 10 12:36:29 PM PDT 24
Finished Mar 10 12:36:42 PM PDT 24
Peak memory 264804 kb
Host smart-e8d7f145-689e-49af-aeec-226f49da8c79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810572196 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.2810572196
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.1671581774
Short name T682
Test name
Test status
Simulation time 2636240700 ps
CPU time 63.04 seconds
Started Mar 10 12:36:22 PM PDT 24
Finished Mar 10 12:37:26 PM PDT 24
Peak memory 261588 kb
Host smart-0af9586b-f950-4f9d-a732-bd365acd9e52
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671581774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.1671581774
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.3457915508
Short name T183
Test name
Test status
Simulation time 2412625000 ps
CPU time 202.74 seconds
Started Mar 10 12:36:28 PM PDT 24
Finished Mar 10 12:39:52 PM PDT 24
Peak memory 294180 kb
Host smart-1e72ddbe-7876-4516-b17f-06780bb2c770
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457915508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.3457915508
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1759427959
Short name T517
Test name
Test status
Simulation time 46324452900 ps
CPU time 242.01 seconds
Started Mar 10 12:36:26 PM PDT 24
Finished Mar 10 12:40:28 PM PDT 24
Peak memory 284320 kb
Host smart-2350d2b4-118b-4bfd-b0dd-5dbedf663151
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759427959 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.1759427959
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.3146164220
Short name T23
Test name
Test status
Simulation time 7400109200 ps
CPU time 72.34 seconds
Started Mar 10 12:36:28 PM PDT 24
Finished Mar 10 12:37:40 PM PDT 24
Peak memory 264448 kb
Host smart-55a7e8f5-6120-4cc4-a66f-29818d8c972b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146164220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.3146164220
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.3998845840
Short name T511
Test name
Test status
Simulation time 110439827000 ps
CPU time 355.27 seconds
Started Mar 10 12:36:26 PM PDT 24
Finished Mar 10 12:42:22 PM PDT 24
Peak memory 264588 kb
Host smart-df35b8f4-242d-4b28-82af-ece783d4a113
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399
8845840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.3998845840
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.2159992363
Short name T864
Test name
Test status
Simulation time 2209233000 ps
CPU time 87.7 seconds
Started Mar 10 12:36:22 PM PDT 24
Finished Mar 10 12:37:50 PM PDT 24
Peak memory 259128 kb
Host smart-38c341a0-89b8-4951-a04a-8d8ae5ec5b05
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159992363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.2159992363
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.2072431404
Short name T579
Test name
Test status
Simulation time 21784300 ps
CPU time 13.59 seconds
Started Mar 10 12:36:27 PM PDT 24
Finished Mar 10 12:36:42 PM PDT 24
Peak memory 264816 kb
Host smart-22549793-2b1d-47b9-ae44-569ddc34ac1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072431404 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.2072431404
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.1043049701
Short name T21
Test name
Test status
Simulation time 5052701200 ps
CPU time 145.06 seconds
Started Mar 10 12:36:21 PM PDT 24
Finished Mar 10 12:38:46 PM PDT 24
Peak memory 264704 kb
Host smart-41afa80c-cb83-4f12-8554-01095d204c73
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043049701 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.1043049701
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.1959245992
Short name T1009
Test name
Test status
Simulation time 76094800 ps
CPU time 113.22 seconds
Started Mar 10 12:36:21 PM PDT 24
Finished Mar 10 12:38:15 PM PDT 24
Peak memory 263024 kb
Host smart-8526a5f8-b33d-4f6c-87a3-24d14a32c677
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959245992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.1959245992
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.964008331
Short name T596
Test name
Test status
Simulation time 2506388200 ps
CPU time 427.38 seconds
Started Mar 10 12:36:22 PM PDT 24
Finished Mar 10 12:43:30 PM PDT 24
Peak memory 264596 kb
Host smart-1b90f83f-79ad-4b87-b260-c1bea821be8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=964008331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.964008331
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.172171597
Short name T781
Test name
Test status
Simulation time 1576696800 ps
CPU time 36.65 seconds
Started Mar 10 12:36:28 PM PDT 24
Finished Mar 10 12:37:05 PM PDT 24
Peak memory 264744 kb
Host smart-a3063969-989a-4eab-be39-cbc6914a9745
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172171597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_rese
t.172171597
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.3128362477
Short name T1037
Test name
Test status
Simulation time 38129200 ps
CPU time 169.55 seconds
Started Mar 10 12:36:22 PM PDT 24
Finished Mar 10 12:39:12 PM PDT 24
Peak memory 268536 kb
Host smart-00cf70a6-df82-4ec5-ab1c-09f2c8c2e5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128362477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3128362477
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.2254791979
Short name T767
Test name
Test status
Simulation time 560601200 ps
CPU time 35.53 seconds
Started Mar 10 12:36:27 PM PDT 24
Finished Mar 10 12:37:04 PM PDT 24
Peak memory 273064 kb
Host smart-ac75ce24-8342-424c-a452-d5ab641728ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254791979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.2254791979
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.1246976529
Short name T194
Test name
Test status
Simulation time 2586537500 ps
CPU time 111.49 seconds
Started Mar 10 12:36:27 PM PDT 24
Finished Mar 10 12:38:20 PM PDT 24
Peak memory 288408 kb
Host smart-ab311958-617d-4b92-96a0-95c9a109dfe1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246976529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_ro.1246976529
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.636996520
Short name T205
Test name
Test status
Simulation time 508897200 ps
CPU time 103.75 seconds
Started Mar 10 12:36:26 PM PDT 24
Finished Mar 10 12:38:10 PM PDT 24
Peak memory 281172 kb
Host smart-dffc468b-1a8f-4ca4-8711-34041fa42e31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
636996520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.636996520
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.1919654858
Short name T852
Test name
Test status
Simulation time 4006644200 ps
CPU time 132.76 seconds
Started Mar 10 12:36:27 PM PDT 24
Finished Mar 10 12:38:41 PM PDT 24
Peak memory 281236 kb
Host smart-7a70628f-d383-44e7-945e-8a24dc34c1cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919654858 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.1919654858
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.3797928239
Short name T539
Test name
Test status
Simulation time 12395346200 ps
CPU time 474.26 seconds
Started Mar 10 12:36:27 PM PDT 24
Finished Mar 10 12:44:22 PM PDT 24
Peak memory 313796 kb
Host smart-c8fb2e9d-f193-4b9b-902d-a1b1efe93ec8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797928239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_rw.3797928239
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.3350949803
Short name T794
Test name
Test status
Simulation time 99176100 ps
CPU time 31 seconds
Started Mar 10 12:36:32 PM PDT 24
Finished Mar 10 12:37:03 PM PDT 24
Peak memory 271924 kb
Host smart-9f0839a1-c409-4527-87c7-c0ec5b62a55f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350949803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.3350949803
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.2163782370
Short name T710
Test name
Test status
Simulation time 71630300 ps
CPU time 31.33 seconds
Started Mar 10 12:36:28 PM PDT 24
Finished Mar 10 12:37:00 PM PDT 24
Peak memory 273996 kb
Host smart-1c00792f-8e05-461a-928b-4dd70a4e1334
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163782370 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.2163782370
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.83868617
Short name T212
Test name
Test status
Simulation time 3703372500 ps
CPU time 516.49 seconds
Started Mar 10 12:36:28 PM PDT 24
Finished Mar 10 12:45:05 PM PDT 24
Peak memory 313988 kb
Host smart-9e98a26c-62f5-4fe7-bba6-967e8f454907
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83868617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash
_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_ser
r.83868617
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.1505611178
Short name T581
Test name
Test status
Simulation time 3620758400 ps
CPU time 67.7 seconds
Started Mar 10 12:36:28 PM PDT 24
Finished Mar 10 12:37:37 PM PDT 24
Peak memory 263616 kb
Host smart-8c665619-67c7-4e52-b502-161dbfaf7d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505611178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1505611178
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.3657020051
Short name T952
Test name
Test status
Simulation time 89502000 ps
CPU time 124.51 seconds
Started Mar 10 12:36:30 PM PDT 24
Finished Mar 10 12:38:35 PM PDT 24
Peak memory 276972 kb
Host smart-7bcec298-bfcf-4219-96af-83af919c7ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657020051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3657020051
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.1177930341
Short name T422
Test name
Test status
Simulation time 2913251600 ps
CPU time 122.52 seconds
Started Mar 10 12:36:25 PM PDT 24
Finished Mar 10 12:38:28 PM PDT 24
Peak memory 264732 kb
Host smart-18ee2792-44b9-4228-80b9-9310c77a9aaf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177930341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.flash_ctrl_wo.1177930341
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2215300353
Short name T518
Test name
Test status
Simulation time 301265200 ps
CPU time 13.94 seconds
Started Mar 10 12:36:38 PM PDT 24
Finished Mar 10 12:36:52 PM PDT 24
Peak memory 264432 kb
Host smart-5ad46235-0d8f-497a-a509-058c7c56e459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215300353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
215300353
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.1594927024
Short name T1095
Test name
Test status
Simulation time 63847200 ps
CPU time 13.25 seconds
Started Mar 10 12:36:38 PM PDT 24
Finished Mar 10 12:36:52 PM PDT 24
Peak memory 274812 kb
Host smart-b78fd627-d4f8-4964-bc4e-d25e3f6e068a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594927024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1594927024
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.665491365
Short name T222
Test name
Test status
Simulation time 38528900 ps
CPU time 21.79 seconds
Started Mar 10 12:36:39 PM PDT 24
Finished Mar 10 12:37:01 PM PDT 24
Peak memory 279656 kb
Host smart-d0c66e85-cfe1-46da-86ad-8cad99409ee5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665491365 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.665491365
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.185364896
Short name T674
Test name
Test status
Simulation time 19537539500 ps
CPU time 2467.86 seconds
Started Mar 10 12:36:34 PM PDT 24
Finished Mar 10 01:17:43 PM PDT 24
Peak memory 263256 kb
Host smart-5d6a841d-960c-4e20-a676-0094e772cc2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185364896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_erro
r_mp.185364896
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.610599615
Short name T804
Test name
Test status
Simulation time 1228529600 ps
CPU time 831.23 seconds
Started Mar 10 12:36:32 PM PDT 24
Finished Mar 10 12:50:23 PM PDT 24
Peak memory 264668 kb
Host smart-970ea332-366e-4a06-83be-db24a35f7d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610599615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.610599615
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.1527151200
Short name T1090
Test name
Test status
Simulation time 700055200 ps
CPU time 26.65 seconds
Started Mar 10 12:36:34 PM PDT 24
Finished Mar 10 12:37:02 PM PDT 24
Peak memory 264748 kb
Host smart-c9cbe984-7032-46da-86df-2d2bc187f6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527151200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.1527151200
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.3465428977
Short name T281
Test name
Test status
Simulation time 106562200 ps
CPU time 13.67 seconds
Started Mar 10 12:36:36 PM PDT 24
Finished Mar 10 12:36:50 PM PDT 24
Peak memory 264836 kb
Host smart-e1991e62-8d51-4cf0-a2a6-57af7e7a1107
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465428977 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.3465428977
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.3902593185
Short name T138
Test name
Test status
Simulation time 80146716700 ps
CPU time 731.96 seconds
Started Mar 10 12:36:31 PM PDT 24
Finished Mar 10 12:48:43 PM PDT 24
Peak memory 262464 kb
Host smart-c88ae556-7381-4b76-8c1f-0e350c14e5d6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902593185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.3902593185
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.610412206
Short name T1047
Test name
Test status
Simulation time 3914134900 ps
CPU time 92.11 seconds
Started Mar 10 12:36:36 PM PDT 24
Finished Mar 10 12:38:08 PM PDT 24
Peak memory 258428 kb
Host smart-65b1dbf4-d222-4c70-82c8-7f122509a25b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610412206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw
_sec_otp.610412206
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.1754144914
Short name T727
Test name
Test status
Simulation time 4732597700 ps
CPU time 183.23 seconds
Started Mar 10 12:36:47 PM PDT 24
Finished Mar 10 12:39:51 PM PDT 24
Peak memory 292796 kb
Host smart-f793dd27-1732-4e71-aad1-e5b3e68a6e5f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754144914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.1754144914
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2807640707
Short name T542
Test name
Test status
Simulation time 69601134000 ps
CPU time 229.64 seconds
Started Mar 10 12:36:39 PM PDT 24
Finished Mar 10 12:40:29 PM PDT 24
Peak memory 284076 kb
Host smart-ff9acc3b-cf14-42d2-a8d1-1a136145f3c8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807640707 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.2807640707
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.3058111606
Short name T740
Test name
Test status
Simulation time 7812938100 ps
CPU time 91.12 seconds
Started Mar 10 12:36:40 PM PDT 24
Finished Mar 10 12:38:11 PM PDT 24
Peak memory 264824 kb
Host smart-4ae8207e-e0ee-485f-8031-91c06419cc8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058111606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.3058111606
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2185640759
Short name T28
Test name
Test status
Simulation time 103562331100 ps
CPU time 390.92 seconds
Started Mar 10 12:36:40 PM PDT 24
Finished Mar 10 12:43:12 PM PDT 24
Peak memory 264696 kb
Host smart-42feacfc-89d3-4c0f-afb6-69b19d4848d3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218
5640759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.2185640759
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.538160083
Short name T905
Test name
Test status
Simulation time 6493134200 ps
CPU time 63.08 seconds
Started Mar 10 12:36:33 PM PDT 24
Finished Mar 10 12:37:38 PM PDT 24
Peak memory 258940 kb
Host smart-0ce2d839-a3bc-49f9-9dd6-433cb56653c3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538160083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.538160083
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.607871210
Short name T550
Test name
Test status
Simulation time 38036600 ps
CPU time 13.37 seconds
Started Mar 10 12:36:37 PM PDT 24
Finished Mar 10 12:36:51 PM PDT 24
Peak memory 264728 kb
Host smart-f0096f5c-e7ec-4f35-baf2-4b3f3634ac9b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607871210 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.607871210
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.3947738566
Short name T91
Test name
Test status
Simulation time 26130833700 ps
CPU time 307.31 seconds
Started Mar 10 12:36:33 PM PDT 24
Finished Mar 10 12:41:42 PM PDT 24
Peak memory 272860 kb
Host smart-828962a5-b13d-4512-9ac9-b072a874abc3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947738566 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.3947738566
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.784454760
Short name T935
Test name
Test status
Simulation time 91945200 ps
CPU time 131.56 seconds
Started Mar 10 12:36:32 PM PDT 24
Finished Mar 10 12:38:44 PM PDT 24
Peak memory 259200 kb
Host smart-445325fb-2aeb-413e-85e4-a14200d54df5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784454760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp
_reset.784454760
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.3744555193
Short name T607
Test name
Test status
Simulation time 726240700 ps
CPU time 299.86 seconds
Started Mar 10 12:36:33 PM PDT 24
Finished Mar 10 12:41:35 PM PDT 24
Peak memory 260808 kb
Host smart-974193d9-360e-479b-b5e0-079a8a028be4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3744555193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.3744555193
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.3246176658
Short name T226
Test name
Test status
Simulation time 21379000 ps
CPU time 13.45 seconds
Started Mar 10 12:36:47 PM PDT 24
Finished Mar 10 12:37:00 PM PDT 24
Peak memory 264632 kb
Host smart-75de4e0a-0678-42ee-ad69-f0ff0d505ddd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246176658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.3246176658
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.3570418498
Short name T108
Test name
Test status
Simulation time 262617700 ps
CPU time 1219.09 seconds
Started Mar 10 12:36:35 PM PDT 24
Finished Mar 10 12:56:55 PM PDT 24
Peak memory 284704 kb
Host smart-61ca5f04-28be-426e-9cfc-1b70495a04fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570418498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.3570418498
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.3389197138
Short name T604
Test name
Test status
Simulation time 59739100 ps
CPU time 32.13 seconds
Started Mar 10 12:36:39 PM PDT 24
Finished Mar 10 12:37:11 PM PDT 24
Peak memory 274124 kb
Host smart-15d7eba3-f690-48b8-9319-edb1c9116f43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389197138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.3389197138
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.68743766
Short name T642
Test name
Test status
Simulation time 2330213400 ps
CPU time 94.99 seconds
Started Mar 10 12:36:31 PM PDT 24
Finished Mar 10 12:38:06 PM PDT 24
Peak memory 281220 kb
Host smart-2e877f8c-7cca-4689-aaeb-41e81201fdc6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68743766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.flash_ctrl_ro.68743766
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.3832872856
Short name T173
Test name
Test status
Simulation time 469970800 ps
CPU time 108.2 seconds
Started Mar 10 12:36:31 PM PDT 24
Finished Mar 10 12:38:20 PM PDT 24
Peak memory 281164 kb
Host smart-8d6972bc-5d89-4b0b-97be-503d3e0f5778
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3832872856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.3832872856
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.3947906958
Short name T377
Test name
Test status
Simulation time 2685622600 ps
CPU time 109 seconds
Started Mar 10 12:36:31 PM PDT 24
Finished Mar 10 12:38:20 PM PDT 24
Peak memory 281232 kb
Host smart-159f2bf5-3774-4bf7-972a-87d4f6529670
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947906958 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.3947906958
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.3458772104
Short name T721
Test name
Test status
Simulation time 20317592400 ps
CPU time 426.6 seconds
Started Mar 10 12:36:32 PM PDT 24
Finished Mar 10 12:43:39 PM PDT 24
Peak memory 308600 kb
Host smart-6db774ee-aef8-4806-819f-063272edbc02
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458772104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct
rl_rw.3458772104
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.1573649490
Short name T843
Test name
Test status
Simulation time 3013601200 ps
CPU time 590.96 seconds
Started Mar 10 12:36:41 PM PDT 24
Finished Mar 10 12:46:32 PM PDT 24
Peak memory 320604 kb
Host smart-ce2c4ecb-6a94-4f4b-91f4-36d55bf82dff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573649490 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_rw_derr.1573649490
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.1534449670
Short name T659
Test name
Test status
Simulation time 771435200 ps
CPU time 33.31 seconds
Started Mar 10 12:36:37 PM PDT 24
Finished Mar 10 12:37:11 PM PDT 24
Peak memory 265928 kb
Host smart-9453f9b3-3834-4624-bebf-0361d4335aac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534449670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.1534449670
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.4169575339
Short name T669
Test name
Test status
Simulation time 75941200 ps
CPU time 30.58 seconds
Started Mar 10 12:36:40 PM PDT 24
Finished Mar 10 12:37:11 PM PDT 24
Peak memory 265800 kb
Host smart-ddf8fe90-1e4c-4290-ab62-6d773bd1cb6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169575339 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.4169575339
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.2536830076
Short name T504
Test name
Test status
Simulation time 3316315900 ps
CPU time 590.11 seconds
Started Mar 10 12:36:34 PM PDT 24
Finished Mar 10 12:46:25 PM PDT 24
Peak memory 319368 kb
Host smart-8feef069-6208-420d-9e4b-4f5adfddc1a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536830076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s
err.2536830076
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.646644700
Short name T30
Test name
Test status
Simulation time 493087500 ps
CPU time 60.04 seconds
Started Mar 10 12:36:38 PM PDT 24
Finished Mar 10 12:37:39 PM PDT 24
Peak memory 261540 kb
Host smart-ba27dba0-5f51-4077-b141-048e977155d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646644700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.646644700
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.4238921096
Short name T887
Test name
Test status
Simulation time 47000300 ps
CPU time 170.24 seconds
Started Mar 10 12:36:31 PM PDT 24
Finished Mar 10 12:39:21 PM PDT 24
Peak memory 277260 kb
Host smart-3b89256a-8773-481e-8daf-605edee19d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238921096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.4238921096
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.2356095913
Short name T913
Test name
Test status
Simulation time 7586703400 ps
CPU time 183.9 seconds
Started Mar 10 12:36:33 PM PDT 24
Finished Mar 10 12:39:39 PM PDT 24
Peak memory 264580 kb
Host smart-a674a75d-c17f-4fd8-a830-cc3e095bab07
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356095913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.flash_ctrl_wo.2356095913
Directory /workspace/9.flash_ctrl_wo/latest
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