Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.51		100.00	97.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	96.36	100.00	83.96		100.00	97.83	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	97.87	100.00	91.51		100.00	97.83	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36	100.00	83.96		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.55	97.91	92.91	96.90	100.00	99.62	97.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.91	100.00	98.46	95.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	91.95	75.93	91.89			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.78	99.16	93.53	100.00		100.00	96.23
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.51		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.06	97.91	93.28	100.00	100.00	99.24	97.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	99.49	100.00	96.92	100.00	100.00	100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	97.22	100.00	88.89		100.00	100.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.55	99.16	93.09	100.00		99.27	96.23
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	202	4	4	100.00
ALWAYS	214	6	6	100.00
ALWAYS	228	6	6	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	29	29	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	585	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
164	3	3
195	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
			MISSING_ELSE
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
276	1	1
279	1	1
280	1	1
281	1	1
286	1	1
316	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
330	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
			MISSING_ELSE
373	1	1
374	1	1
387	1	1
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
414	1	1
427	1	1
521	1	1
548	1	1
549	1	1
550	1	1
551	1	1
553	1	1
554	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
566	1	1
583	1	1
584	1	1
585	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20
1	1	Covered	T8,T125,T11

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20
1	1	Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T8,T125,T11

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T20

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T7,T8
1	0	1	Covered	T4,T5,T20
1	1	0	Covered	T70,T71,T72
1	1	1	Covered	T4,T5,T20

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T9
1	1	Covered	T4,T5,T20

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20
1	1	Covered	T4,T5,T20

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T24,T73,T74
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T9

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T22,T33
1	1	Covered	T4,T5,T6

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T70,T71,T72
1	0	Covered	T80,T222

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T80,T222

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T70,T71,T72

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T22,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T22,T33

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T67,T26
1	0	Covered	T6,T22,T33

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Not Covered
1	1	Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T29
1	0	Covered	T18,T19,T29

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T81

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T81

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T81

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T81

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	340	Covered	T6,T22,T33
StCtrlProg	338	Covered	T4,T5,T6
StCtrlRead	336	Covered	T1,T2,T3
StDisable	334	Covered	T7,T13,T14
StIdle	348	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	368	Covered	T6,T22,T33
StCtrlProg->StIdle	358	Covered	T4,T5,T6
StCtrlRead->StIdle	348	Covered	T1,T2,T3
StIdle->StCtrl	340	Covered	T6,T22,T33
StIdle->StCtrlProg	338	Covered	T4,T5,T6
StIdle->StCtrlRead	336	Covered	T1,T2,T3
StIdle->StDisable	334	Covered	T7,T13,T14

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	316	2	2	100.00
TERNARY	391	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	430	2	1	50.00
IF	151	4	4	100.00
IF	164	2	2	100.00
IF	202	3	3	100.00
IF	214	4	4	100.00
IF	228	4	4	100.00
CASE	330	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	316	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T20,T81
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T20,T81
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	430	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if (ctrl_rsp_vld)
-3-:	155	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if ((!rst_ni))
-2-:	204	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T8,T125,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	216	if ((host_outstanding == '0))
-3-:	218	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T15,T16
0	0	0	Covered	T4,T5,T20

	LineNo.	Expression
-1-:	228	if ((!rst_ni))
-2-:	230	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	232	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T15,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	case (state_q)
-2-:	333	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	335	if ((ctrl_gnt && rd_i))
-4-:	337	if ((ctrl_gnt && prog_i))
-5-:	339	if (ctrl_gnt)
-6-:	346	if (rd_stage_data_valid)
-7-:	356	if (prog_ack)
-8-:	366	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T7,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T4,T5,T6
StIdle	0	0	0	1	-	-	-	Covered	T6,T22,T33
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T4,T5,T6
StCtrlProg	-	-	-	-	-	0	-	Covered	T4,T5,T6
StCtrl	-	-	-	-	-	-	1	Covered	T6,T22,T33
StCtrl	-	-	-	-	-	-	0	Covered	T6,T22,T33
StDisable	-	-	-	-	-	-	-	Covered	T7,T13,T14
default	-	-	-	-	-	-	-	Covered	T18,T11,T19

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	815039054	3749685	0	0
CtrlPrio_A	815039054	3749685	0	0
HostTransIdleChk_A	815039054	39409736	0	0
NoRemainder_A	1964	1964	0	0
OneHotReqs_A	815039054	813316946	0	0
Pow2Multiple_A	1964	1964	0	0
RdTxnCheck_A	814671108	812949000	0	0
u_state_regs_A	815039054	813316946	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	3749685	0	0
T8	568	6	0	0
T9	298707	17203	0	0
T13	1182	0	0	0
T14	3825	0	0	0
T17	3446	0	0	0
T22	208604	0	0	0
T23	27729	0	0	0
T24	0	16	0	0
T32	29518	0	0	0
T33	12304	0	0	0
T42	0	79413	0	0
T43	0	81576	0	0
T44	0	86726	0	0
T46	3091	0	0	0
T48	1158	0	0	0
T49	2920	0	0	0
T57	10017	0	0	0
T60	1413	0	0	0
T69	6001	0	0	0
T75	0	13792	0	0
T76	2035	0	0	0
T94	0	3025	0	0
T96	1838	0	0	0
T97	0	3295	0	0
T100	0	9592	0	0
T102	1538	0	0	0
T103	3795	0	0	0
T104	1048	0	0	0
T202	0	89919	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	3749685	0	0
T8	568	6	0	0
T9	298707	17203	0	0
T13	1182	0	0	0
T14	3825	0	0	0
T17	3446	0	0	0
T22	208604	0	0	0
T23	27729	0	0	0
T24	0	16	0	0
T32	29518	0	0	0
T33	12304	0	0	0
T42	0	79413	0	0
T43	0	81576	0	0
T44	0	86726	0	0
T46	3091	0	0	0
T48	1158	0	0	0
T49	2920	0	0	0
T57	10017	0	0	0
T60	1413	0	0	0
T69	6001	0	0	0
T75	0	13792	0	0
T76	2035	0	0	0
T94	0	3025	0	0
T96	1838	0	0	0
T97	0	3295	0	0
T100	0	9592	0	0
T102	1538	0	0	0
T103	3795	0	0	0
T104	1048	0	0	0
T202	0	89919	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	39409736	0	0
T4	4628	80	0	0
T5	6934	10	0	0
T6	130964	0	0	0
T7	1180	41	0	0
T8	1136	88	0	0
T9	0	147297	0	0
T20	3388	12	0	0
T21	2678	0	0	0
T22	417208	0	0	0
T23	0	501	0	0
T32	59036	611	0	0
T33	0	98	0	0
T34	0	8	0	0
T46	0	24	0	0
T48	2316	0	0	0
T57	0	359	0	0
T60	0	12	0	0
T69	0	151	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1964	1964	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	813316946	0	0
T1	2142	1958	0	0
T2	2250	1740	0	0
T3	2538	2080	0	0
T4	4628	4492	0	0
T5	6934	6632	0	0
T6	130964	130852	0	0
T7	1180	1022	0	0
T8	1136	960	0	0
T20	3388	3068	0	0
T21	2678	2498	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1964	1964	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	814671108	812949000	0	0
T1	2142	1958	0	0
T2	2250	1740	0	0
T3	2538	2080	0	0
T4	4628	4492	0	0
T5	6934	6632	0	0
T6	130964	130852	0	0
T7	1180	1022	0	0
T8	1136	960	0	0
T20	3388	3068	0	0
T21	2678	2498	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	813316946	0	0
T1	2142	1958	0	0
T2	2250	1740	0	0
T3	2538	2080	0	0
T4	4628	4492	0	0
T5	6934	6632	0	0
T6	130964	130852	0	0
T7	1180	1022	0	0
T8	1136	960	0	0
T20	3388	3068	0	0
T21	2678	2498	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	202	4	4	100.00
ALWAYS	214	6	6	100.00
ALWAYS	228	6	6	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	29	29	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	585	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
164	3	3
195	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
			MISSING_ELSE
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
276	1	1
279	1	1
280	1	1
281	1	1
286	1	1
316	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
330	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
			MISSING_ELSE
373	1	1
374	1	1
387	1	1
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
414	1	1
427	1	1
521	1	1
548	1	1
549	1	1
550	1	1
551	1	1
553	1	1
554	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
566	1	1
583	1	1
584	1	1
585	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	89	83.96
Logical	106	89	83.96
Non-Logical	0	0
Event	0	0

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T32
1	1	Not Covered

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T8,T32,T22
1	0	Covered	T4,T8,T32
1	1	Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T8,T32
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T32
1	0	Covered	T8,T32,T22
1	1	Covered	T1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T8,T32
1	Covered	T1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T8,T32
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T32

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T8,T32
1	0	1	Covered	T4,T8,T32
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T32

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T57
1	1	Covered	T4,T8,T32

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T32,T22,T23
1	0	Covered	T4,T8,T32
1	1	Covered	T4,T8,T32

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T32,T22
1	1	Covered	T4,T8,T32

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T32
1	0	Covered	T8,T32,T22
1	1	Covered	T8,T9,T69

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T32,T22
1	1	Covered	T32,T22,T23

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T22,T49,T69
1	1	Covered	T8,T32,T22

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T32,T22
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T32
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T32,T22
1	1	Covered	T32,T22,T23

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T32,T22,T23
1	1	Covered	T8,T32,T22

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T22,T33
1	0	Covered	T8,T32,T22
1	1	Covered	T22,T49,T69

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T67,T26
1	0	Covered	T6,T22,T33

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T32
1	0	Not Covered
1	1	Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T32,T22
1	1	Covered	T4,T8,T32

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T32
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T29
1	0	Covered	T18,T19,T29

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T33,T60
1	0	Covered	T81,T46,T82

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T60,T46
1	0	Covered	T81,T46,T82

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T81,T46,T82

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T81,T46,T82

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	340	Covered	T22,T49,T69
StCtrlProg	338	Covered	T8,T32,T22
StCtrlRead	336	Covered	T32,T22,T23
StDisable	334	Covered	T7,T13,T14
StIdle	348	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	368	Covered	T22,T49,T69
StCtrlProg->StIdle	358	Covered	T8,T32,T22
StCtrlRead->StIdle	348	Covered	T32,T22,T23
StIdle->StCtrl	340	Covered	T22,T49,T69
StIdle->StCtrlProg	338	Covered	T8,T32,T22
StIdle->StCtrlRead	336	Covered	T32,T22,T23
StIdle->StDisable	334	Covered	T7,T13,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	316	2	2	100.00
TERNARY	391	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	430	2	1	50.00
IF	151	4	4	100.00
IF	164	2	2	100.00
IF	202	3	3	100.00
IF	214	4	4	100.00
IF	228	4	4	100.00
CASE	330	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	316	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T81,T46,T82
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T81,T46,T82
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	430	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if (ctrl_rsp_vld)
-3-:	155	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T32,T22
0	0	1	Covered	T8,T9,T69
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if ((!rst_ni))
-2-:	204	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T15,T16
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	216	if ((host_outstanding == '0))
-3-:	218	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T15,T16
0	0	0	Covered	T4,T8,T32

	LineNo.	Expression
-1-:	228	if ((!rst_ni))
-2-:	230	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	232	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T15,T16
0	0	0	Covered	T4,T8,T32

	LineNo.	Expression
-1-:	330	case (state_q)
-2-:	333	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	335	if ((ctrl_gnt && rd_i))
-4-:	337	if ((ctrl_gnt && prog_i))
-5-:	339	if (ctrl_gnt)
-6-:	346	if (rd_stage_data_valid)
-7-:	356	if (prog_ack)
-8-:	366	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T7,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T32,T22,T23
StIdle	0	0	1	-	-	-	-	Covered	T8,T32,T22
StIdle	0	0	0	1	-	-	-	Covered	T22,T49,T69
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T32,T22,T23
StCtrlRead	-	-	-	-	0	-	-	Covered	T32,T22,T23
StCtrlProg	-	-	-	-	-	1	-	Covered	T8,T32,T22
StCtrlProg	-	-	-	-	-	0	-	Covered	T8,T32,T22
StCtrl	-	-	-	-	-	-	1	Covered	T22,T49,T69
StCtrl	-	-	-	-	-	-	0	Covered	T22,T49,T69
StDisable	-	-	-	-	-	-	-	Covered	T7,T13,T14
default	-	-	-	-	-	-	-	Covered	T18,T11,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	407519527	1791651	0	0
CtrlPrio_A	407519527	1791651	0	0
HostTransIdleChk_A	407519527	19126103	0	0
NoRemainder_A	982	982	0	0
OneHotReqs_A	407519527	406658473	0	0
Pow2Multiple_A	982	982	0	0
RdTxnCheck_A	407335554	406474500	0	0
u_state_regs_A	407519527	406658473	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	1791651	0	0
T8	568	6	0	0
T9	0	5287	0	0
T13	1182	0	0	0
T14	3825	0	0	0
T22	208604	0	0	0
T23	27729	0	0	0
T32	29518	0	0	0
T33	12304	0	0	0
T42	0	35741	0	0
T43	0	28737	0	0
T44	0	41200	0	0
T48	1158	0	0	0
T49	2920	0	0	0
T75	0	4434	0	0
T94	0	1680	0	0
T97	0	1360	0	0
T100	0	4375	0	0
T104	1048	0	0	0
T202	0	65405	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	1791651	0	0
T8	568	6	0	0
T9	0	5287	0	0
T13	1182	0	0	0
T14	3825	0	0	0
T22	208604	0	0	0
T23	27729	0	0	0
T32	29518	0	0	0
T33	12304	0	0	0
T42	0	35741	0	0
T43	0	28737	0	0
T44	0	41200	0	0
T48	1158	0	0	0
T49	2920	0	0	0
T75	0	4434	0	0
T94	0	1680	0	0
T97	0	1360	0	0
T100	0	4375	0	0
T104	1048	0	0	0
T202	0	65405	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	19126103	0	0
T4	2314	19	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	70	0	0
T9	0	61130	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	0	0	0
T23	0	183	0	0
T32	29518	278	0	0
T33	0	98	0	0
T46	0	24	0	0
T48	1158	0	0	0
T57	0	171	0	0
T60	0	12	0	0
T69	0	151	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407335554	406474500	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	202	4	4	100.00
ALWAYS	214	6	6	100.00
ALWAYS	228	6	6	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	29	29	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	585	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
164	3	3
195	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
			MISSING_ELSE
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
276	1	1
279	1	1
280	1	1
281	1	1
286	1	1
316	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
330	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
			MISSING_ELSE
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
355	1	1
356	1	1
357	1	1
358	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
			MISSING_ELSE
373	1	1
374	1	1
387	1	1
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
414	1	1
427	1	1
521	1	1
548	1	1
549	1	1
550	1	1
551	1	1
553	1	1
554	1	1
555	1	1
556	1	1
557	1	1
558	1	1
559	1	1
566	1	1
583	1	1
584	1	1
585	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	97	91.51
Logical	106	97	91.51
Non-Logical	0	0
Event	0	0

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20
1	1	Covered	T8,T125,T11

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20
1	1	Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T8,T125,T11

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T20
1	Covered	T1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T20

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T7,T8
1	0	1	Covered	T4,T5,T20
1	1	0	Covered	T70,T71,T72
1	1	1	Covered	T4,T5,T20

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T9
1	1	Covered	T4,T5,T20

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20
1	1	Covered	T4,T5,T20

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T24,T73,T74
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T20

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T9,T69

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T4,T32,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T32
1	0	Covered	T6,T22,T33
1	1	Covered	T4,T5,T6

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T70,T71,T72
1	0	Covered	T80,T222

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T80,T222

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T70,T71,T72

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T22,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T22,T33

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T67,T26
1	0	Covered	T6,T22,T33

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Not Covered
1	1	Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T20

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T29
1	0	Covered	T18,T19,T29

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T52

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T52

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T52

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T20,T52

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	340	Covered	T6,T22,T33
StCtrlProg	338	Covered	T4,T5,T6
StCtrlRead	336	Covered	T1,T2,T3
StDisable	334	Covered	T7,T14,T103
StIdle	348	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	368	Covered	T6,T22,T33
StCtrlProg->StIdle	358	Covered	T4,T5,T6
StCtrlRead->StIdle	348	Covered	T1,T2,T3
StIdle->StCtrl	340	Covered	T6,T22,T33
StIdle->StCtrlProg	338	Covered	T4,T5,T6
StIdle->StCtrlRead	336	Covered	T1,T2,T3
StIdle->StDisable	334	Covered	T7,T14,T103

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	316	2	2	100.00
TERNARY	391	2	2	100.00
TERNARY	392	2	2	100.00
TERNARY	393	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	550	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	430	2	1	50.00
IF	151	4	4	100.00
IF	164	2	2	100.00
IF	202	3	3	100.00
IF	214	4	4	100.00
IF	228	4	4	100.00
CASE	330	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	316	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T20,T52
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T20,T52
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	430	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if (ctrl_rsp_vld)
-3-:	155	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T9,T69
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	202	if ((!rst_ni))
-2-:	204	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T8,T125,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	216	if ((host_outstanding == '0))
-3-:	218	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T15,T16
0	0	0	Covered	T4,T5,T20

	LineNo.	Expression
-1-:	228	if ((!rst_ni))
-2-:	230	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	232	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T11,T15,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	case (state_q)
-2-:	333	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	335	if ((ctrl_gnt && rd_i))
-4-:	337	if ((ctrl_gnt && prog_i))
-5-:	339	if (ctrl_gnt)
-6-:	346	if (rd_stage_data_valid)
-7-:	356	if (prog_ack)
-8-:	366	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T7,T13,T14
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T4,T5,T6
StIdle	0	0	0	1	-	-	-	Covered	T6,T22,T33
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T4,T5,T6
StCtrlProg	-	-	-	-	-	0	-	Covered	T4,T5,T6
StCtrl	-	-	-	-	-	-	1	Covered	T6,T22,T33
StCtrl	-	-	-	-	-	-	0	Covered	T6,T22,T33
StDisable	-	-	-	-	-	-	-	Covered	T7,T14,T103
default	-	-	-	-	-	-	-	Covered	T18,T11,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	407519527	1958034	0	0
CtrlPrio_A	407519527	1958034	0	0
HostTransIdleChk_A	407519527	20283633	0	0
NoRemainder_A	982	982	0	0
OneHotReqs_A	407519527	406658473	0	0
Pow2Multiple_A	982	982	0	0
RdTxnCheck_A	407335554	406474500	0	0
u_state_regs_A	407519527	406658473	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	1958034	0	0
T9	298707	11916	0	0
T17	3446	0	0	0
T24	0	16	0	0
T42	0	43672	0	0
T43	0	52839	0	0
T44	0	45526	0	0
T46	3091	0	0	0
T57	10017	0	0	0
T60	1413	0	0	0
T69	6001	0	0	0
T75	0	9358	0	0
T76	2035	0	0	0
T94	0	1345	0	0
T96	1838	0	0	0
T97	0	1935	0	0
T100	0	5217	0	0
T102	1538	0	0	0
T103	3795	0	0	0
T202	0	24514	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	1958034	0	0
T9	298707	11916	0	0
T17	3446	0	0	0
T24	0	16	0	0
T42	0	43672	0	0
T43	0	52839	0	0
T44	0	45526	0	0
T46	3091	0	0	0
T57	10017	0	0	0
T60	1413	0	0	0
T69	6001	0	0	0
T75	0	9358	0	0
T76	2035	0	0	0
T94	0	1345	0	0
T96	1838	0	0	0
T97	0	1935	0	0
T100	0	5217	0	0
T102	1538	0	0	0
T103	3795	0	0	0
T202	0	24514	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	20283633	0	0
T4	2314	61	0	0
T5	3467	10	0	0
T6	65482	0	0	0
T7	590	41	0	0
T8	568	18	0	0
T9	0	86167	0	0
T20	1694	12	0	0
T21	1339	0	0	0
T22	208604	0	0	0
T23	0	318	0	0
T32	29518	333	0	0
T34	0	8	0	0
T48	1158	0	0	0
T57	0	188	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407335554	406474500	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0