Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.50	100.00	90.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.61	100.00	90.45			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	90.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.55	99.16	93.09	100.00		99.27	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	96.15	100.00	84.62			100.00	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	92.48	100.00	72.41	100.00		90.00	100.00
u_rsp_order_fifo	96.55	100.00	82.76	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	100.00	90.45			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.78	99.16	93.53	100.00		100.00	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	96.15	100.00	84.62			100.00	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	96.55	100.00	82.76	100.00		100.00	100.00
u_rsp_order_fifo	96.55	100.00	82.76	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		119	119	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
ALWAYS	354	12	12	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
ALWAYS	562	6	6	100.00
CONT_ASSIGN	572	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
CONT_ASSIGN	615	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
ALWAYS	631	6	6	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	655	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	695	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	701	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
289	1	1
296	1	1
299	1	1
302	1	1
320	1	1
325	1	1
354	1	1
355	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
365	1	1
366	1	1
			MISSING_ELSE
371	1	1
376	1	1
387	1	1
393	1	1
398	1	1
416	1	1
420	1	1
430	1	1
433	1	1
439	1	1
444	1	1
447	1	1
469	1	1
475	1	1
479	1	1
483	1	1
500	1	1
504	1	1
507	1	1
508	1	1
562	1	1
563	1	1
564	1	1
565	1	1
566	1	1
567	1	1
			MISSING_ELSE
572	1	1
576	1	1
579	1	1
586	1	1
590	1	1
598	1	1
615	1	1
620	1	1
625	4	4
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
636	1	1
			MISSING_ELSE
642	1	1
654	1	1
655	1	1
676	1	1
688	1	1
691	1	1
695	1	1
698	1	1
701	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	440	400	90.91
Logical	440	400	90.91
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T91,T61,T100
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T100,T210
1	1	1	Covered	T91,T61,T100

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T60,T61
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T5,T60,T61

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T130,T61,T211
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T130,T61,T211

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T61,T100,T187
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T61,T100,T187

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T6
1	0	1	1	1	1	1	Covered	T152
1	1	0	1	1	1	1	Covered	T20,T46,T52
1	1	1	0	1	1	1	Covered	T4,T5,T6
1	1	1	1	0	1	1	Covered	T61,T100,T187
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T9,T97,T94
1	1	1	1	1	1	1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T5,T22,T60
1	1	1	0	1	1	1	Covered	T4,T5,T6
1	1	1	1	0	1	1	Covered	T61,T100,T187
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T9,T76,T97
1	1	1	1	1	1	1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T22,T52,T78
1	1	1	0	1	1	1	Covered	T4,T5,T6
1	1	1	1	0	1	1	Covered	T61,T211,T100
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T9,T75,T212
1	1	1	1	1	1	1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T22,T52,T78
1	1	1	0	1	1	1	Covered	T4,T5,T6
1	1	1	1	0	1	1	Covered	T61,T100,T187
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T75,T100,T101
1	1	1	1	1	1	1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T97,T94
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T76,T97
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T75,T212
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T75,T100,T101
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T49,T9,T97
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T49,T9,T76
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T33,T49,T9
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T49,T9,T97
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T22,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T20,T22,T46

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T52,T78
0	1	0	Covered	T20,T46,T52
1	0	0	Covered	T25,T67,T26

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T20,T46,T52

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T33,T49
1	1	Covered	T22,T52,T78

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T22,T60
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T22,T60

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T52,T78
0	1	0	Covered	T5,T60,T46
1	0	0	Covered	T25,T67,T26

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T60,T46

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T33,T49
1	1	Covered	T22,T52,T78

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T47,T52
1	0	Covered	T4,T5,T6
1	1	Covered	T22,T47,T52

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T52,T78
0	1	0	Covered	T47,T52,T25
1	0	0	Covered	T25,T67,T26

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T47,T52,T25

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T33,T49
1	1	Covered	T22,T52,T78

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T52,T78
1	0	Covered	T4,T5,T6
1	1	Covered	T22,T52,T78

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T52,T78
0	1	0	Covered	T52,T25,T28
1	0	0	Covered	T25,T67,T26

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T52,T25,T28

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T33,T49
1	1	Covered	T22,T52,T78

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T69
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T69
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       289
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       296
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       299
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T2,T3

 LINE       302
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION (req_o && ack_i)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T69
1	1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       376
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T57,T69
1	0	Covered	T125,T80,T126
1	1	Covered	T1,T2,T3

 LINE       387
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change)
             --------------------------------1-------------------------------   -----------2-----------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T57,T69
1	1	1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match)
             --1--   --------2-------   ----3----   ------4------   ----5---

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	Not Covered
1	1	0	1	1	Covered	T8,T9,T57
1	1	1	0	1	Covered	T125,T126
1	1	1	1	0	Covered	T4,T5,T6
1	1	1	1	1	Covered	T1,T2,T3

 LINE       416
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20
1	1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T22

 LINE       420
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T8

 LINE       430
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       439
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       439
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T32,T23
1	0	Covered	T2,T3,T5

 LINE       444
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T32,T23

 LINE       469
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T39,T124
1	0	Covered	T125,T80,T126
1	1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       479
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T8,T24,T125
1	1	1	Covered	T1,T2,T3

 LINE       483
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T100,T188,T39
1	1	1	Covered	T4,T5,T6

 LINE       500
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       504
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       507
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       508
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       539
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T81
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       564
 EXPRESSION (req_o && ack_i && descramble_i)
             --1--    --2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T188
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       566
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T81
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       576
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T45,T100,T208
1	1	0	Covered	T8,T24,T125
1	1	1	Covered	T1,T2,T3

 LINE       586
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       586
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       590
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       590
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       598
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       598
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       615
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       615
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       615
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       620
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       620
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       620
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T6
1	1	1	0	Covered	T4,T5,T6
1	1	1	1	Covered	T4,T5,T6

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T6
1	1	1	0	Covered	T4,T5,T6
1	1	1	1	Covered	T4,T5,T6

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T6
1	1	1	0	Covered	T4,T5,T6
1	1	1	1	Covered	T4,T5,T6

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T6
1	1	1	0	Covered	T4,T5,T6
1	1	1	1	Covered	T4,T5,T6

 LINE       636
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T100,T210
1	0	Not Covered

 LINE       642
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       655
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       676
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       676
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       688
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       691
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T5

 LINE       691
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       691
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T2,T3,T5

 LINE       691
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T100,T210

 LINE       695
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		40	40	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	296	2	2	100.00
TERNARY	439	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	586	3	3	100.00
TERNARY	590	3	3	100.00
TERNARY	615	3	3	100.00
TERNARY	642	2	2	100.00
TERNARY	676	2	2	100.00
TERNARY	655	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	354	4	4	100.00
IF	562	4	4	100.00
IF	634	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	296	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	439	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(hint_descram) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	586	(forward) ? 
-2-:	586	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	590	(forward) ? 
-2-:	590	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	615	(forward) ? 
-2-:	615	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	642	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	676	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	655	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	354	if ((!rst_ni))
-2-:	358	if ((req_o && ack_i))
-3-:	365	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	562	if ((!rst_ni))
-2-:	564	if (((req_o && ack_i) && descramble_i))
-3-:	566	if ((calc_req_o && calc_ack_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	634	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	815039054	1265612	0	0
ExclusiveOps_A	815039054	813316946	0	0
ExclusiveProgHazard_A	815039054	813316946	0	0
ExclusiveState_A	815039054	813316946	0	0
ForwardCheck_A	815039054	4351755	0	0
IdleCheck_A	815039054	96010994	0	0
MaxBufs_A	1964	1964	0	0
OneHotAlloc_A	815039054	813316946	0	0
OneHotMatch_A	815039054	813316946	0	0
OneHotRspMatch_A	815039054	813316946	0	0
OneHotUpdate_A	815039054	813316946	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	1265612	0	0
T4	4628	29	0	0
T5	6934	33	0	0
T6	130964	256	0	0
T7	1180	13	0	0
T8	1136	0	0	0
T9	0	1456	0	0
T20	3388	6	0	0
T21	2678	0	0	0
T22	417208	1192	0	0
T23	0	632	0	0
T32	59036	687	0	0
T33	0	73	0	0
T34	0	117	0	0
T48	2316	0	0	0
T49	0	11	0	0
T57	0	156	0	0
T60	0	12	0	0
T69	0	28	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	813316946	0	0
T1	2142	1958	0	0
T2	2250	1740	0	0
T3	2538	2080	0	0
T4	4628	4492	0	0
T5	6934	6632	0	0
T6	130964	130852	0	0
T7	1180	1022	0	0
T8	1136	960	0	0
T20	3388	3068	0	0
T21	2678	2498	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	813316946	0	0
T1	2142	1958	0	0
T2	2250	1740	0	0
T3	2538	2080	0	0
T4	4628	4492	0	0
T5	6934	6632	0	0
T6	130964	130852	0	0
T7	1180	1022	0	0
T8	1136	960	0	0
T20	3388	3068	0	0
T21	2678	2498	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	813316946	0	0
T1	2142	1958	0	0
T2	2250	1740	0	0
T3	2538	2080	0	0
T4	4628	4492	0	0
T5	6934	6632	0	0
T6	130964	130852	0	0
T7	1180	1022	0	0
T8	1136	960	0	0
T20	3388	3068	0	0
T21	2678	2498	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	4351755	0	0
T4	4628	34	0	0
T5	6934	15	0	0
T6	130964	32	0	0
T7	1180	14	0	0
T8	1136	18	0	0
T9	0	22397	0	0
T20	3388	6	0	0
T21	2678	0	0	0
T22	417208	1192	0	0
T23	0	632	0	0
T32	59036	681	0	0
T48	2316	0	0	0
T49	0	16	0	0
T57	0	183	0	0
T60	0	11	0	0
T69	0	35	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	96010994	0	0
T1	1071	128	0	0
T2	1125	264	0	0
T3	1269	264	0	0
T4	4628	225	0	0
T5	6934	475	0	0
T6	130964	1344	0	0
T7	1180	169	0	0
T8	1136	216	0	0
T9	0	66514	0	0
T20	3388	334	0	0
T21	2678	128	0	0
T22	208604	1800	0	0
T23	0	486	0	0
T32	29518	489	0	0
T33	0	377	0	0
T48	1158	0	0	0
T49	0	23	0	0
T57	0	522	0	0
T60	0	94	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1964	1964	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	813316946	0	0
T1	2142	1958	0	0
T2	2250	1740	0	0
T3	2538	2080	0	0
T4	4628	4492	0	0
T5	6934	6632	0	0
T6	130964	130852	0	0
T7	1180	1022	0	0
T8	1136	960	0	0
T20	3388	3068	0	0
T21	2678	2498	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	813316946	0	0
T1	2142	1958	0	0
T2	2250	1740	0	0
T3	2538	2080	0	0
T4	4628	4492	0	0
T5	6934	6632	0	0
T6	130964	130852	0	0
T7	1180	1022	0	0
T8	1136	960	0	0
T20	3388	3068	0	0
T21	2678	2498	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	813316946	0	0
T1	2142	1958	0	0
T2	2250	1740	0	0
T3	2538	2080	0	0
T4	4628	4492	0	0
T5	6934	6632	0	0
T6	130964	130852	0	0
T7	1180	1022	0	0
T8	1136	960	0	0
T20	3388	3068	0	0
T21	2678	2498	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	815039054	813316946	0	0
T1	2142	1958	0	0
T2	2250	1740	0	0
T3	2538	2080	0	0
T4	4628	4492	0	0
T5	6934	6632	0	0
T6	130964	130852	0	0
T7	1180	1022	0	0
T8	1136	960	0	0
T20	3388	3068	0	0
T21	2678	2498	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		119	119	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
ALWAYS	354	12	12	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
ALWAYS	562	6	6	100.00
CONT_ASSIGN	572	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
CONT_ASSIGN	615	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
ALWAYS	631	6	6	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	655	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	695	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	701	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
289	1	1
296	1	1
299	1	1
302	1	1
320	1	1
325	1	1
354	1	1
355	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
365	1	1
366	1	1
			MISSING_ELSE
371	1	1
376	1	1
387	1	1
393	1	1
398	1	1
416	1	1
420	1	1
430	1	1
433	1	1
439	1	1
444	1	1
447	1	1
469	1	1
475	1	1
479	1	1
483	1	1
500	1	1
504	1	1
507	1	1
508	1	1
562	1	1
563	1	1
564	1	1
565	1	1
566	1	1
567	1	1
			MISSING_ELSE
572	1	1
576	1	1
579	1	1
586	1	1
590	1	1
598	1	1
615	1	1
620	1	1
625	4	4
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
636	1	1
			MISSING_ELSE
642	1	1
654	1	1
655	1	1
676	1	1
688	1	1
691	1	1
695	1	1
698	1	1
701	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	440	396	90.00
Logical	440	396	90.00
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T91,T61,T100
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T91,T61,T100

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T61,T100
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T5,T61,T100

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T61,T100,T213
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T61,T100,T213

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T61,T100,T187
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T61,T100,T187

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T6
1	0	1	1	1	1	1	Covered	T152
1	1	0	1	1	1	1	Covered	T20,T52,T118
1	1	1	0	1	1	1	Covered	T4,T5,T6
1	1	1	1	0	1	1	Covered	T61,T100,T187
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T9,T97,T94
1	1	1	1	1	1	1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T5,T22,T52
1	1	1	0	1	1	1	Covered	T4,T5,T6
1	1	1	1	0	1	1	Covered	T61,T188,T214
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T94,T203,T215
1	1	1	1	1	1	1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T22,T52,T78
1	1	1	0	1	1	1	Covered	T4,T5,T6
1	1	1	1	0	1	1	Covered	T61,T100,T187
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T9,T101,T203
1	1	1	1	1	1	1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T4,T5,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T22,T52,T78
1	1	1	0	1	1	1	Covered	T4,T5,T6
1	1	1	1	0	1	1	Covered	T61,T100,T188
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T75,T207,T216
1	1	1	1	1	1	1	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T97,T94
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T94,T217,T203
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T101,T217
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T75,T217,T218
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T97,T94
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T94,T44,T202
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T44,T202
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T97,T44,T202
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T22,T52
1	0	Covered	T4,T5,T6
1	1	Covered	T20,T22,T52

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T52,T78
0	1	0	Covered	T20,T52,T25
1	0	0	Covered	T25,T67,T68

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T20,T52,T25

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T33,T96
1	1	Covered	T22,T52,T78

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T22,T52
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T22,T52

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T52,T78
0	1	0	Covered	T5,T52,T25
1	0	0	Covered	T25,T67,T68

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T52,T25

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T33,T96
1	1	Covered	T22,T52,T78

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T52,T78
1	0	Covered	T4,T5,T6
1	1	Covered	T22,T52,T78

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T52,T78
0	1	0	Covered	T52,T25,T28
1	0	0	Covered	T25,T67,T68

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T52,T25,T28

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T33,T96
1	1	Covered	T22,T52,T78

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T52,T78
1	0	Covered	T4,T5,T6
1	1	Covered	T22,T52,T78

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T52,T78
0	1	0	Covered	T52,T25,T28
1	0	0	Covered	T25,T67,T68

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T52,T25,T28

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T33,T96
1	1	Covered	T22,T52,T78

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T69
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T69
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T69
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       289
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       296
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       299
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T9
1	1	Covered	T1,T2,T3

 LINE       302
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION (req_o && ack_i)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T69
1	1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       376
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T57,T69
1	0	Covered	T125,T126
1	1	Covered	T1,T2,T3

 LINE       387
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change)
             --------------------------------1-------------------------------   -----------2-----------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T57,T69
1	1	1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match)
             --1--   --------2-------   ----3----   ------4------   ----5---

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	Not Covered
1	1	0	1	1	Covered	T8,T9,T76
1	1	1	0	1	Covered	T125,T126
1	1	1	1	0	Covered	T4,T5,T6
1	1	1	1	1	Covered	T1,T2,T3

 LINE       416
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T20
1	1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T22

 LINE       420
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T8

 LINE       430
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       439
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       439
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T32,T23
1	0	Covered	T2,T3,T5

 LINE       444
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T32,T23

 LINE       469
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T125,T126
1	1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       475
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       479
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T24,T125,T11
1	1	1	Covered	T1,T2,T3

 LINE       483
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T188,T41
1	1	1	Covered	T4,T5,T6

 LINE       500
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       504
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       507
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       508
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       539
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       564
 EXPRESSION (req_o && ack_i && descramble_i)
             --1--    --2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T188
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       566
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       576
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T45,T100,T208
1	1	0	Covered	T24,T125,T11
1	1	1	Covered	T1,T2,T3

 LINE       586
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       586
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       590
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       590
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       598
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       598
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       615
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       615
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       615
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       620
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       620
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       620
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T6
1	1	1	0	Covered	T4,T5,T6
1	1	1	1	Covered	T4,T5,T6

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T6
1	1	1	0	Covered	T4,T5,T6
1	1	1	1	Covered	T4,T5,T6

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T6
1	1	1	0	Covered	T4,T5,T6
1	1	1	1	Covered	T4,T5,T6

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T5,T6
1	1	1	0	Covered	T4,T5,T6
1	1	1	1	Covered	T4,T5,T6

 LINE       636
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Not Covered

 LINE       642
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       655
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       676
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       676
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       688
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3

 LINE       691
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T5

 LINE       691
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       691
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T2,T3,T5

 LINE       691
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       695
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		40	40	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	296	2	2	100.00
TERNARY	439	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	586	3	3	100.00
TERNARY	590	3	3	100.00
TERNARY	615	3	3	100.00
TERNARY	642	2	2	100.00
TERNARY	676	2	2	100.00
TERNARY	655	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	354	4	4	100.00
IF	562	4	4	100.00
IF	634	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	296	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	439	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(hint_descram) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	586	(forward) ? 
-2-:	586	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	590	(forward) ? 
-2-:	590	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	615	(forward) ? 
-2-:	615	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	642	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	676	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	655	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	354	if ((!rst_ni))
-2-:	358	if ((req_o && ack_i))
-3-:	365	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	562	if ((!rst_ni))
-2-:	564	if (((req_o && ack_i) && descramble_i))
-3-:	566	if ((calc_req_o && calc_ack_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	634	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	407519527	894454	0	0
ExclusiveOps_A	407519527	406658473	0	0
ExclusiveProgHazard_A	407519527	406658473	0	0
ExclusiveState_A	407519527	406658473	0	0
ForwardCheck_A	407519527	2663130	0	0
IdleCheck_A	407519527	50329465	0	0
MaxBufs_A	982	982	0	0
OneHotAlloc_A	407519527	406658473	0	0
OneHotMatch_A	407519527	406658473	0	0
OneHotRspMatch_A	407519527	406658473	0	0
OneHotUpdate_A	407519527	406658473	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	894454	0	0
T4	2314	24	0	0
T5	3467	33	0	0
T6	65482	256	0	0
T7	590	13	0	0
T8	568	0	0	0
T20	1694	6	0	0
T21	1339	0	0	0
T22	208604	592	0	0
T23	0	470	0	0
T32	29518	520	0	0
T34	0	117	0	0
T48	1158	0	0	0
T49	0	6	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	2663130	0	0
T4	2314	27	0	0
T5	3467	15	0	0
T6	65482	32	0	0
T7	590	14	0	0
T8	568	9	0	0
T20	1694	6	0	0
T21	1339	0	0	0
T22	208604	592	0	0
T23	0	470	0	0
T32	29518	520	0	0
T48	1158	0	0	0
T49	0	7	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	50329465	0	0
T1	1071	128	0	0
T2	1125	264	0	0
T3	1269	264	0	0
T4	2314	206	0	0
T5	3467	475	0	0
T6	65482	1344	0	0
T7	590	169	0	0
T8	568	146	0	0
T20	1694	334	0	0
T21	1339	128	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		119	119	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
ALWAYS	354	12	12	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
ALWAYS	562	6	6	100.00
CONT_ASSIGN	572	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
CONT_ASSIGN	615	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
ALWAYS	631	6	6	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	655	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	695	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	701	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
289	1	1
296	1	1
299	1	1
302	1	1
320	1	1
325	1	1
354	1	1
355	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
365	1	1
366	1	1
			MISSING_ELSE
371	1	1
376	1	1
387	1	1
393	1	1
398	1	1
416	1	1
420	1	1
430	1	1
433	1	1
439	1	1
444	1	1
447	1	1
469	1	1
475	1	1
479	1	1
483	1	1
500	1	1
504	1	1
507	1	1
508	1	1
562	1	1
563	1	1
564	1	1
565	1	1
566	1	1
567	1	1
			MISSING_ELSE
572	1	1
576	1	1
579	1	1
586	1	1
590	1	1
598	1	1
615	1	1
620	1	1
625	4	4
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
636	1	1
			MISSING_ELSE
642	1	1
654	1	1
655	1	1
676	1	1
688	1	1
691	1	1
695	1	1
698	1	1
701	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	440	398	90.45
Logical	440	398	90.45
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T32
0	1	Covered	T61,T100,T187
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T8,T32
1	1	0	Covered	T100,T210
1	1	1	Covered	T61,T100,T187

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T32
0	1	Covered	T60,T61,T211
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T8,T32
1	1	0	Not Covered
1	1	1	Covered	T60,T61,T211

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T32
0	1	Covered	T130,T61,T211
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T8,T32
1	1	0	Not Covered
1	1	1	Covered	T130,T61,T211

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T32
0	1	Covered	T61,T100,T187
1	0	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T8,T32
1	1	0	Not Covered
1	1	1	Covered	T61,T100,T187

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T32

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T32

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T32

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T8,T32
1	Covered	T1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T32
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T32

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T4,T8,T32
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T32,T22,T23
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T46,T219,T220
1	1	1	0	1	1	1	Covered	T4,T8,T32
1	1	1	1	0	1	1	Covered	T61,T100,T214
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T9,T188,T175
1	1	1	1	1	1	1	Covered	T4,T8,T32

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T32
1	0	Covered	T4,T8,T32

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T32,T22,T23
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T22,T60,T47
1	1	1	0	1	1	1	Covered	T4,T8,T32
1	1	1	1	0	1	1	Covered	T61,T100,T187
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T9,T76,T97
1	1	1	1	1	1	1	Covered	T4,T8,T32

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T32
1	0	Covered	T4,T8,T32

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T32,T22,T23
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T22,T78,T221
1	1	1	0	1	1	1	Covered	T4,T8,T32
1	1	1	1	0	1	1	Covered	T61,T211,T100
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T75,T212,T187
1	1	1	1	1	1	1	Covered	T4,T8,T32

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T32
1	0	Covered	T4,T8,T32

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T32,T22,T23
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T22,T78,T221
1	1	1	0	1	1	1	Covered	T4,T8,T32
1	1	1	1	0	1	1	Covered	T61,T100,T187
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T75,T100,T101
1	1	1	1	1	1	1	Covered	T4,T8,T32

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T32
1	0	Covered	T4,T8,T32

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T217,T188
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T9,T76,T97
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T75,T212,T217
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T75,T100,T101
1	1	1	Covered	T1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T49,T9,T106
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T49,T9,T76
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T33,T49,T9
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T49,T9,T44
1	1	1	Covered	T1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T46,T78
1	0	Covered	T4,T8,T32
1	1	Covered	T22,T46,T78

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T78,T25
0	1	0	Covered	T46,T25,T26
1	0	0	Covered	T25,T26,T68

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T32,T22
1	1	Covered	T46,T25,T26

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T49,T69,T25
1	1	Covered	T22,T78,T25

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T60,T46
1	0	Covered	T4,T8,T32
1	1	Covered	T22,T60,T46

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T78,T25
0	1	0	Covered	T60,T46,T47
1	0	0	Covered	T25,T26,T68

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T32,T22
1	1	Covered	T60,T46,T47

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T49,T69,T25
1	1	Covered	T22,T78,T25

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T47,T78
1	0	Covered	T4,T8,T32
1	1	Covered	T22,T47,T78

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T78,T25
0	1	0	Covered	T47,T25,T26
1	0	0	Covered	T25,T26,T68

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T32,T22
1	1	Covered	T47,T25,T26

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T49,T69,T25
1	1	Covered	T22,T78,T25

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T78,T25
1	0	Covered	T4,T8,T32
1	1	Covered	T22,T78,T25

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T78,T25
0	1	0	Covered	T25,T26,T27
1	0	0	Covered	T25,T26,T68

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T32,T22
1	1	Covered	T25,T26,T27

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T49,T69,T25
1	1	Covered	T22,T78,T25

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T4,T8,T32
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T69,T75
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T32

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T69,T202
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T32

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T69
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T32

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T69,T97
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T8,T32

 LINE       289
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T32,T22,T23
1	0	Covered	T4,T8,T32
1	1	Covered	T4,T8,T32

 LINE       296
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       299
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T57
1	1	Covered	T4,T8,T32

 LINE       302
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T32
1	1	Covered	T4,T8,T32

 LINE       358
 EXPRESSION (req_o && ack_i)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T69,T75
1	1	Covered	T4,T8,T32

 LINE       371
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T32
0	1	Covered	T4,T8,T32
1	0	Covered	T1,T2,T3

 LINE       376
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T57,T24,T43
1	0	Covered	T125,T80,T126
1	1	Covered	T1,T2,T3

 LINE       387
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change)
             --------------------------------1-------------------------------   -----------2-----------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T4,T8,T32
1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T8,T32
1	1	0	Covered	T57,T24,T43
1	1	1	Covered	T1,T2,T3

 LINE       398
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match)
             --1--   --------2-------   ----3----   ------4------   ----5---

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	Not Covered
1	1	0	1	1	Covered	T8,T9,T57
1	1	1	0	1	Covered	T125
1	1	1	1	0	Covered	T4,T32,T22
1	1	1	1	1	Covered	T4,T8,T32

 LINE       416
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T32,T23
1	0	Covered	T4,T22,T49
1	1	Covered	T8,T32,T23

 LINE       420
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T32,T22
1	0	Covered	T4,T32,T22
1	1	Covered	T8,T22,T9

 LINE       420
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T32,T22

 LINE       430
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T22,T9,T60
1	0	Covered	T8,T32,T23
1	1	Covered	T60,T130,T61

 LINE       439
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T23,T60

 LINE       439
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T32,T23,T46
1	0	Covered	T60,T130,T61

 LINE       444
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T32,T22,T23
1	0	Covered	T8,T32,T23
1	1	Covered	T32,T23,T46

 LINE       469
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T39,T124
1	0	Covered	T125,T80,T126
1	1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T60,T46

 LINE       475
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T60,T46
1	1	Covered	T33,T60,T46

 LINE       479
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T33,T60
1	0	1	Covered	T4,T32,T22
1	1	0	Covered	T8,T24,T125
1	1	1	Covered	T33,T60,T46

 LINE       483
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T60,T46
1	1	0	Covered	T100,T39,T124
1	1	1	Covered	T4,T8,T32

 LINE       500
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T33,T60,T46
1	0	Not Covered
1	1	Covered	T4,T8,T32

 LINE       504
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T33,T60,T46

 LINE       507
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T8,T32
1	1	Covered	T33,T60,T46

 LINE       508
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T60,T46
1	1	Covered	T4,T8,T32

 LINE       539
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T81,T46,T82
1	0	Covered	T8,T33,T60
1	1	Covered	T8,T33,T60

 LINE       564
 EXPRESSION (req_o && ack_i && descramble_i)
             --1--    --2--    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T4,T8,T32
1	1	1	Covered	T8,T33,T60

 LINE       566
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T81,T46,T82
1	0	Covered	T8,T33,T60
1	1	Covered	T8,T33,T60

 LINE       576
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T45,T100,T208
1	1	0	Covered	T8,T24,T125
1	1	1	Covered	T33,T60,T46

 LINE       586
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       586
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T60,T46

 LINE       590
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       590
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T4,T8,T32
1	Covered	T1,T2,T3

 LINE       598
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T60,T46
1	0	Covered	T4,T8,T32

 LINE       598
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T60,T46

 LINE       615
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T8,T32

 LINE       615
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T60,T46

 LINE       615
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T60,T46

 LINE       620
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T25,T26,T27
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T32

 LINE       620
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T32
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       620
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T8,T32
1	1	1	0	Covered	T4,T8,T32
1	1	1	1	Covered	T4,T32,T22

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T8,T32
1	1	1	0	Covered	T4,T8,T32
1	1	1	1	Covered	T4,T32,T22

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T8,T32
1	1	1	0	Covered	T4,T8,T32
1	1	1	1	Covered	T4,T32,T22

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T4,T8,T32
1	1	1	0	Covered	T4,T8,T32
1	1	1	1	Covered	T4,T32,T22

 LINE       636
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T32,T22
0	1	Covered	T100,T210
1	0	Not Covered

 LINE       642
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T32,T22

 LINE       655
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T60,T46,T47

 LINE       676
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T32,T23

 LINE       676
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T8,T32,T23
1	Covered	T33,T60,T46

 LINE       688
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T32,T22
1	0	Covered	T4,T8,T32

 LINE       691
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T60,T46,T47

 LINE       691
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T60,T46
1	0	Covered	T4,T8,T32
1	1	Covered	T60,T46,T47

 LINE       691
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T33,T60,T46
1	0	0	Covered	T61,T100,T187

 LINE       691
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T32,T22
1	1	Covered	T100,T210

 LINE       695
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T33,T60,T46
1	0	Covered	T4,T8,T32
1	1	Covered	T60,T46,T47

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		40	40	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	296	2	2	100.00
TERNARY	439	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	586	3	3	100.00
TERNARY	590	3	3	100.00
TERNARY	615	3	3	100.00
TERNARY	642	2	2	100.00
TERNARY	676	2	2	100.00
TERNARY	655	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	354	4	4	100.00
IF	562	4	4	100.00
IF	634	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T32

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T32

	LineNo.	Expression
-1-:	296	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	439	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T32,T23,T60
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(hint_descram) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T60,T46
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	586	(forward) ? 
-2-:	586	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T32
0	1	Covered	T33,T60,T46
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	590	(forward) ? 
-2-:	590	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T8,T32

	LineNo.	Expression
-1-:	615	(forward) ? 
-2-:	615	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T8,T32
0	1	Covered	T33,T60,T46
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	642	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	676	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T32,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	655	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T60,T46,T47
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T32

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T8,T32

	LineNo.	Expression
-1-:	354	if ((!rst_ni))
-2-:	358	if ((req_o && ack_i))
-3-:	365	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T8,T32
0	0	1	Covered	T4,T8,T32
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	562	if ((!rst_ni))
-2-:	564	if (((req_o && ack_i) && descramble_i))
-3-:	566	if ((calc_req_o && calc_ack_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T33,T60
0	0	1	Covered	T8,T33,T60
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	634	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T22
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	407519527	371158	0	0
ExclusiveOps_A	407519527	406658473	0	0
ExclusiveProgHazard_A	407519527	406658473	0	0
ExclusiveState_A	407519527	406658473	0	0
ForwardCheck_A	407519527	1688625	0	0
IdleCheck_A	407519527	45681529	0	0
MaxBufs_A	982	982	0	0
OneHotAlloc_A	407519527	406658473	0	0
OneHotMatch_A	407519527	406658473	0	0
OneHotRspMatch_A	407519527	406658473	0	0
OneHotUpdate_A	407519527	406658473	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	371158	0	0
T4	2314	5	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	0	0	0
T9	0	1456	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	600	0	0
T23	0	162	0	0
T32	29518	167	0	0
T33	0	73	0	0
T48	1158	0	0	0
T49	0	5	0	0
T57	0	156	0	0
T60	0	12	0	0
T69	0	28	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	1688625	0	0
T4	2314	7	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	9	0	0
T9	0	22397	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	600	0	0
T23	0	162	0	0
T32	29518	161	0	0
T48	1158	0	0	0
T49	0	9	0	0
T57	0	183	0	0
T60	0	11	0	0
T69	0	35	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	45681529	0	0
T4	2314	19	0	0
T5	3467	0	0	0
T6	65482	0	0	0
T7	590	0	0	0
T8	568	70	0	0
T9	0	66514	0	0
T20	1694	0	0	0
T21	1339	0	0	0
T22	208604	1800	0	0
T23	0	486	0	0
T32	29518	489	0	0
T33	0	377	0	0
T48	1158	0	0	0
T49	0	23	0	0
T57	0	522	0	0
T60	0	94	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	982	982	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407519527	406658473	0	0
T1	1071	979	0	0
T2	1125	870	0	0
T3	1269	1040	0	0
T4	2314	2246	0	0
T5	3467	3316	0	0
T6	65482	65426	0	0
T7	590	511	0	0
T8	568	480	0	0
T20	1694	1534	0	0
T21	1339	1249	0	0