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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull	0	0	412887629	2647043	0	0
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A	0	0	981	981	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A	0	0	412887629	29455342	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	412887629	29455342	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A	0	0	981	981	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck	0	0	981	981	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A	0	0	412887629	3603423	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	412887629	3603423	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A	0	0	412887629	28493761	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	412887629	28493761	0	0
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	981	981	0	0
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	407247520	406401400	0	0
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	407247520	406401400	0	0
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A	0	0	981	981	0	0
tb.dut.u_tl_gate.u_state_regs_A	0	0	412887629	412041509	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	981	981	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	981	981	0	0
tb.dut.u_to_prog_fifo.AddrOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.DataIntgOptions_A	0	0	981	981	0	0
tb.dut.u_to_prog_fifo.ReqOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A	0	0	981	981	0	0
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	981	981	0	0
tb.dut.u_to_prog_fifo.TlOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_A	0	0	412887629	3864891	0	0
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_AKnownEnable	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.WdataOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.WeOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.WmaskOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite	0	0	981	981	0	0
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A	0	0	981	981	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A	0	0	412887629	3864891	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	412887629	3864891	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A	0	0	981	981	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	981	981	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.AddrOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.DataIntgOptions_A	0	0	981	981	0	0
tb.dut.u_to_rd_fifo.ReqOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A	0	0	981	981	0	0
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	981	981	0	0
tb.dut.u_to_rd_fifo.TlOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_A	0	0	412887629	4540983	0	0
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_AKnownEnable	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	981	981	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	412887629	2369875	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	412294773	2363401	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	981	981	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	412887629	4540983	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	412887629	4540983	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	981	981	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	981	981	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	412712982	4532763	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	412887629	4542387	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	412887629	2369875	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	412887629	412041509	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	412887629	2369875	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	412887629	18446	0	975
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	412887629	12718	0	975
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	407247520	406368253	0	2535
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	412887629	0	0	975
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	412887629	0	0	975
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	412887629	0	0	975
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	412887629	0	0	975
tb.dut.u_flash_hw_if.DisableChk_A	0	0	400940883	4996681	0	43
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	407247645	406368363	0	2535
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	407225275	406346143	0	2385
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	407247645	406368363	0	2535
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	407247645	406368363	0	2535
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	407247645	406368363	0	2535
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	407247645	406368363	0	2535
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	407247645	406368363	0	2535

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	415605260	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	415605260	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	415605260	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	415605260	46024	46024	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	415605260	15	15	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	415605260	8	8	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	415605260	3	3	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	415605260	13991	13991	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	415605260	38273	38273	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	415605260	15828154	15828154	1170

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	415605260	46024	46024	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	415605260	15	15	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	415605260	8	8	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	415605260	3	3	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	415605260	13991	13991	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	415605260	38273	38273	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	415605260	15828154	15828154	1170