Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24446467	1		T1	96035		T2	3779		T3	503
full_word	7759849	1		T1	20331		T2	665		T3	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32206016	1		T1	116366		T2	4444		T3	505
auto[TlIntgErrCmd]	88	1		T62	3		T198	3		T199	5
auto[TlIntgErrData]	95	1		T62	3		T198	4		T199	4
auto[TlIntgErrBoth]	117	1		T62	4		T198	3		T199	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27717948	1		T1	102471		T2	3967		T3	497
auto[1]	4488368	1		T1	13895		T2	477		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23783159	1		T1	94983		T2	3714		T3	497
auto[TlIntgErrNone]	partial	auto[1]	663037	1		T1	1052		T2	65		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	3934634	1		T1	7488		T2	253		T4	1079
auto[TlIntgErrNone]	full_word	auto[1]	3825186	1		T1	12843		T2	412		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T62	3		T198	3		T217	1
auto[TlIntgErrCmd]	partial	auto[1]	40	1		T199	5		T217	2		T219	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T245	1		T374	1		T380	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T219	1		T249	1		T285	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T62	1		T198	2		T217	1
auto[TlIntgErrData]	partial	auto[1]	44	1		T62	2		T198	2		T199	4
auto[TlIntgErrData]	full_word	auto[0]	3	1		T374	1		T285	1		T379	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T219	1		T283	1		T377	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1		T62	3		T198	1		T199	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T62	1		T198	2		T217	1
auto[TlIntgErrBoth]	full_word	auto[0]	10	1		T282	1		T381	3		T375	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T245	1		T249	1		T381	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24088	1		T62	8		T198	7		T199	10
full_word	4471868	1		T2	19		T6	16156		T17	14

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4495671	1		T2	19		T6	16156		T17	14
auto[TlIntgErrCmd]	95	1		T62	4		T198	4		T199	3
auto[TlIntgErrData]	98	1		T62	4		T198	3		T199	2
auto[TlIntgErrBoth]	92	1		T62	1		T198	2		T199	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4466210	1		T2	19		T6	16156		T17	14
auto[1]	29746	1		T62	3		T198	7		T199	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1480	1		T214	8		T215	22		T216	128
auto[TlIntgErrNone]	partial	auto[1]	22344	1		T214	123		T215	492		T216	1398
auto[TlIntgErrNone]	full_word	auto[0]	4464624	1		T2	19		T6	16156		T17	14
auto[TlIntgErrNone]	full_word	auto[1]	7223	1		T214	58		T215	168		T216	342
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T62	2		T199	1		T217	3
auto[TlIntgErrCmd]	partial	auto[1]	59	1		T62	2		T198	3		T199	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T249	1		T381	1		T375	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T198	1		T335	1		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1		T62	3		T198	2		T199	1
auto[TlIntgErrData]	partial	auto[1]	51	1		T199	1		T219	3		T245	5
auto[TlIntgErrData]	full_word	auto[0]	3	1		T62	1		T381	1		T375	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T198	1		T219	1		T381	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1		T199	1		T217	1		T219	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T62	1		T198	2		T199	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T376	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T245	1		T249	1		T381	1