Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	98.41	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

315 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.num	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.op	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.start	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_0.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_0.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_1.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_1.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_2.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_2.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_3.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_3.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_4.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_4.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_5.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_5.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_6.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_6.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_7.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_7.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr1.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr1.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr10.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr11.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr12.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr13.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr13.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr14.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr14.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr15.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr15.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr16.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr16.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr17.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr17.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr18.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr19.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field4	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field5	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field6	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field7	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field8	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field9	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field4	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field4	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field5	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field6	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field7	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field8	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr8.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr9.field0	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.num

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.num

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.num

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.op

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.op

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.start

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.start

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1041	1		T61	1		T62	10		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1008	1		T267	7		T268	7		T269	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1148	1		T267	6		T268	6		T269	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1183	1		T267	8		T268	8		T269	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	796	1		T267	8		T268	8		T269	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	992	1		T267	6		T268	5		T269	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	736	1		T267	6		T268	8		T269	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	35	1		T267	7		T268	7		T269	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	715	1		T184	3		T190	4		T191	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	753	1		T184	7		T190	9		T191	3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	469	1		T62	2		T63	1		T198	4
auto[1]	514	1		T61	1		T62	6		T198	5

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	550	1		T62	2		T63	1		T198	4
auto[1]	647	1		T61	1		T62	8		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	498	1		T62	1		T63	1		T198	4
auto[1]	568	1		T61	1		T62	7		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	394	1		T63	1		T198	4		T199	3
auto[1]	497	1		T61	1		T62	7		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	518	1		T62	2		T63	1		T198	4
auto[1]	595	1		T61	1		T62	7		T198	5

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	535	1		T62	1		T63	1		T198	3
auto[1]	618	1		T61	1		T62	7		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	484	1		T62	2		T63	1		T198	4
auto[1]	546	1		T61	1		T62	8		T198	5

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	289	1		T61	1		T62	4		T198	4
auto[1]	423	1		T62	6		T63	1		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	413	1		T61	1		T62	4		T198	3
auto[1]	506	1		T62	6		T63	1		T198	5

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	340	1		T61	1		T62	4		T198	3
auto[1]	454	1		T62	6		T63	1		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	249	1		T61	1		T62	4		T198	4
auto[1]	411	1		T62	5		T63	1		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	319	1		T61	1		T62	4		T198	4
auto[1]	474	1		T62	6		T63	1		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	390	1		T61	1		T62	4		T198	4
auto[1]	485	1		T62	6		T63	1		T198	4

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	314	1		T61	1		T62	3		T198	3
auto[1]	438	1		T62	5		T63	1		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	367	1		T61	1		T62	3		T198	4
auto[1]	519	1		T62	7		T63	1		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	529	1		T61	1		T62	3		T198	3
auto[1]	556	1		T62	7		T198	6		T199	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	430	1		T61	1		T62	3		T198	4
auto[1]	524	1		T62	7		T63	1		T198	5

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	336	1		T61	1		T62	2		T198	4
auto[1]	419	1		T62	5		T63	1		T198	5

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	464	1		T61	1		T62	3		T198	4
auto[1]	538	1		T62	6		T63	1		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	482	1		T61	1		T62	3		T198	4
auto[1]	553	1		T62	7		T63	1		T198	5

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	344	1		T61	1		T62	3		T198	3
auto[1]	520	1		T62	7		T63	1		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	234	1		T62	2		T198	3		T199	1
auto[1]	736	1		T61	1		T62	7		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	348	1		T62	1		T198	3		T199	1
auto[1]	824	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	276	1		T62	2		T198	3		T199	1
auto[1]	768	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	208	1		T62	2		T198	3		T199	1
auto[1]	722	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	300	1		T62	1		T198	3		T199	1
auto[1]	790	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	324	1		T62	2		T198	3		T199	1
auto[1]	805	1		T62	8		T63	1		T198	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	252	1		T62	2		T198	3		T199	1
auto[1]	760	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	194	1		T61	1		T62	1		T198	3
auto[1]	531	1		T62	7		T63	1		T198	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	320	1		T61	1		T62	1		T198	3
auto[1]	653	1		T62	8		T63	1		T198	5

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	270	1		T61	1		T62	1		T198	3
auto[1]	588	1		T62	9		T63	1		T198	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	225	1		T61	1		T62	1		T198	3
auto[1]	515	1		T62	7		T63	1		T198	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	285	1		T61	1		T62	1		T198	2
auto[1]	613	1		T62	9		T63	1		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	303	1		T61	1		T62	1		T198	3
auto[1]	647	1		T62	9		T63	1		T198	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	260	1		T61	1		T62	1		T198	3
auto[1]	564	1		T62	9		T63	1		T198	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	363	1		T62	1		T198	2		T199	4
auto[1]	598	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	442	1		T62	1		T198	2		T199	3
auto[1]	720	1		T61	1		T62	9		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	395	1		T62	1		T198	2		T199	4
auto[1]	647	1		T61	1		T62	9		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	348	1		T62	1		T198	2		T199	4
auto[1]	578	1		T61	1		T62	9		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	412	1		T62	1		T198	2		T199	4
auto[1]	671	1		T61	1		T62	9		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	422	1		T62	1		T198	1		T199	4
auto[1]	698	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	377	1		T62	1		T198	2		T199	4
auto[1]	630	1		T61	1		T62	9		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	188	1		T62	2		T198	2		T199	4
auto[1]	720	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	290	1		T62	2		T198	2		T199	3
auto[1]	815	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	218	1		T62	2		T198	2		T199	4
auto[1]	765	1		T61	1		T62	7		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	196	1		T62	1		T198	2		T199	3
auto[1]	670	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	263	1		T62	1		T198	2		T199	4
auto[1]	766	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	280	1		T62	2		T198	1		T199	4
auto[1]	782	1		T62	8		T63	1		T198	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	232	1		T62	2		T198	2		T199	4
auto[1]	716	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	220	1		T62	1		T198	5		T199	2
auto[1]	632	1		T61	1		T62	9		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	378	1		T62	1		T198	5		T199	1
auto[1]	669	1		T61	1		T62	6		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	285	1		T62	1		T198	4		T199	2
auto[1]	641	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	186	1		T62	1		T198	4		T199	2
auto[1]	535	1		T61	1		T62	8		T63	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	313	1		T62	1		T198	4		T199	2
auto[1]	651	1		T61	1		T62	9		T63	1