Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T17
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T17,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T17

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1653154464	1649737488	0	0
CheckNGreaterZero_A	4240	4240	0	0
GntImpliesReady_A	1653154464	450826299	0	0
GntImpliesValid_A	1653154464	450826299	0	0
GrantKnown_A	1653154464	1649737488	0	0
IdxKnown_A	1653154464	1649737488	0	0
IndexIsCorrect_A	1653154464	450826299	0	0
NoReadyValidNoGrant_A	1653154464	180820392	0	0
Priority_A	1653154464	475374227	0	0
ReadyAndValidImplyGrant_A	1653154464	450826299	0	0
ReqAndReadyImplyGrant_A	1653154464	450826299	0	0
ReqImpliesValid_A	1653154464	475374227	0	0
ValidKnown_A	1653154464	1649737488	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	1649737488	0	0
T1	3268404	3268044	0	0
T2	38172	37444	0	0
T3	14548	12000	0	0
T4	2077028	2076696	0	0
T5	2516	2272	0	0
T6	3170268	3169704	0	0
T12	4968	4152	0	0
T13	4616	3688	0	0
T17	50272	49696	0	0
T18	16452	13964	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4240	4240	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T12	4	4	0	0
T13	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	450826299	0	0
T1	3268404	1164830	0	0
T2	38172	13786	0	0
T3	14548	358	0	0
T4	2077028	970794	0	0
T5	2516	70	0	0
T6	3170268	55772	0	0
T7	0	30014	0	0
T8	0	177792	0	0
T12	4968	134	0	0
T13	4616	134	0	0
T17	50272	18848	0	0
T18	16452	472	0	0
T25	0	330552	0	0
T26	0	498	0	0
T55	0	26	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	450826299	0	0
T1	3268404	1164830	0	0
T2	38172	13786	0	0
T3	14548	358	0	0
T4	2077028	970794	0	0
T5	2516	70	0	0
T6	3170268	55772	0	0
T7	0	30014	0	0
T8	0	177792	0	0
T12	4968	134	0	0
T13	4616	134	0	0
T17	50272	18848	0	0
T18	16452	472	0	0
T25	0	330552	0	0
T26	0	498	0	0
T55	0	26	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	1649737488	0	0
T1	3268404	3268044	0	0
T2	38172	37444	0	0
T3	14548	12000	0	0
T4	2077028	2076696	0	0
T5	2516	2272	0	0
T6	3170268	3169704	0	0
T12	4968	4152	0	0
T13	4616	3688	0	0
T17	50272	49696	0	0
T18	16452	13964	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	1649737488	0	0
T1	3268404	3268044	0	0
T2	38172	37444	0	0
T3	14548	12000	0	0
T4	2077028	2076696	0	0
T5	2516	2272	0	0
T6	3170268	3169704	0	0
T12	4968	4152	0	0
T13	4616	3688	0	0
T17	50272	49696	0	0
T18	16452	13964	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	450826299	0	0
T1	3268404	1164830	0	0
T2	38172	13786	0	0
T3	14548	358	0	0
T4	2077028	970794	0	0
T5	2516	70	0	0
T6	3170268	55772	0	0
T7	0	30014	0	0
T8	0	177792	0	0
T12	4968	134	0	0
T13	4616	134	0	0
T17	50272	18848	0	0
T18	16452	472	0	0
T25	0	330552	0	0
T26	0	498	0	0
T55	0	26	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	180820392	0	0
T1	3268404	6956	0	0
T2	38172	1304	0	0
T3	14548	1282	0	0
T4	2077028	3040	0	0
T5	2516	274	0	0
T6	3170268	1844572	0	0
T7	0	44490	0	0
T8	0	173776	0	0
T12	4968	536	0	0
T13	4616	536	0	0
T17	50272	1872	0	0
T18	16452	1792	0	0
T26	0	1320	0	0
T44	0	34	0	0
T55	0	68	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	475374227	0	0
T1	3268404	1164830	0	0
T2	38172	13786	0	0
T3	14548	358	0	0
T4	2077028	970794	0	0
T5	2516	70	0	0
T6	3170268	532176	0	0
T7	0	35432	0	0
T8	0	218934	0	0
T12	4968	134	0	0
T13	4616	134	0	0
T17	50272	18848	0	0
T18	16452	472	0	0
T25	0	330552	0	0
T26	0	498	0	0
T55	0	26	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	450826299	0	0
T1	3268404	1164830	0	0
T2	38172	13786	0	0
T3	14548	358	0	0
T4	2077028	970794	0	0
T5	2516	70	0	0
T6	3170268	55772	0	0
T7	0	30014	0	0
T8	0	177792	0	0
T12	4968	134	0	0
T13	4616	134	0	0
T17	50272	18848	0	0
T18	16452	472	0	0
T25	0	330552	0	0
T26	0	498	0	0
T55	0	26	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	450826299	0	0
T1	3268404	1164830	0	0
T2	38172	13786	0	0
T3	14548	358	0	0
T4	2077028	970794	0	0
T5	2516	70	0	0
T6	3170268	55772	0	0
T7	0	30014	0	0
T8	0	177792	0	0
T12	4968	134	0	0
T13	4616	134	0	0
T17	50272	18848	0	0
T18	16452	472	0	0
T25	0	330552	0	0
T26	0	498	0	0
T55	0	26	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	475374227	0	0
T1	3268404	1164830	0	0
T2	38172	13786	0	0
T3	14548	358	0	0
T4	2077028	970794	0	0
T5	2516	70	0	0
T6	3170268	532176	0	0
T7	0	35432	0	0
T8	0	218934	0	0
T12	4968	134	0	0
T13	4616	134	0	0
T17	50272	18848	0	0
T18	16452	472	0	0
T25	0	330552	0	0
T26	0	498	0	0
T55	0	26	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1653154464	1649737488	0	0
T1	3268404	3268044	0	0
T2	38172	37444	0	0
T3	14548	12000	0	0
T4	2077028	2076696	0	0
T5	2516	2272	0	0
T6	3170268	3169704	0	0
T12	4968	4152	0	0
T13	4616	3688	0	0
T17	50272	49696	0	0
T18	16452	13964	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413288616	412434372	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	413288616	123194413	0	0
GntImpliesValid_A	413288616	123194413	0	0
GrantKnown_A	413288616	412434372	0	0
IdxKnown_A	413288616	412434372	0	0
IndexIsCorrect_A	413288616	123194413	0	0
NoReadyValidNoGrant_A	413288616	47239611	0	0
Priority_A	413288616	129614826	0	0
ReadyAndValidImplyGrant_A	413288616	123194413	0	0
ReqAndReadyImplyGrant_A	413288616	123194413	0	0
ReqImpliesValid_A	413288616	129614826	0	0
ValidKnown_A	413288616	412434372	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	123194413	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	14613	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	123194413	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	14613	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	123194413	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	14613	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	47239611	0	0
T1	817101	1019	0	0
T2	9543	256	0	0
T3	3637	641	0	0
T4	519257	951	0	0
T5	629	137	0	0
T6	792567	476457	0	0
T12	1242	268	0	0
T13	1154	268	0	0
T17	12568	256	0	0
T18	4113	896	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	129614826	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	158192	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	123194413	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	14613	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	123194413	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	14613	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	129614826	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	158192	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413288616	412434372	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	413288616	122985232	0	0
GntImpliesValid_A	413288616	122985232	0	0
GrantKnown_A	413288616	412434372	0	0
IdxKnown_A	413288616	412434372	0	0
IndexIsCorrect_A	413288616	122985232	0	0
NoReadyValidNoGrant_A	413288616	47239611	0	0
Priority_A	413288616	129405645	0	0
ReadyAndValidImplyGrant_A	413288616	122985232	0	0
ReqAndReadyImplyGrant_A	413288616	122985232	0	0
ReqImpliesValid_A	413288616	129405645	0	0
ValidKnown_A	413288616	412434372	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	122985232	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	14613	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	122985232	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	14613	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	122985232	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	14613	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	47239611	0	0
T1	817101	1019	0	0
T2	9543	256	0	0
T3	3637	641	0	0
T4	519257	951	0	0
T5	629	137	0	0
T6	792567	476457	0	0
T12	1242	268	0	0
T13	1154	268	0	0
T17	12568	256	0	0
T18	4113	896	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	129405645	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	158192	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	122985232	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	14613	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	122985232	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	14613	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	129405645	0	0
T1	817101	528991	0	0
T2	9543	64	0	0
T3	3637	179	0	0
T4	519257	147955	0	0
T5	629	35	0	0
T6	792567	158192	0	0
T12	1242	67	0	0
T13	1154	67	0	0
T17	12568	9164	0	0
T18	4113	236	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T6,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T6,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T17
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T17,T7
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413288616	412434372	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	413288616	102323327	0	0
GntImpliesValid_A	413288616	102323327	0	0
GrantKnown_A	413288616	412434372	0	0
IdxKnown_A	413288616	412434372	0	0
IndexIsCorrect_A	413288616	102323327	0	0
NoReadyValidNoGrant_A	413288616	43170585	0	0
Priority_A	413288616	108176878	0	0
ReadyAndValidImplyGrant_A	413288616	102323327	0	0
ReqAndReadyImplyGrant_A	413288616	102323327	0	0
ReqImpliesValid_A	413288616	108176878	0	0
ValidKnown_A	413288616	412434372	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	102323327	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	13273	0	0
T7	0	15007	0	0
T8	0	88896	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	102323327	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	13273	0	0
T7	0	15007	0	0
T8	0	88896	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	102323327	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	13273	0	0
T7	0	15007	0	0
T8	0	88896	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	43170585	0	0
T1	817101	2459	0	0
T2	9543	396	0	0
T3	3637	0	0	0
T4	519257	569	0	0
T5	629	0	0	0
T6	792567	445829	0	0
T7	0	22245	0	0
T8	0	86888	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	680	0	0
T18	4113	0	0	0
T26	0	660	0	0
T44	0	17	0	0
T55	0	34	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	108176878	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	107896	0	0
T7	0	17716	0	0
T8	0	109467	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	102323327	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	13273	0	0
T7	0	15007	0	0
T8	0	88896	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	102323327	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	13273	0	0
T7	0	15007	0	0
T8	0	88896	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	108176878	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	107896	0	0
T7	0	17716	0	0
T8	0	109467	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T6,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T6,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T17
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T17,T7
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	413288616	412434372	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	413288616	102323327	0	0
GntImpliesValid_A	413288616	102323327	0	0
GrantKnown_A	413288616	412434372	0	0
IdxKnown_A	413288616	412434372	0	0
IndexIsCorrect_A	413288616	102323327	0	0
NoReadyValidNoGrant_A	413288616	43170585	0	0
Priority_A	413288616	108176878	0	0
ReadyAndValidImplyGrant_A	413288616	102323327	0	0
ReqAndReadyImplyGrant_A	413288616	102323327	0	0
ReqImpliesValid_A	413288616	108176878	0	0
ValidKnown_A	413288616	412434372	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	102323327	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	13273	0	0
T7	0	15007	0	0
T8	0	88896	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	102323327	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	13273	0	0
T7	0	15007	0	0
T8	0	88896	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	102323327	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	13273	0	0
T7	0	15007	0	0
T8	0	88896	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	43170585	0	0
T1	817101	2459	0	0
T2	9543	396	0	0
T3	3637	0	0	0
T4	519257	569	0	0
T5	629	0	0	0
T6	792567	445829	0	0
T7	0	22245	0	0
T8	0	86888	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	680	0	0
T18	4113	0	0	0
T26	0	660	0	0
T44	0	17	0	0
T55	0	34	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	108176878	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	107896	0	0
T7	0	17716	0	0
T8	0	109467	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	102323327	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	13273	0	0
T7	0	15007	0	0
T8	0	88896	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	102323327	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	13273	0	0
T7	0	15007	0	0
T8	0	88896	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	108176878	0	0
T1	817101	53424	0	0
T2	9543	6829	0	0
T3	3637	0	0	0
T4	519257	337442	0	0
T5	629	0	0	0
T6	792567	107896	0	0
T7	0	17716	0	0
T8	0	109467	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	260	0	0
T18	4113	0	0	0
T25	0	165276	0	0
T26	0	249	0	0
T55	0	13	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0