Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_to_prog_fifo.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.54	93.44	65.77			69.23	85.71	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415471434	33691906	0	0
DepthKnown_A	415471434	414531742	0	0
RvalidKnown_A	415471434	414531742	0	0
WreadyKnown_A	415471434	414531742	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	33691906	0	0
T1	817101	116366	0	0
T2	9543	4444	0	0
T3	3637	505	0	0
T4	519257	73942	0	0
T5	629	123	0	0
T6	792567	32675	0	0
T12	1242	106	0	0
T13	1154	106	0	0
T17	12568	5707	0	0
T18	4113	505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415471434	42293173	0	0
DepthKnown_A	415471434	414531742	0	0
RvalidKnown_A	415471434	414531742	0	0
WreadyKnown_A	415471434	414531742	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	42293173	0	0
T1	817101	116366	0	0
T2	9543	4444	0	0
T3	3637	505	0	0
T4	519257	73942	0	0
T5	629	123	0	0
T6	792567	32675	0	0
T12	1242	106	0	0
T13	1154	106	0	0
T17	12568	5707	0	0
T18	4113	505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415471434	2358416	0	0
DepthKnown_A	415471434	414531742	0	0
RvalidKnown_A	415471434	414531742	0	0
WreadyKnown_A	415471434	414531742	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	2358416	0	0
T1	817101	6573	0	0
T2	9543	223	0	0
T3	3637	0	0	0
T4	519257	999	0	0
T5	629	0	0	0
T6	792567	0	0	0
T8	0	7802	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	0	0	0
T18	4113	0	0	0
T20	0	134	0	0
T21	0	11488	0	0
T25	0	15056	0	0
T31	0	7903	0	0
T54	0	12	0	0
T74	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415471434	3692493	0	0
DepthKnown_A	415471434	414531742	0	0
RvalidKnown_A	415471434	414531742	0	0
WreadyKnown_A	415471434	414531742	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	3692493	0	0
T1	817101	6573	0	0
T2	9543	223	0	0
T3	3637	0	0	0
T4	519257	999	0	0
T5	629	0	0	0
T6	792567	0	0	0
T8	0	7802	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	0	0	0
T18	4113	0	0	0
T20	0	240	0	0
T21	0	5120	0	0
T25	0	15056	0	0
T31	0	18329	0	0
T54	0	12	0	0
T74	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415471434	4127250	0	0
DepthKnown_A	415471434	414531742	0	0
RvalidKnown_A	415471434	414531742	0	0
WreadyKnown_A	415471434	414531742	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	4127250	0	0
T1	817101	6988	0	0
T2	9543	213	0	0
T3	3637	0	0	0
T4	519257	1078	0	0
T5	629	3	0	0
T6	792567	11696	0	0
T7	0	18640	0	0
T8	0	19406	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	246	0	0
T18	4113	0	0	0
T21	0	5120	0	0
T31	0	5632	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415471434	4943611	0	0
DepthKnown_A	415471434	414531742	0	0
RvalidKnown_A	415471434	414531742	0	0
WreadyKnown_A	415471434	414531742	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	4943611	0	0
T1	817101	6988	0	0
T2	9543	213	0	0
T3	3637	0	0	0
T4	519257	1078	0	0
T5	629	3	0	0
T6	792567	11696	0	0
T7	0	18640	0	0
T8	0	7899	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	246	0	0
T18	4113	0	0	0
T21	0	5120	0	0
T31	0	25295	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415471434	27139235	0	0
DepthKnown_A	415471434	414531742	0	0
RvalidKnown_A	415471434	414531742	0	0
WreadyKnown_A	415471434	414531742	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	27139235	0	0
T1	817101	102805	0	0
T2	9543	4008	0	0
T3	3637	505	0	0
T4	519257	71865	0	0
T5	629	120	0	0
T6	792567	20979	0	0
T12	1242	106	0	0
T13	1154	106	0	0
T17	12568	5461	0	0
T18	4113	505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415471434	33657069	0	0
DepthKnown_A	415471434	414531742	0	0
RvalidKnown_A	415471434	414531742	0	0
WreadyKnown_A	415471434	414531742	0	0
gen_passthru_fifo.paramCheckPass	1275	1275	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	33657069	0	0
T1	817101	102805	0	0
T2	9543	4008	0	0
T3	3637	505	0	0
T4	519257	71865	0	0
T5	629	120	0	0
T6	792567	20979	0	0
T12	1242	106	0	0
T13	1154	106	0	0
T17	12568	5461	0	0
T18	4113	505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415471434	414531742	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1275	1275	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T20,T21
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413288616	3664671	0	0
DepthKnown_A	413288616	412434372	0	0
RvalidKnown_A	413288616	412434372	0	0
WreadyKnown_A	413288616	412434372	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	413288616	3664671	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	3664671	0	0
T1	817101	6573	0	0
T2	9543	223	0	0
T3	3637	0	0	0
T4	519257	999	0	0
T5	629	0	0	0
T6	792567	0	0	0
T8	0	7802	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	0	0	0
T18	4113	0	0	0
T20	0	240	0	0
T21	0	5120	0	0
T25	0	15056	0	0
T31	0	18329	0	0
T44	0	84	0	0
T54	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	412434372	0	0
T1	817101	817011	0	0
T2	9543	9361	0	0
T3	3637	3000	0	0
T4	519257	519174	0	0
T5	629	568	0	0
T6	792567	792426	0	0
T12	1242	1038	0	0
T13	1154	922	0	0
T17	12568	12424	0	0
T18	4113	3491	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288616	3664671	0	0
T1	817101	6573	0	0
T2	9543	223	0	0
T3	3637	0	0	0
T4	519257	999	0	0
T5	629	0	0	0
T6	792567	0	0	0
T8	0	7802	0	0
T12	1242	0	0	0
T13	1154	0	0	0
T17	12568	0	0	0
T18	4113	0	0	0
T20	0	240	0	0
T21	0	5120	0	0
T25	0	15056	0	0
T31	0	18329	0	0
T44	0	84	0	0
T54	0	12	0	0